Freescale Semiconductor, Inc.

Transcription

1 nc. SEMICONDUCTOR TECHNICAL DATA Product Proposal 16-Bit Microcontroller PP Rev. 3, 12-May-04 Based on Motorola s market-leading flash technology, members of the deliver the power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive, general purpose Industrial and Automotive network applications. members are comprised of standard on-chip peripherals including a 16-bit central processing unit (CPU12), up to 128K bytes of Flash EEPROM or ROM, up to 4K bytes of RAM, an asynchronous serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer module (TIM), a 6-channel 8-bit Pulse Width Modulator (PWM), an 8-channel, 10-bit analog-to-digital converter (ADC) and up to one CAN 2.0 A, B software compatible module (MSCAN12). The has full 16-bit data paths throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O port bits are available with Wake-Up capability from STOP or WAIT mode. The is available in 48, 52 and 80 pin QFP packages, with the 80 Pin version pin compatible to the HCS12 B and D- Family derivatives. The C-Family includes ROM versions MC3S12C128/96/64/32/16 of all devices which provide a further cost reduction path for applications with high volume and stable code. Features 16-bit HCS12 CORE HCS12 CPU MMC (memory map and interface) INT (interrupt control) BDM (background debug mode) DBG12 (enhanced debug12 module including breakpoints and change-of-flow trace buffer) Multiplexed Expansion Bus (available only in 80 pin package version) 16-bit HCS12 CPU Upward compatible with M68HC11 instruction set Interrupt stacking and programmer s model identical to M68HC11 Instruction queue Enhanced indexed addressing Wake-up interrupt inputs Up to 10-port bits available for wake up interrupt function Memory options 16K, 32K, 64K, 96K and 128K Byte Flash EEPROM (erasable in 512-byte sectors) or 16K, 32K, 64K, 96K and 128K Byte ROM 2K and 4K Byte RAM Analog-to-Digital Converters One 8-channel module with 10-bit resolution. External conversion trigger capability Up to one 1M bit per second, CAN 2.0 A, B software compatible modules Five receive and three transmit buffers This document contains information on a new product. Specifications and information herein are subject to change without notice For More Information On This Product,

2 nc. Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for receive, transmit, error and wake-up Low-pass filter wake-up function Loop-back for self test operation Timer Module (TIM) 16-bit Counter with 7-bit Prescaler 8 programmable input capture or output compare channels Simple PWM Mode Modulo Reset of Timer Counter 16-Bit Pulse Accumulator External Event Counting Gated Time Accumulation 6 PWM channels Programmable period and duty cycle 8-bit 6-channel or 16-bit 3-channel Separate control for each pulse width and duty cycle Center-aligned or left-aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Serial interfaces One asynchronous serial communications interface (SCI) One synchronous serial peripheral interface (SPI) CRG (Clock Reset Generator Module) Windowed COP watchdog, Real time interrupt, Clock monitor, Clock generation Reset Generation Phase-locked loop clock frequency multiplier Limp home mode in absence of external clock Low power 0.5 to 16 MHz crystal oscillator reference clock Operation frequency 32MHz equivalent to 16MHz Bus Speed for single chip 32MHz equivalent to 16MHz Bus Speed in expanded bus modes Option: 50MHz equivalent to 25MHz Bus Speed Internal 2.5V Regulator Supports an input voltage range from 3.3V-10% to 5.5V Low power mode capability Includes low voltage reset (LVR) circuitry Includes low voltage interrupt (LVI) circuitry 48-Pin LQFP, 52-Pin LQFP or 80-Pin QFP package Up to 58 I/O lines with 5V input and drive capability Up to 2 dedicated 5V input only lines (IRQ, XIRQ) 5V A/D converter inputs and 5V I/O Development support Single-wire background debug mode (BDM) On-chip hardware breakpoints Enhanced DBG12 debug features 2 For More Information On This PRODUCT Product, PROPOSAL, Rev. 3, 12-May-04

3 nc. Table 1 List of members Flash ROM RAM Package Device CAN SCI SPI A/D PWM Timer I/O 48LQFP MC9S12C ch 6ch 8ch K 0 4K 52LQFP MC9S12C ch 6ch 8ch 35 80QFP MC9S12C ch 6ch 8ch 60 48LQFP MC9S12C ch 6ch 8ch 31 96K 0 4K 52LQFP MC9S12C ch 6ch 8ch 35 80QFP MC9S12C ch 6ch 8ch 60 48LQFP MC9S12C ch 6ch 8ch 31 64K 0 4K 52LQFP MC9S12C ch 6ch 8ch 35 80QFP MC9S12C ch 6ch 8ch 60 48LQFP MC9S12C ch 6ch 8ch 31 32K 0 2K 52LQFP MC9S12C ch 6ch 8ch 35 80QFP MC9S12C ch 6ch 8ch 60 32K 0 2K 48LQFP MC9S12GC ch 6ch 8ch 31 52LQFP MC9S12GC ch 6ch 8ch 35 16K 0 2K 48LQFP MC9S12GC ch 6ch 8ch 31 52LQFP MC9S12GC ch 6ch 8ch 35 48LQFP MC3S12C ch 6ch 8ch K 4K 52LQFP MC3S12C ch 6ch 8ch 35 80QFP MC3S12C ch 6ch 8ch 60 48LQFP MC3S12C ch 6ch 8ch K 4K 52LQFP MC3S12C ch 6ch 8ch 35 80QFP MC3S12C ch 6ch 8ch 60 48LQFP MC3S12C ch 6ch 8ch K 4K 52LQFP MC3S12C ch 6ch 8ch 35 80QFP MC3S12C ch 6ch 8ch 60 48LQFP MC3S12C ch 6ch 8ch K 2K 52LQFP MC3S12C ch 6ch 8ch 35 80QFP MC3S12C ch 6ch 8ch K 2K 48LQFP MC3S12GC ch 6ch 8ch 31 52LQFP MC3S12GC ch 6ch 8ch K 2K 48LQFP MC9S12GC ch 6ch 8ch 31 52LQFP MC9S12GC ch 6ch 8ch 35 Pin out explanations: I/O is the sum of ports capable to act as digital input or output. For 80 Pin Versions: Port A = 8, B = 8, E = input only, J = 2, M = 6, P = 8, S = 4, T = 8, PAD = inputs provide Interrupt capability (P= 8, J = 2, IRQ, XIRQ) For 52 Pin Versions: Port A = 3, B = 1, E = input only, M = 6, P = 3, S = 2, T = 8, PAD = 8. 5 inputs provide Interrupt capability (P= 3, IRQ, XIRQ) For 48 Pin Versions: Port A = 1, B = 1, E = input only, M = 6, P = 1, S = 2, T = 8, PAD = 8. 3 inputs provide Interrupt capability (P= 1, IRQ, XIRQ) PRODUCT PROPOSAL, Rev. For 3, 12-May-04 More Information On This Product, 3

4 nc. VSSR VDDR VDDX VSSX VDD2 VSS2 VDD1 VSS1 BKGD XFC VDDPLL VSSPLL EXTAL XTAL RESET PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 TEST/VPP Multiplexed Wide Bus Voltage Regulator 32K, 64K, 96K, 128K Byte Flash/ROM 2K, 4K Byte RAM Single-wire Background Debug12 Module PLL PTE DDRE PA7 PA6 ADDR15 ADDR14 DATA15 DATA14 Clock and Reset Generation Module XIRQ IRQ R/W LSTRB/TAGLO ECLK MODA/IPIPE0 MODB/IPIPE1 NOACC/XCLKS HCS12 CPU COP Watchdog Clock Monitor Periodic Interrupt System Integration Module (SIM) Multiplexed Address/Data Bus DDRA PTA PA5 PA4 PA3 PA2 PA1 PA0 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 Internal Logic 2.5V VDD1,2 VSS1,2 PB7 PB6 ADDR7 ADDR6 DATA7 DATA6 DDRB PTB PB5 PB4 PB3 PB2 PB1 PB0 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 I/O Driver 5V VDDX VSSX ATD Timer Module PWM Module SCI MSCAN SPI IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PW0 PW1 PW2 PW3 PW4 PW5 RXD TXD RXCAN TXCAN MISO SS MOSI SCK VDDA VSSA VRH VRL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 MUX DDRAD PTAD DDRT PTT Keypad Interrupt DDRP PTP Key Int DDRJ PTJ DDRS PTS DDRM PTM VDDA VSSA VRH VRL PAD0 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PP0 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PJ6 PJ7 PS0 PS1 PS2 PS3 PM0 PM1 PM2 PM3 PM4 PM5 Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package PLL 2.5V VDDPLL VSSPLL A/D Converter 5V VDDA VSSA VRL is bonded internally to VSSA for 52 and 48 Pin packages Voltage Regulator 5V & I/O VDDR VSSR Figure 1 Block Diagram 4 For More Information On This PRODUCT Product, PROPOSAL, Rev. 3, 12-May-04

5 nc. $0400 $3000 $03FF $3FFF $3000 1K Register Space Mappable to any 2K Boundary 4K Bytes RAM $4000 $3FFF $4000 Mappable to any 4K Boundary NORMAL EXT EXPANDED SPECIAL $7FFF $BFFF BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: - $03FF: Register Space - $0FFF: 4K RAM (only 3K visible $ $0FFF) Flash Erase Sector Size is 1024 Bytes Figure 2 MCxS12C128 User Configurable Memory Map 16K Page Window 8 * 16K Flash EEPROM/ROM Pages PRODUCT PROPOSAL, Rev. For 3, 12-May-04 More Information On This Product, 5

6 nc. $0400 $3000 $03FF $3FFF $3000 1K Register Space Mappable to any 2K Boundary 4K Bytes RAM $4000 $3FFF $4000 Mappable to any 4K Boundary NORMAL EXT EXPANDED SPECIAL $7FFF $BFFF BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: - $03FF: Register Space - $0FFF: 4K RAM (only 3K visible $ $0FFF) Flash Erase Sector Size is 1024 Bytes Figure 3 MCxS12C96 User Configurable Memory Map 16K Page Window 6 * 16K Flash EEPROM/ROM Pages 6 For More Information On This PRODUCT Product, PROPOSAL, Rev. 3, 12-May-04

7 nc. $0400 $3000 $03FF $3FFF $3000 1K Register Space Mappable to any 2K Boundary 4K Bytes RAM $4000 $3FFF $4000 Mappable to any 4K Boundary NORMAL EXT EXPANDED SPECIAL $7FFF $BFFF BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: - $03FF: Register Space - $0FFF: 4K RAM (only 3K visible $ $0FFF) Flash Erase Sector Size is 512 Bytes Figure 4 MCxS12C64 User Configurable Memory Map 16K Page Window 4 * 16K Flash EEPROM/ROM Pages PRODUCT PROPOSAL, Rev. For 3, 12-May-04 More Information On This Product, 7

8 nc. $0400 $03FF 1K Register Space Mappable to any 2K Boundary $3800 $3800 2K Bytes RAM $4000 $3FFF Mappable to any 2K Boundary NORMAL EXT EXPANDED SPECIAL $BFFF BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: - $03FF: Register Space $ $0FFF: 2K RAM Flash Erase Sector Size is 512 Bytes Figure 5 MCxS12C32 User Configurable Memory Map 16K Page Window 2 * 16K Flash EEPROM/ROM Pages 8 For More Information On This PRODUCT Product, PROPOSAL, Rev. 3, 12-May-04

9 nc. $0400 $03FF 1K Register Space Mappable to any 2K Boundary $3800 $3800 2K Bytes RAM $4000 $3FFF Mappable to any 2K Boundary NORMAL EXT EXPANDED SPECIAL $BFFF BDM (If Active) The figure shows a useful map, which is not the map out of reset. After reset the map is: - $03FF: Register Space $ $0FFF: 2K RAM Flash Erase Sector Size is 512 Bytes Figure 6 MCxS12C16 User Configurable Memory Map 16K Page Window 1 * 16K Flash EEPROM/ROM Page PRODUCT PROPOSAL, Rev. For 3, 12-May-04 More Information On This Product, 9

10 nc. PP4/KWP4/PW4 PP5/KWP5/PW5 PP7/KWP7 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PJ6/KWJ6 PJ7/KWJ7 PP6/KWP6/ROMONE PS3 PS2 PS1/TXD PS0/RXD VSSA VRL PW3/KWP3/PP3 PW2/KWP2/PP2 PW1/KWP1/PP1 PW0/KWP0/PP0 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB QFP ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 XCLKS/NOACC/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST/VPP LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 Signals shown in Bold are not available on the 52 or 48 Pin Package Signals shown in Bold Italic are available in the 52, but not the 48 Pin Package VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 VSS2 VDD2 PA7/ADDR15/DATA15 PA6/ADDR14/DATA14 PA5/ADDR13/DATA13 PA4/ADDR12/DATA12 PA3/ADDR11/DATA11 PA2/ADDR10/DATA10 PA1/ADDR9/DATA9 PA0/ADDR8/DATA8 Figure 7 Pin Assignments in 80 QFP for!!! Pin-out is Subject to Change!!! 10 For More Information On This PRODUCT Product, PROPOSAL, Rev. 3, 12-May-04

11 nc. PP4/KWP4/PW4 PP5/KWP5/PW5 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PS1/TXD PS0/RXD VSSA PW3/KWP3/PP3 PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB QFP XCLKS/PE7 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST/VPP IRQ/PE1 XIRQ/PE * Signals shown in Bold are not available on the 48 Pin Package VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 PA2 PA1 PA0 Figure 8 Pin assignments 52 QFP for PRODUCT PROPOSAL, Rev. For 3, 12-May-04 More Information On This Product, 11

12 nc. PP5/KWP5 VDDX VSSX PM0/RXCAN PM1/TXCAN PM2/MISO PM3/SS PM4/MOSI PM5/SCK PS1/TXD PS0/RXD VSSA PW0/IOC0/PT0 PW1/IOC1/PT1 PW2/IOC2/PT2 PW3/IOC3/PT3 VDD1 VSS1 PW4/IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 MODC/BKGD PB LQFP XCLKS/PE7 ECLK/PE4 VSSR VDDR RESET VDDPLL XFC VSSPLL EXTAL XTAL TEST/VPP IRQ/PE1 Figure 9 Pin Assignments in 48 LQFP for VRH VDDA PAD07/AN07 PAD06/AN06 PAD05/AN05 PAD04/AN04 PAD03/AN03 PAD02/AN02 PAD01/AN01 PAD00/AN00 PA0 XIRQ/PE0 12 For More Information On This PRODUCT Product, PROPOSAL, Rev. 3, 12-May-04

13 Package mechanical information nc. B 9 1 T B1 12 AB AC 4X 4X AB T-U A1 48 A AC T-U Z Z Z S1 S BASE METAL F D G N M AC T-U Z SECTION AE-AE J AD 36 U 25 V1 DETAIL Y V AC C H E AE P DETAIL Y M TOP & BOTTOM DETAIL AD W AE T, U, Z K AA NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 2. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 3. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 4. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 5. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 6. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED R MILLIMETERS DIM MIN MAX A BSC A BSC B BSC B BSC C D E F G BSC H J K L 0 7 M 12 REF N P BSC R S BSC S BSC V BSC V BSC W REF AA REF L GAUGE PLANE Figure pin LQFP Mechanical Dimensions (case no ISSUE F) PRODUCT PROPOSAL, Rev. For 3, 12-May-04 More Information On This Product, 13

14 nc. 4X X 13 TIPS 0.20 (0.008) H L-M N 0.20 (0.008) T L-M N -X- X=L, M, N 1 39 C L -L- 3X VIEW Y -M- AB AB G B V VIEW Y B1 V1 PLATING F BASE METAL J U C A1 S1 C2 -N- A S 4X θ2 4X θ (0.002) S C1 VIEW AA -H- -T- SEATING PLANE W θ1 K E Z 0.10 (0.004) T VIEW AA 2X R R (0.010) θ GAGE PLANE D 0.13 (0.005) M T L-M S N S SECTION AB-AB ROTATED 90 CLOCKWISE NOTES: 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER 4. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 5. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 6. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 7. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H- 8. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND MILLIMETERS INCHES DIM MIN MAX MIN MAX A BSC BSC A BSC BSC B BSC BSC B BSC BSC C C C D E F G 0.65 BSC BSC J K 0.50 REF REF R S BSC BSC S BSC BSC U V BSC BSC V BSC BSC W 0.20 REF REF Z 1.00 REF REF θ θ θ2 12 REF 12 REF θ3 12 REF 12 REF Figure pin LQFP Mechanical Dimensions (case no. 848D-03) 14 For More Information On This PRODUCT Product, PROPOSAL, Rev. 3, 12-May-04

15 nc. L L -A- DETAIL A B 0.20 M H A-B S D S 0.05 D V 0.20 M C A-B S D S B B DETAIL A P -B- -A-,-B-,-D- DATUM PLANE C -H- -H- E 80 H D- A 0.20 M H A-B S D S 0.05 A-B S G DETAIL C 0.20 M C A-B S D S W X K U T R Q M M 21 DETAIL C -C- SEATING PLANE DATUM PLANE 0.10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -A-, -B- AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. J F SECTION B-B VIEW ROTATED 90 N D 0.20 M C A-B S D S MILLIMETERS DIM MIN MAX A B C D E F G 0.65 BSC H J K L REF M 5 10 N P BSC Q 0 7 R S T U V W X 1.6 REF Figure pin QFP Mechanical Dimensions (case no. 841B) PRODUCT PROPOSAL, Rev. For 3, 12-May-04 More Information On This Product, 15

16 nc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters can and do vary in different applications. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado HOME PAGE: JAPAN: Motorola Japan Ltd.; SPS, Technial Information Center, , Minami-Azabu, Minato-ku, Tokyo Japan ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong CUSTOMER FOCUS CENTER: Motorola, 2004 For More Information On This Product,

17 This datasheet has been download from: Datasheets for electronics components.