Low Power Dissipation Model Analysis for Embedded

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1 Low Power Dissipation Model Analysis for Embedded Systems Yang-Hsin Fan Dept. of Computer Science and Information Engineering National Taitung University 684. Sec. 1, Chunghua Rd., Taitung City, 95002, Taiwan Jan-Ou Wu Dept. of Electronic Engineering De Lin Institute of Technology 1. Ln. 380, Qingyun Rd., Tucheng Dist, New Taipei City 23654, Taiwan #112 San-Fu Wang Dept. of Electronic Engineering Ming Chi University of Technology 84 Gungjuan Rd., Taishan Dist. New Taipei City 24301, Taiwan #4867 ABSTRACT Embedded systems serve diverse functionalities to meet the requirement for computer, communication equipment, consumer electronics and car (4C) products. It results the need of embedded systems to exponential growth. While hundreds of thousand embedded systems run on every corner of daily life, the consumed power consumption is extremely huge. As a result, embedded systems consumed low power consumption become a significantly issue. This study presents model analysis approach to obtain low power consumption for embedded systems. First, embedded systems are divided into a set of tasks that are implemented with hardware circuits and software applications. Second, various models with same tasks combination and height of tree of embedded system are analyzed for power dissipation. Next, dynamic and static power consumption for each task is measured for further calculating to gain an embedded system with low power dissipation. Four, we present a schema via formula for various models to fast assessing the consumed power consumption for embedded systems. Finally, the effectiveness of the proposed approach is demonstrated by assessing an adaptive pulse code modulation (ADPCM) system. Categories and Subject Descriptors C.3 [Computer Systems Organization]: Special-Purpose and Application-Based Systems real-time and embedded systems, microprocessor/microcomputer applications. General Terms Theory, Experimentation. Keywords Low power consumption, Power saving, Embedded system. 1. INTRODUCTION Recently, low power consumption of embedded systems become significant issue owing that the energy of earth is gradually consumed. The worst affected products include computer, communications equipment, consumer electronics and car, etc. In the energy shortage era, the Intel Company predicts that 15 billion embedded products will surf to internet in year Once those products simultaneously serve, energy dissipation must be rapidly raised even used up if power saving or energy efficient improvement is not achieved. Executing task inside embedded systems consume power consumption. The states of task categories power dissipation into dynamic and static power consumption. Dynamic power consumption happens while task is performed. On the other hand, task consumes static power dissipation when its states being idle. For embedded system insides n tasks, executing task 1 results that consume dynamic power consumption and the other tasks arise static power consumption. In consideration task 2 runs, it consumes dynamic power consumption and task 1, task 3, task 4 to task n occur static power consumption. To iterate the process for every task execution, the power consumption of embedded system can be assessed. From these evaluating designs, the lowest power consumption of embedded system can be determined. 2. PRELIMINARY WORK Smarter, smaller and portable characteristics make embedded systems to serve the functions becoming diversity. The products reside embedded systems that spread over computer, communication, consumer and car (4C). However, the more embedded systems serve, the more power dissipation consumed. For minimizing the CPU power consumption for real time embedded system, Vîlcu [1] first studies task execution in the power consumption of processor(s). Then, he finds the affection of optimal configuration processor(s) for energy consumption. Finally, he defines globally optimal scheduling which gains minimal energy consumption for homogeneous multiprocessor system. Silva-Filho and Lima [2] state memory hierarchy consumes power up to 50% in microprocessor system. Consequently, they propose an automated architecture exploration mechanism to NIOS II processor and memory hierarch with parameter variation. Experimental results show the reduction of energy consumption near to 27%. In 2008, Zeng et al. [3] present generalized dynamic energy performance scaling (DEPS) framework to hard real-time embedded systems for exploring application-specific energy-saving potential issue. Three energy performance tradeoff technologies called DHRC, DVFS and DPM are integrated into DEPS. Experiment results of simulation show the static DEPS improves 13.6% and 13.7% in DVFS and DHRC, respectively. Also, dynamic DEPS improves 5.7% than static DEPS. Qiu et al. [4] discuss the execution time of tasks with conditional instructions or operations problem. They adopt probabilistic random variable approach to model execution time of tasks. Then, Research Notes in Information Science (RNIS) Volume13,May 2013 doi: /rnis.vol

2 they propose practical algorithm VACP to minimize energy consumption for uniprocessor embedded systems. Gao et al. [5] present energy-efficient architecture for embedded software (EAES) and dynamic energy-saving method to solve energysaving problem. The former uses a processor with dynamic voltage scaling capability, FPGA modules and extends directed acyclic graph to embedded system. The latter adopts preassignment to achieve dynamic runtime scheduling and minimizing energy consumption. Real-time power information is a valuable data for software designer for battery-powered embedded systems. Genser et al. [6] propose power profiling approach to collect real-time power information at early design stages. Moreover, they present an emulation-based power profiling approach to achieve real-time power analysis for embedded systems. Because of the power information is collected at early design stages, the development efficiency and time-to-market is improved. In 2008, Elewi et al. [7] first discuss the real time scheduling of dependent tasks problem and then present enhanced multi-speed (MS) algorithm for energy saving. With energy consumption problem of battery-powered embedded systems, Casares et al. [8] aim embedded smart camera to analyze the power consumption and performance. Not only graph of energy consumption but also instruction of collections is presented. They conclude the important of lightweight algorithm, the time of transfer data and transferred data type. 3. LOW POWER MODEL ANALYSIS Modern embedded system executes sequentially a set of tasks to provide multimedia, social network and diverse applications. Performing these tasks consume a lot of power energy that depend on the deploying architecture of embedded system. In order to design embedded system with low power dissipation or power saving, minimizing power dissipation for every task is one intuitive approach. Each task consume individually the power dissipation that affect the design becomes low power dissipation products or power saving equipment. Consequently, the candidate of tasks combination for embedded system becomes a significant issue. According to the hardware-software codesign theory, the candidate of tasks is either hardware circuits or software applications. As a result, the degree of power consumption that depends on the power dissipation with designed tasks with implementation via hardware circuits or software applications. Tree topology is generally used to analysis the power dissipation for embedded systems. It consists of node, arc, control and data flow, height and level. Figure 1 shows two tree topologies called M and N of embedded system with 7 tasks. The embedded system executes task from node 1. Then, it departs for next nodes that depend on the arcs after run a period of time. The arc connect sink and destination node. It is used to exhibit the control and data flow. Another terminology in tree topology called height, H, of tree that is used to exhibit the architecture for embedded systems. The other terminology named level, L, is used to indicate the control or data flow in specific time for embedded systems. We apply tree topology to model embedded system and then further to analysis their power consumption. From the appearance of view, Figure 1(a) and (b) are two kinds of design of topology for embedded system. Both of them are consist of 7 nodes, some arcs, control and data flow and levels. In particular, it is as same as H in two tree topology. Besides, level 1 to 3 happen the control or data flow in time t 1, t 2 and t 3. Embedded systems consume dynamic or static power consumption that depends on the status for task. Dynamic power consumption D occurs while task is executed. On the contrary, the (a) M topology (b) N topology Figure 1. Two tree topologies of embedded system with 7 tasks. idle status of task consumes static power consumption S. For example, task 1 of Figure 1(a) in time t 1 is working for a particular function resulting it dissipates D. At the same time, tasks 2 to 7 dissipate S since they are idle in t 1. Similarly, task 2 consumes D in time t 2 and task 1 and tasks 3 to 7 dissipate static power consumption. On time t 3, task 3 to 7 consumes D and task 1 and 2 dissipate S. Based on the stated rules, any topology of embedded systems can be analysis for their total power consumption for assessment. Figure 2 demonstrates M topology with 7 tasks, height and level as 3. Labels D and S beside tasks indicate dynamic and static power consumption. We analyze power consumption via the order of level in the following. Figure 2(a) shows the power consumption model analysis for level 1. Label D besides task H in level 1 is marked and the other tasks on level 2 and 3 are marked in symbol S. Such results imply dynamic and static power consumption happen simultaneously upon whole embedded system. Figure 2(b) displays the analysis for power consumption in level 2. Label D next to task S is marked and the other tasks are marked with symbol S. Similarly, the power dissipation in level 3 is discussed in Figure 2(c). Five tasks named H, S, H, H and S in level 3 next to label D are marked and tasks located on level 1 and 2 are marked with symbol S. Figure 2(d) exhibits the total power consumption for M topology. Another model referred to topology shown in Figure 3 is introduced in the following. It characteristics include 7 tasks, the height and level as 3, the number of tasks with H and S is as same as Figure 2. In other words, both topology M and N have four H and three S. The power consumption model analysis adopts stated steps and approach. First, we analyse the power consumption for Figure 3(a) for level l. We label D next to task H in level 1 and the (a) power consumption (c) power consumption (b) power consumption (d) Total power consumption Figure 2. Power consumption model analysis for M topology. 185

3 (a) power consumption (c) power consumption (b) power consumption (d) Total power consumption Figure 3. Power consumption model analysis for N topology. other tasks on level 2 and level 3 are marks S. Figure 3(b) presents the power dissipation for level 2. Symbol D next two tasks named S and H in level 2 are marked and the other tasks in level 1 and level 3 are marked with label S. Figure 3(c) aims level 3 to discuss. Four tasks, S, H, H and S, are marked with D in level 3 and tasks locate in level 1 and 2 are marks with S. After every level of embedded system is analyzed, the total power consumption for topology N is shown in Figure 3(d). According to Figure 2(d) and Figure 3(d), we conclude topology M dissipates the same power consumption as topology N. i.e., both topology consume total power consumption as one dynamic power consumption, D, and two static power consumption, S for each node. Such conclusion can be applied to other topology of embedded systems. As a result, we summary the sum of power consumption for embedded system in Equation (1). It consists of the levels of tree, L, a set of static power consumption P s,t1, P s,t2,, P s,tn and dynamic power consumption P d,t1, P d,t2,, P d,tn for each node. P= (L 1) P, + P, + + P, + P, + P, + + P, where L is the height of tree, P s is static power consumption, P d is dynamic power consumption, t 1, t 2,, t n is a set of tasks (1) Table 1. Measured data of tasks for ADPCM system. Application ADPCM Tasks system Encoder Decoder H/W (mw) Power Consumption S/W (mw) Dynamic Static Dynamic Static T a T b T c T d T e T f The experiments are set to five scenarios which depend on the number of tasks with implementation by hardware circuits and software applications. These five scenarios are different to the number of hardware tasks and software tasks. The first scenario is that embedded system implement with five hardware tasks (i.e ) and one software task (i.e. 0) and level as 6. Figure 4 illustrates the power dissipation of ADPCM with six designs with five hardware tasks and one software task. There are six kinds of designs that are , , , , and Experimental results display the implementation with which gains low power consumption as 6.01mW. On the contrary, the design of consumes the most power consumption as 6.055mW. The second scenario is that embedded system implement with four hardware tasks (i.e. 1111) and two software tasks (i.e. 00) and level as 6. Figure 5 displays these designs with four hardware tasks, two software tasks and level as 6. It has 15 types of combinations while develop an embedded system. The lowest power dissipation is mW which are developed via a set of tasks with On the other hand, the most power consumption of design as that consume mW. The third scenario is that embedded system implement with three hardware tasks (i.e. 111) and three software tasks (i.e. 000) and level as 6. Figure 6 demonstrates these embedded systems that comprises of three hardware and software tasks and level as 6. There are totally 20 types to complete the designs. Experimental results indicate the lowest power consumption as mW which tasks are made of In contrast, the most power dissipation as design that consumes mW. 4. EXPERIMENTAL RESULTS This study is evaluated by adaptive pulse code modulation (ADPCM) system which is comprised of encoder and decoder modules. The encoder module consists of four tasks namely T a, T b, T c and T d. On the other hand, two tasks called T e and T f are designed for decoder module. Each task is implemented separately to hardware and software form by using Verilog and C language. The measured data of each task includes dynamic and static power consumption with implementation of hardware circuits and software applications. Table 1 shows the measured data for T a to T f. Figure 4. Power dissipation of ADPCM embedded system with five hardware tasks and one software task. 186

4 The fourth scenario is that embedded system implement with two hardware tasks (i.e. 11) and four software tasks (i.e. 0000) and level as 6. Figure 7 illustrates the 15 results that consist of two hardware circuits and four software applications. Among 15 designs, the embedded system with performance gains low power consumption as mW. On the contrary, the design of consumes the most power consumption as mW. Finally, the fifth scenario is that embedded system implement with one hardware task (i.e. 1) and five software tasks (i.e ) and level as 6. Figure 8 exhibits the outcomes which comprise of one hardware circuit and five software applications. The lowest power consumption is made up of design. It consumes power dissipation as mW. In contrast, the design with consumes the power dissipation as mW. Figure 5. Power dissipation of ADPCM embedded system with four hardware tasks and two software tasks. Figure 6. Power dissipation of ADPCM embedded system with three hardware and software tasks. Figure 7. Power dissipation of ADPCM embedded system with two hardware tasks and four software tasks. Figure 8. Power dissipation of ADPCM embedded system with one hardware task and five software tasks. 5. CONCLUSIONS This study aims for power consumption of embedded systems to achieve the low power dissipation design. We categorize tasks into hardware or software form with corresponding to implementation by hardware circuits or software applications. Each task consumes dynamic and static power consumption that is taken into account. Then, we present various models with same tasks combination and height of tree of embedded system to gain low power consumption. Based on the proposed approach of low power model analysis, embedded system with minimizing the power consumption can be determined among diverse designs. Experimental results of ADPCM prove the effectiveness for gaining low power consumption of embedded systems that apply low power model analysis approach. 6. ACKNOWLEDGMENTS The authors would like to thank the National Science Council of the Republic of China, Taiwan, for financially supporting this research under Contract No. NSC E REFERENCES [1] D. Vilcu Real time scheduling and CPU power consumption in embedded systems. In Proceeding of the IEEE International Conference on Automation, Quality and Testing, Robotics (Cluj-Napoca, Romania, May 22 25, 2008). IEEE, DOI= /AQTR [2] Silva-Filho, A.G., and Lima, S.M.L Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor. In Proceeding of the IEEE International SOC Conference (Newport Beach, CA, USA, September 17 20, 2008). IEEE, DOI= /SOCC [3] G. Zeng, H. Tomiyama, H. Takada, and T. Ishihara A generalized framework for system-wide energy savings in hard real-time embedded systems. In Proceeding of the IEEE/IFIP International Conference on Embedded and Ubiquitous Computing (Shanghai, China, December 17 20, 2008). IEEE, DOI= /EUC [4] M. Qiu, J. Wu, F. Hu, S. Liu, and L. Wang Voltage assignment for soft real-time embedded systems with continuous probability distribution. In Proceeding of the IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (Beijing, China, August 24-26, 2009). IEEE, DOI= /RTCSA [5] Z. Gao, G. Dai, P. Liu, and P. Zhang Energy-efficient architecture for embedded software with hard real-time 187

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