AN SMSC LAN8700 User Application and Configuration Guide. 1 Introduction. 1.1 Reference Documents

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1 AN SMSC LAN8700 User Application and Configuration Guide 1 Introduction This application note contains guidelines for the successful configuration and implementation of the LAN8700(i). It contains good general design practices as well as specific requirements of the LAN8700(i). It contains a list of product features, circuit design requirements, and a FAQ section. The LAN8700 is the commercial temperature version of the part, the LAN8700i is the Industrial temperature version of the part. The LAN8700(i) name refers to either the commercial temperature version or the industrial temperature version or both unless otherwise specified. 1.1 Reference Documents The following documents are referred to in this application note: 1. SMSC LAN8700(i) Datasheet ( 2. SMSC LAN8700 MII Reference Design ( 3. SMSC LAN8700 RMII Reference Design ( 4. SMSC LAN8700-LV MII Reference Design ( 5. SMSC LAN8700-LV RMII Reference Design ( 6. SMSC Application Note AN Suggested Magnetics ( 7. SMSC Application Note AN Parallel Crystal circuit Input Voltage Control ( 8. SMSC LAN8700/LAN8700I and LAN8187/LAN8187I Ethernet PHY Layout Guidelines ( 9. SMSC Magneticless Configuration Options for SMSC LAN Devices 10. EVB8700 User Manual 11. Schematic Checklist for the SMSC LAN8700(i) Please note that it is important to always refer to the SMSC LAN8700(i) Datasheet and LAN8700(i) Reference Designs for complete and current information regarding the LAN8700 Design. Additionally, the circuit examples shown in this document are for illustrative purposes only. Please reference the LAN8700(i) Reference Design Schematic when Implementing actual circuits in your design. Please visit SMSC s website at for the latest updated documentation. SMSC AN Revision 0.3 ( )

2 2 Configuration Options 2.1 MII vs RMII Mode The LAN8700 must be configured to support the MII or RMII bus for connectivity to the MAC. This configuration is done through the COL/RMII/CRS_DV pin. MII or RMII mode selection is latched on the rising edge of the reset input (nrst) based on the strapping of the COL/RMII/CRS_DV pin. To select MII mode, float the COL/RMII/CRS_DV pin. To select RMII mode, pull the pin high with an external resistor to VDDIO. Most of the MII and RMII pins are multiplexed. Table 2.1, "MII/RMII Signal Mapping", shown below, describes the relationship of the related device pins to what pins are used in MII and RMII mode. Table 2.1 MII/RMII Signal Mapping SIGNAL NAME MII MODE RMII MODE TXD0 TXD0 TXD0 TXD1 TXD1 TXD1 TX_EN TX_EN TX_EN RX_ER/ RXD4 RX_ER/ RXD4/ RX_ER Note 2.2 COL/RMII/CRS_DV COL CRS_DV RXD0 RXD0 RXD0 RXD1 RXD1 RXD1 TXD2 TXD2 Note 2.1 TXD3 TXD3 Note 2.1 TX_ER/ TXD4 CRS RX_DV RXD2 RXD3/ nintsel TX_CLK RX_CLK TX_ER/ TXD4 CRS RX_DV RXD2 RXD3 TX_CLK RX_CLK CLKIN/XTAL1 CLKIN/XTAL1 REF_CLK Note 2.1 Note 2.2 In RMII mode, this pin needs to tied to VSS. The RX_ER signal is required by the PHY, but it is optional for the MAC. The MAC can choose to ignore or not use this signal. Revision 0.3 ( ) 2 SMSC AN 16.12

3 2.2 Variable VDDIO The Digital I/O pins on the LAN8700 are variable voltage to take advantage of low power savings from shrinking technologies. These pins can operate from a low I/O voltage of +1.8V-10% up to +3.3V+10%. Due to this low voltage feature addition, the system designer needs to take the following sections into consideration. Boot strapping configuration, I/O voltage stability, and LED illumination Boot Strapping Configuration. Due to a lower I/O voltage, a lower strapping resistor needs to be used to ensure the strapped configuration is latched into the PHY device at power-on reset. Table 2.2 Boot Strapping Configuration Resistors I/O VOLTAGE PULL-UP/PULL-DOWN RESISTOR 3.0 to k ohm resistor 2.0 to k ohm resistor 1.6 to 2.0 5k ohm resistor I/O Voltage Stability The I/O voltage the System Designer applies on VDDIO needs to maintain its value with a tolerance of ± 10%. Varying the voltage up or down, after the PHY has completed power-on reset can cause errors in the PHY operation LED illumination The wavelength of the light emitted, and therefore its color, depends on the band gap energy of the materials forming the p-n junction. In silicon or germanium diodes, the electrons and holes recombine by a non-radiative transition which produces no optical emission, because these are indirect bandgap materials. The materials used for an LED have a direct band gap with energies corresponding to near infrared, visible or near-ultraviolet light. The voltage drop for various color LEDs is shown in Table 2.3. Table 2.3 Minimum Voltage Potentials Required for Different LED Colors COLOR POTENTIAL DIFFERENCE Red 1.8V to 2.1V Orange 2.2V Yellow 2.4V Green 2.6V Blue 3.0V to 3.5V White 3.0V to 3.5V The system designer needs to take into consideration how they are configuring the LEDs to operate. At lower IO voltages, the PHY device output LED signals may not have enough potential to properly illuminate an LED. SMSC AN Revision 0.3 ( )

4 With a Variable IO voltage configured above 2.6V, the LED is driven by the LED output signal to either VSS or VDDIO. When VDDIO is above 2.6V output, the Green, Yellow, Orange, and Red LEDs will operate because the potential across it is greater than their required potential. When the IO voltage drops down below 2.6V, the voltage potential across the Green LED will be under the minimum required to activate the band gap of the LED. Therefore it will not turn on as the voltage potential across the LED is not high enough. To fix this issue, connect the LED to the 3.3V power and change the PHY LED output so that its always active low. This will bring a 3.3V voltage potential across the LED when the LED output signal goes active low. When the output LED signal deactivates and goes high, the output will be 1.8V, and v will be 1.5V and the led will not turn on. 2.3 Internal +1.8V Regulator Part of the flexpwr TM technology is the ability to disable the internal +1.8V regulator. This further increases the power savings as a more efficient external switching regulator can provide the necessary +1.8V to the internal PHY circuitry. A 4.7uF low ESR and 0.1uF capacitor must always be added to VDD_CORE and placed close to the PHY. This capacitance provides decoupling to the power supply noise and ensures stability of the internal regulator Disable the Internal +1.8V Regulator To disable the +1.8v internal regulator, a pullup strapping resistor is attached from RXCLK/REGOFF to VDDIO. When both VDDIO and VDDA are within specification, the PHY will sample the RXCLK/REGOFF pin to determine if the internal regulator should turn on. If the pin is pulled up to VDDIO and sampled above VIH, then the internal regulator is off, and the system needs to supply +1.8V ± 10% to the VDD_CORE pin Enable the Internal +1.8V Regulator By default the RXCLK/REGOFF pin is left floating to enable the internal +1.8V regulator. Leaving the pin floating lets the internal resistor strap the regulator on. During VDDIO and VDDA power-on, if the REGOFF pin is sampled below VIL, then the internal +1.8V regulator will turn on and run from the VDD33 pin. 2.4 MODE[2:0] Pins The Mode[2:0] pins control the Mode of the PHY after power-on-reset. By default the internal resistors on each pin will pull the mode configuration high and set the mode to 111, which is all capable, Autonegotiation. To activate an alternative mode you can boot-strap the MODE pins by adding resistors to each corresponding pin. For example, to bootup the PHY in 100base-TX Full Duplex Auto-negotiation disabled, you could add a 10k Pull-down to Mode2 pin, which will result in the mode bits getting set to 011, this corresponds to 100Base-TX Full Duplex. Auto-negotiation disabled. Revision 0.3 ( ) 4 SMSC AN 16.12

5 Table 2.4 MODE[2:0] Bus PINS MODE2 MODE1 MODE0 MODE[2:0] REGISTER MODE DEFINITIONS AUTO NEGOTIATION DUPLEX (internal pull-up) (internal pull-up) (internal pull-up) 111 All capable Enabled Full and Half (internal pull-up) (internal pull-up) 110 Power Down mode (internal pull-up) (internal pull-up) 101 Repeater mode Enabled Advertise half duplex (internal pull-up) Base-TX Half Duplex Auto Negotiation Enabled Full and Half (internal pull-up) (internal pull-up) Base-TX Full Duplex Disabled Full (internal pull-up) Base-TX Half Duplex. Disabled Half (internal pull-up) Base-T Full Duplex Disabled Full Base-T Half Duplex Disabled Half All Capable Mode No external strapping resistors are added to the MODE pins. This is the default mode for the PHY and enables auto negotiation with the link partner. This is the recommended configuration for most applications Power Down Mode When the PHY is Boot-Strapped into this mode, with a pulldown resistor to VSS on MODE0 pin, the PHY will power-up with bit 11 of register 0 set to a 1. In this mode the entire PHY, except the management interface, is powered-down and stays in that condition as long as bit 0.11 is HIGH. When bit 0.11 is cleared, the PHY powers up and is automatically reset into All Capable mode Repeater Mode Adding a strapping resistor to VSS on MODE1 pin will configure the PHY device to run in Repeater Mode after reset. AutoNegotiation is enabled with 100Base-TX Half Duplex advertised. CRS is active only during Receive Base-TX Half Duplex AutoNegotiation To enable this mode, add a resistor to VSS on both Mode0 and Mode1. This mode will advertise 100Base-TX Half Duplex to the link partner, but will also Auto Negotiate with the link partner, if the link partner also supports AutoNegotiation Base-TX Full Duplex To enable this mode, add a resistor to VSS on the Mode2 pin. This will configure the PHY device into Full Duplex, 100Base-TX mode and will not Auto Negotiate. This mode is the highest communication mode capable with our PHY. With 100Mbps going out of the PHY, and 100Mbps going into our PHY, the instantaneous data rate across the MII bus is 200Mbps. SMSC AN Revision 0.3 ( )

6 This mode will automatically start transmitting MLT-3 pseudo random sequence, which can easily be used for taking eye diagrams and electricals performance measurements Base-TX Half Duplex Adding a resistor to VSS on the Mode2 and the Mode0 pins, will enable 100Base-TX Half Duplex operation and will not Auto Negotiate. This mode is the second highest communication mode capable with our PHY. With 100Mbps going out of the PHY, and 100Mbps going into our PHY, but because only transmit or receive is active at one time, the instantaneous data rate across the MII bus is only 100Mbps. This mode will also send out an MLT-3 pseudo random sequence on the TX RX pairs (AMDIX enabled) Base-T Full Duplex This mode will boot strap the device to come up and communicate in 10Base-T Full Duplex mode only. The link partner will need to also be manually configured for 10Base-T Full Duplex Base-T Half Duplex CRS Duplex This mode will boot strap the device to come up and communicate in 10Base-T Half Duplex mode only. The link partner will need to also be manually configured for 10Base-T Half Duplex. This is the slowest speed that the PHY is capable of operating in. CRS is dependent on the current Duplex Mode, except in Repeater mode. If the Auto negotiation sets the Duplex to Half mode, then the CRS will be active both during Transmit and Receive. If the Auto negotiation sets the Duplex to Full Mode, then the CRS will be active only during Receive. The duplex determines if the PHY device can receive while transmitting. In half duplex, the PHY can only receive or transmit, not both. In full duplex, the PHY can receive and transmit at the same time. 2.5 Pin 1 Modes Pin 1 is a multi-function pin and can be used as either an interrupt output from the PHY, or as a TX_ER/TXD4 from the MAC Configuration nint Use The nint, TX_ER, and TXD4 functions share a common pin. There are two functional modes for this pin, the TX_ER/TXD4 mode and nint (interrupt) mode. The RXD3/nINTSEL pin is used to select one of these two functional modes. The RXD3/nINTSEL pin is latched on the rising edge of the nrst. The system designer must float the nintsel pin to put the nint/tx_er/txd4 pin into nint mode or pull-low to VSS with an external resistor to set the device in TX_ER/TXD4 mode. The default setting is to float the pin high for nint mode. The Management interface supports an interrupt capability that is not a part of the IEEE specification. It generates an active low asynchronous interrupt signal on the nint output whenever certain events are detected as setup by the Interrupt Mask Register 30. Revision 0.3 ( ) 6 SMSC AN 16.12

7 The Interrupt system on the SMSC LAN8700/8700I has two modes, a Primary Interrupt mode and an Alternative Interrupt mode. Both systems will assert the nint pin low when the corresponding mask bit is set, the difference is how they de-assert the output interrupt signal nint. The Primary interrupt mode is the default interrupt mode after a power-up or hard reset, the Alternative interrupt mode would need to be setup again after a power-up or hard reset Primary Interrupt System The Primary Interrupt system is the default interrupt mode, (Bit 17.6 = 0 ). The Primary Interrupt System is always selected after power-up or hard reset. To set an interrupt, set the corresponding mask bit in the interrupt Mask register 30 (see Table 2.5, "Interrupt Management Table"). Then when the event to assert nint is true, the nint output will be asserted. When the corresponding Event to De-Assert nint is true, then the nint will be de-asserted. Table 2.5 Interrupt Management Table MASK INTERRUPT SOURCE FLAG INTERRUPT SOURCE EVENT TO ASSERT NINT EVENT TO DE-ASSERT NINT ENERGYON 17.1 ENERGYON Rising 17.1 Note 2.3 Falling 17.1 or Reading register Auto-Negotiation complete 1.5 Auto-Negotiate Complete Rising 1.5 Falling 1.5 or Reading register Remote Fault Detected 1.4 Remote Fault Rising 1.4 Falling 1.4, or Reading register 1 or Reading register Link Down 1.2 Link Status Falling 1.2 Reading register 1 or Reading register Auto-Negotiation LP Acknowledge 5.14 Acknowledge Rising 5.14 Falling 5.14 or Read register Parallel Detection Fault 6.4 Parallel Detection Fault Rising 6.4 Falling 6.4 or Reading register 6, or Reading register 29 or Re-AutoNegotiation or Link down Auto-Negotiation Page Received 6.1 Page Received Rising 6.1 Falling of 6.1 or Reading register 6, or Reading register 29 Re-AutoNegotiation, or Link Down. Note 2.3 If the mask bit is enabled and nint has been de-asserted while ENERGYON is still high, nint will assert for 256 ms, approximately one second after ENERGYON goes low when the Cable is unplugged. To prevent an unexpected assertion of nint, the ENERGYON interrupt mask should always be cleared as part of the ENERGYON interrupt service routine. Note: The ENERGYON bit 17.1 is defaulted to a 1 at the start of the signal acquisition process, therefore the Interrupt source flag 29.7 will also read as a 1 at power-up. If no signal is present, then both 17.1 and 29.7 will clear within a few milliseconds. SMSC AN Revision 0.3 ( )

8 Alternate Interrupt System The Alternative method is enabled by writing a 1 to 17.6 (ALTINT). To set an interrupt, set the corresponding bit in the Mask Register 30, (see Table 2.6, "Alternative Interrupt System Management Table"). To Clear an interrupt, either clear the corresponding bit in the Mask Register (30), this will de-assert the nint output, or Clear the Interrupt Source, and write a 1 to the corresponding Interrupt Source Flag. Writing a 1 to the Interrupt Source Flag will cause the state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a 1. If the Condition to De- Assert is true, then the Interrupt Source Flag is cleared, and the nint is also de-asserted. If the Condition to De-Assert is false, then the Interrupt Source Flag remains set, and the nint remains asserted. For example 30.7 is set to 1 to enable the ENERGYON interrupt. After a cable is plugged in, ENERGYON (17.1) goes active and nint will be asserted low. To de-assert the nint interrupt output, either. 1. Clear the ENERGYON bit (17.1), by removing the cable, then writing a 1 to register Or 2. Clear the Mask bit 30.1 by writing a 0 to Table 2.6 Alternative Interrupt System Management Table MASK INTERRUPT SOURCE FLAG INTERRUPT SOURCE EVENT TO ASSERT NINT CONDITION TO DE-ASSERT BIT TO CLEAR NINT ENERGYON 17.1 ENERGYON Rising low Auto-Negotiation complete 1.5 Auto-Negotiate Complete Rising low Remote Fault Detected 1.4 Remote Fault Rising low Link Down 1.2 Link Status Falling high Auto-Negotiation LP Acknowledge 5.14 Acknowledge Rising low Parallel Detection Fault 6.4 Parallel Detection Fault Rising low Auto-Negotiation Page Received 6.1 Page Received Rising low 29.1 Note: The ENERGYON bit 17.1 is defaulted to a 1 at the start of the signal acquisition process, therefore the Interrupt source flag 29.7 will also read as a 1 at power-up. If no signal is present, then both 17.1 and 29.7 will clear within a few milliseconds. 2.6 PHY Address Control and LED Polarity Control The PHY ADDRESS bits are latched on the rising edge of the internal reset (nreset). The 5-bit address word[0:4] is input on the PHYAD[0:4] pins. The default setting is all high 5'b1_1111. The address lines are strapped as defined in the diagram below. The LED outputs will automatically change polarity based on the presence of an external resistor. If the LED pin is pulled high (by an internal 33K pull-up resistor if VDDIO is +3.3V) to select a logical high PHY address, then the LED output will be active low. If the LED pin is pulled low (by an external resistor to select a logical low PHY address, the LED output will then be an active high output. Revision 0.3 ( ) 8 SMSC AN 16.12

9 To set the PHY address on the LED pins without LEDs or on the GPO1 or CRS pin, float the pin to set the address high or the pin with an external resistor (see Table 2.2, Boot Strapping Configuration Resistors, on page 3) to GND to set the address low. See Figure 2.1, "PHY Address Strapping on LEDs": Phy Address = 1 LED output = active low VDD Phy Address = 0 LED output = active high LED1-LED4 ~10K ohms ~270 ohms ~270 ohms LED1-LED4 Figure 2.1 PHY Address Strapping on LEDs 3 Clocking The PHY device can accept a clocking source from either a crystal, or from an external clock source. 3.1 Crystal Source Crystal Selection In any crystal-based oscillator circuit, the oscillator frequency is based almost entirely on the characteristics of the crystal that is used. Therefore, it is important to select a crystal that meets the design requirements. 18pF load capacitance, 100uW max drive level, 50ppm across the intended operational temperature range Crystal Circuit The recommended crystal circuit is shown below in Figure 1, "Clock Crystal Circuit". The resistor R1 is used to provide DC bias to the CMOS inverter for inversion amplifier operation. Too large an R sets the circuit unstable, while too small a resistor makes the amplifier gain small. We have chosen a 1Meg Ohm value for its optimum bias. SMSC AN Revision 0.3 ( )

10 SMSC LAN8700 PHY device CLKIN/XTAL1 XTAL2 R2 Y1 C1 R1 C2 Figure 1 Clock Crystal Circuit C1 and C2 are 33pF each, based on the load capacitance for the crystal. The load capacitance of the crystal is the crystal manufacturers required capacitance for the crystal to see in the system. The crystal chosen above requires 18pF. This is achieved using C1 and C2 in parallel along with the capacitance of the system Cs. CL = (C1*C2)/(C1+C2)+Cs. Cs includes the trace capacitance, and the input capacitance of the pins XTAL1 and XTAL2. R2 on the Crystal is used to control the crystal drive strength into the PHY clock generator. This resistance can be fine tuned to meet the requirements of each crystal manufacturer. R2 is intended to control the voltage across the input of the crystal circuitry and may not be needed. R2 should be incorporated on the output pin of the crystal circuitry. The voltage across the input pin can then be regulated by adjusting the value of the series resistor. Many factors determine the operation of this circuit. PCB trace construction & impedance, crystal device selection, capacitor values & type, all have an effect on the circuit operation. All combinations cannot possibly be analyzed, that is why it is the responsibility of each design engineer to verify the circuit with each new board layout and component change. A resistor value of 10ohm to 60 ohm is the suggested range for the series resistor. However, whatever value is selected, the value must be verified in the lab. 3.2 CLOCKIN Option The LAN8700 PHY device can also accept a clock input of either 25Mhz for MII mode operation or 50Mhz for RMII mode operation. For 25Mhz, the clock needs to be 40 to 60% duty cycle and 50ppm. For 50Mhz, the clock needs to be 45 to 55% duty cycle and 50ppm. The IEEE specification requires that the clocking signal be 100ppm, for optimum ethernet compatibility, we suggest you use a clock source with 50ppm or better across temperature. The SMSC LAN8700 uses the Reference Clock as the network clock such that no buffering is required on the transmit data path. The SMSC LAN8700 will recover the clock from the incoming data stream, the receiver will account for differences between the local REF_CLK and the recovered clock through use of sufficient elasticity buffering. The elasticity buffer does not affect the Inter-Packet Gap (IPG) for received IPGs of 36 bits or greater. To tolerate the clock variations specified here for Ethernet MTUs, the elasticity buffer shall tolerate a minimum of ±10 bits. Revision 0.3 ( ) 10 SMSC AN 16.12

11 4 Serial Management Interface (SMI) The MDIO pin is the management Data Input/Output pin, and the MDC pin is the management clock input pin. The MDIO is a bi-directional open-drain pin, and may require a pull-up resistor to VDDIO for reliable operation. If the MAC is capable of driving the signal high and low, then a pull-up resistor may not be needed. The system designer is encouraged to investigate the signal quality in the lab of their design to ensure a proper signal into the MDIO of the LAN8700 device. If the MAC has an open collector output, then the MDIO line would require a 1.5k ohm pull-up resistor to VDDIO. 5 Discrete Magnetics and Integrated Magnetics 5.1 Discrete Magnetics Discrete magnetics example is shown in Figure 5.1 on page 12. The advantage of using discrete magnetics is that it gives the designer more control over the impedance of the un-used pairs, and control of the common mode termination from the RJ45 connector. This also allows the designer to customize additional ESD protection above the protection integrated into the PHY. SMSC AN Revision 0.3 ( )

12 Figure 5.1 Discrete Magnetics Example 5.2 Integrated Magnetics Integrated Magnetics allows the customer a simpler design solution. There are fewer connection options as most of the terminations are already integrated into the magnetic/rj45 plug. An example of an integrated design is show n in Figure 5.2, "Integrated Magnetics Example". Revision 0.3 ( ) 12 SMSC AN 16.12

13 . Figure 5.2 Integrated Magnetics Example SMSC AN Revision 0.3 ( )

14 6 Frequently Asked Questions Q1> HOW DO I CONNECT THE LAN8700 MAGNETICLESSLY? To connect a PHY to another PHY on a PCB board without the need for isolation magnetics, the design is essentially the same as with the magnetics, just without the magnetics included. 3.3V 3.3V 50 Ohm 50 Ohm 50 Ohm 50 Ohm SMSC LAN8700 or LAN8187 or LAN921X X = 5, 7, or 8 TX RX RX TX SMSC LAN8700 or LAN8187 or LAN921X X = 5, 7, or 8 50 Ohm 50 Ohm 50 Ohm 50 Ohm 3.3V 3.3V Figure 6.1 LAN8700 to LAN8700 Magneticlessly For more details, please refer to the Application note Magneticless Configuration Options for SMSC LAN Devices. Q2> REGOFF CAN CAUSE YOUR PHY TO NOT WORK All of the configuration pins of the PHY are strapped during the nrst transition above Vih, except the REGOFF pin. This pin will be strapped during a combined AND logic of the VDDIO and VDDA power pins. When VDDA comes up to its specified voltage level, and VDDIO comes up to its specified voltage level, then REGOFF is sampled to determine if the internal regulator should provide the PHY with the core VDD_CORE +1.8V power. Most MAC devices will tri-state the RXCLK pin because its an input pin by default. Some ASIC and FPGA devices will MUX the pin as an output and drive it to another configuration. If the MAC device holds the REGOFF pin high during power-up of VDDIO and VDDA, then the internal regulator will not turn on and the PHY will not work without +1.8V supplied to the VDD_CORE power pin. To work around this issue, the customer can add a Pull-down strapping resistor to the REGOFF/RXCLK pin to hold this pin to VSS during power up. The value of the resistor depends on the strength of the internal MAC pull-up strength. I suggest starting with 5K ohm and going up or down in value to find an optimum amount. The customer needs to also take into consideration the RXCLK signal will need to overcome the configuration strapping resistor. An alternative solution is to delay the VDDIO power to the PHY. The internal REGOFF is strapped by the VDDA and VDDIO, since the VDDA current is used to drive the isolation transformers and is at least 110mA for 10base-T and 42mA for 100Base-T, this could get tricky to control. Revision 0.3 ( ) 14 SMSC AN 16.12

15 The VDDIO power is only 4.7mA at maximum, so a circuit to control the VDDIO and provide at least 5mA power could be used to switch on the PHY after the MAC has tri-stated all of its inputs. Q3> IS IT POSSIBLE FOR THE PHY DEVICE TO ADD THE SFD AND PREAMBLE IN THE TRANSMIT DIRECTION, AND REMOVE THE SFD AND PREAMBLE IN THE RECEIVE DIRECTION? Not at this time. These are controlled by the MAC device, in its simplest form, the PHY device is just a serializer-deserializer. The digital bits coming into the digital side of the PHY, will be the same as the digital bits coming out the PHY of the link partner, on the other side. Q4> WHEN THE RMII INTERFACE IS SHARED BETWEEN ANOTHER DEVICE, CAN I HOLD THE PHY DEVICE IN RESET TO ACCESS THE OTHER DEVICE? DOES THE PHY TRISTATE THE RMII BUS DURING RESET? The PHY will strap the configuration pins with internal resistors during reset. The value of the internal strapping resistor depends on the IO voltage and default strapping mode. For 3.3V IO, an internal Pull-down will be 77k ohms, and an internal Pull-up will be 33k ohms. For 1.8V IO, an internal Pull-down will be 77k ohms, and an internal pull-up will be 140k ohms. To determine which pin is pull-up and by default, please refer to table 7.11 of the latest SMSC LAN8700 Datasheet. Q5> THE MAC DEVICE USES THE MII BUS AS ITS CONFIGURATION STRAPPING PINS, HOW CAN I TRI- STATE THE PHY TO ENSURE THE MAC DEVICE CAN RESET INTO THE CORRECT STRAPPED CONFIGURATION? The PHY has an Isolate bit 10, in register 0. If the system sets this bit high, the MII output will be tristated and the PHY will ignore anything on the digital interface except the MDIO and MDC. The PHY data paths may be electrically isolated from the MII by setting register 0, bit 10 to a logic one. In isolation mode, the PHY does not respond to the TXD, TX_EN and TX_ER inputs. The PHY still responds to management transactions. Isolation provides a means for multiple PHYs to be connected to the same MII without contention occurring. The PHY is not isolated on power-up (bit 0:10 = 0). Q6> DO I NEED EXTERNAL ESD PROTECTION DEVICES TO ACHIEVE THE ESD LEVELS STATED IN YOUR DATASHEET? No the PHY component has active protection built in and can withstand ±8KV Human body Model discharge and as a system ±8KV Contact discharge and ±15KV Air-Gap Discharge. For more information please refer to the SMSC LAN8700 Datasheet chapter 7 DC Electrical Characteristics. Q7> CAN I USE A 50MHZ CRYSTAL IN RMII MODE? No, the 50Mhz crystal is a third harmonic of a Mhz crystal, so it requires some extra circuitry to get it to work with our crystal driver circuit. Also, the clock source into the CLKIN/XTAL1 input needs to also be sent to the MAC, and there is not enough drive strength from the crystal to support this. Q8> ARE THERE ANY POTENTIAL TEST MODES THAT THE PHY COULD GET INTO INADVERTENTLY? RX_ER and RXDV both need to be held low during nrst transition during boot-strap configuration. SMSC cannot guarantee proper operation of the PHY if either or both of these pins are held high during reset boot-strapping. SMSC AN Revision 0.3 ( )

16 80 ARKAY DRIVE, HAUPPAUGE, NY (631) , FAX (631) Copyright 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC s website at SMSC is a registered trademark of Standard Microsystems Corporation ( SMSC ). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 0.3 ( ) 16 SMSC AN 16.12