SMP/BIOS Overview. June 3, 2013

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Osborne McKinney
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1 SMP/BIOS Overview June 3, 2013

2 Topics What is SMP/BIOS? Benefits New APIs Task Scheduling Hwi/Swi Scheduling Inter-core locking Benchmarks Getting Started Benelli/Ducati specific Information Summary

3 What is SMP/BIOS? What is an SMP system? Symmetric Multiprocessing (SMP) systems are composed of two or more identical processor cores that share a common view of memory and peripherals All processors are managed by a single OS instance What is SMP/BIOS? SMP/BIOS is a multi-core variant of SYS/BIOS designed to run on SMP systems

4 SMP/BIOS Benefits A single instance of SMP/BIOS manages the concurrent execution of tasks on shared cores Simplified development of Ducati/Benelli subsystem applications Easily maximize M3/M4 core utilization Simple migration from multiple separate BIOS application instances to a single SMP/BIOS application instance Backward compatible with SYS/BIOS applications with certain caveats Possible application behavioral differences (including application failure) if the application relied on task priorities to ensure exclusive access to system objects

5 New APIs BIOS Module Bool BIOSsmpEnabled (BIOS_smpEnabled) This flag is provided to manage building applications for both SMP and non-smp versions of SYS/BIOS Task Module UInt Task_setAffinity(Task_Handle handle, UInt affinity); Used to dynamically set a task s core affinity Can be used by a running task to move itself to another core UInt Task_getAffinity(Task_Handle handle); Used to dynamically get a task s core affinity TaskdefaultAffinity module config parameter Used to globally define default Task affinity of user created tasks Defaults to Task_AFFINITY_NONE TaskPARAMSaffinity instance config parameter Used to define a task s affinity at create time Default is inherited from TaskdefaultAffinity (ie Task_AFFINITY_NONE)

6 New APIs Idle Module Existing metaonly IdleaddFunc (Function); Add idle functions only to Core 0 New metaonly IdleaddCoreFunc (Function, CoreId); Add idle functions to a specific core Power Module Power_suspend() now sets up WUGEN masks and SLEEPDEEP Returns after readying tasks on each core that do the suspend work Core Module (new) tisysbioshalcore module UInt Core_getCoreId(); returns the current core id const UInt Core_numCores (CorenumCores) number of smp cores Core is a proxy for target/device specific delegate module Currently bound to tisysbiosfamilyarmducatismpcore

7 3*N-1 2*N+3 2*N+2 2*N+1 2*N 2*N-1 N+3 N+2 N+1 N N Don t Care Ready Queues Core 1 Ready Queues Core 0 Ready Queues Task Scheduling Core Affinity Support Each task has a core affinity (Hard CPU Affinity) 0, 1, or Task_AFFINITY_NONE Default is Task_AFFINITY_NONE Task Scheduler Ready Queues 3 ready queue sets in total, 1 per core affinity Each ready queue set contains N queues, N being the number of supported task priorities (16 by default) Each ready queue maintains a list of ready tasks that share the same priority and affinity For coding efficiency, the three sets of ready queues are placed contiguously in memory A ready task is removed from its ready queue when it is made to run

8 Task Scheduling Algorithm Core X* Task Scheduler called Pick highest priority ready task from between Current Core s ready Set and Don t Care ready Set SMP Scheduling Rule: At any given time, the two highest priority tasks that are ready to run, ARE in running state Scheduling Algorithm: The Task scheduler on a particular core is called whenever a Task on that core becomes ready to run due to a Semaphore_post(), Event_post(), Task_sleep() timeout, etc Core 0 task scheduler always picks the highest priority ready task from between the core 0 ready set and the don t care ready set Core 1 task scheduler always picks the highest priority ready task from between the core 1 ready set and the don t care ready set Pre-empted tasks are placed at the beginning of their respective ready queue while Blocked tasks that become ready are placed at the end Return from Scheduler Interrupt other core to make its scheduler run Yes Selected ready task s priority > Running task s priority? No Yes Put currently running task on its ready queue & remove the selected highest priority ready task from its ready queue and make it run No scheduling required on current core Other Core s scheduler needs to perform a scheduling operation? * X is current Core Id on which task scheduler is running No

9 Hwi and Swi Scheduling For design simplification, Hwis and Swis are forced to run on Core 0 Swis can be posted from either core but will only be run on Core 0 By default, user Hwis are routed to core 0 Hwi routing can be configured by the user NOTE: Unlike Non-SMP BIOS, Hwis and/or Swis can be running on Core 0 while a Task is running on Core 1

Inter-core Locking An Inter-core Lock guarantees exclusive access to Hwi/Swi/Task critical section code/data Accessed through these Core module

specific Current Design The Inter-core lock is acquired whenever any of the three schedulers (Task, Swi or Hwi) are disabled by Task_disable(),

10 Inter-core Locking An Inter-core Lock guarantees exclusive access to Hwi/Swi/Task critical section code/data Accessed through these Core module APIs: Core_lock() Core_unlock() These APIs are spec d in ICore but must only to be used internally by BIOS Their implementations are hardware specific Current Design The Inter-core lock is acquired whenever any of the three schedulers (Task, Swi or Hwi) are disabled by Task_disable(), Swi_disable(), or Hwi_disable(), and released only when all 3 schedulers are enabled A Task or Swi disable on one core effectively disables Hwi s on the other core

only use the ducati subsystem s CTM timers It previously mapped Timer 0 to the M3 s local SysTick timer and Timer 1 to one of the two

11 Benelli/Ducati specific Information Hwi interrupt management Certain Hwi APIs invoked from Core 1 write to a virtual NVIC, then force these NVIC changes to occur on Core 0 using the Inter-core interrupt Timer management The tisysbiosfamilyarmducatitimer module was modified to only use the ducati subsystem s CTM timers It previously mapped Timer 0 to the M3 s local SysTick timer and Timer 1 to one of the two global CTM timers Ducati Hardware Breakpoints A cortex M3 constraint requires code to be bound to addresses 0-0x1FFFFFFF for HW breakpoints to work

12 Summary With SMP/BIOS, the TWO highest priorities tasks that are ready to run will be RUNNING SIMULTANEOUSLY at all times You can not depend on Task priorities to guarantee critical section protection Currently, there is no attempt to balance Tasks between the 2 cores (No explicit Load Balancing) All Hwi s are routed to core 0 by default Interrupt routing can be overridden by the user All Swi s are run on core 0 Internally guaranteed May be posted on either core Hwi s and Swi s running on core 0 while tasks are running on core 1 may violate thread execution assumptions You can not depend on Swi/Task priorities to guarantee critical section protection SMP aware SysMin, SysStd, LoggerBuf modules (in tisysbiossmp package) are provided in place of corresponding xdcruntime equivalents tisysbiosload module has been enhanced to support SMP/BIOS

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