Multi-CPLD SUPPORTS ALTERA MAX7000S AND MAX3000A PLD DEVICES. Logic Design Environment. Maximum Digital Designs, LLC Presents:

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1 Maximum Digital Designs, LLC Presents: Multi-CPLD Logic Design Environment SUPPORTS ALTERA MAX7000S AND MAX3000A PLD DEVICES (+ other pin compatible industry standard CPLDs/SPLDs)

2 Table of Figures Figure 1 - Clock Sockets...6 Figure 2 - Typical Clock Pinout...7 Figure 3 - Ground Features...8 Figure 4 - Power Features...10 Figure 5 - Programming Header...12 Figure 6 - Max7000S 44 Pin Device Programming...13 Page 2 of 24

3 1 STANDARD PACKAGE CONTENTS: DISCLAIMER: INTENDED USE: CLOCKS ½ SIZE SOCKET INCLUDED CLOCKS GROUNDS GROUND PLANES AVAILABLE GROUNDS Markings POWER BOARD REQUIREMENTS RECTIFICATION TAKE OFF POWER Limits MULTIVOLT SELECTION AVAILABLE CURRENT PER SOCKET POWER LED PROGRAMMING BYTEBLASTERMV BYTEBLASTERMV DRIVER INSTALLATION Driver Installation Sequence SETTING UP PROGRAMMING HARDWARE IN QUARTUS II SOFTWARE DISCRETE DEVICE PROGRAMMING Programming the Max7000S 44 Pin Device Programming the Max3000A 44 Pin Device Programming the Max7000S 84 Pin Device I/O PIN LOCATIONS MAX7000S 44S 44 PIN DEVICE PIN MAP MAX3000A 44A 44 PIN DEVICE PIN MAP MAX7000S 84S 84 PIN DEVICE PIN MAP EXAMPLE CODE FOUR-BIT COUNTER EIGHT-BIT REGISTER MUX BIT ALU SUPPORT INFORMATION WARRANTY THIRTY (90) DAY SATISFACTION GUARANTEE NINETY (90) DAY GUARANTEE SYSTEM REQUIREMENTS SUPPORTED DEVICES TRADEMARK INFORMATION Page 3 of 24

4 1 Standard Package Contents: 1. (1) Multi-CPLD Design Board 2. (3) MHz Clocks (Installed) 3. (1) EPM3032ALC44-10 (Installed) Page 4 of 24

5 2 Disclaimer: Maximum Digital Designs, LLC reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. Maximum Digital Designs, LLC provides the information and data included in this document for your benefit. However, it is not possible to entirely verify and test all the information, in all circumstances, particularly information relating to products manufactured by those other than Maximum Digital Designs, LLC. Maximum Digital Designs, LLC makes neither warranty nor representation relating to the quality, content, or adequacy of this information. Although every effort has been made to ensure the accuracy of this manual, Maximum Digital Designs, LLC shall not be liable for any errors, incidental or consequential damages in connection with the furnishing, performance, or use of Maximum Digital Designs, LLC products. Maximum Digital Designs, LLC assumes no responsibility for damage or loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the Multi-CPLD, or for any damage or loss caused by malfunction. Customers assume all responsibility in using the Multi-CPLD. Maximum Digital Designs, LLC provides a thirty (30) day money back satisfaction guarantee less shipping if product is in resellable condition (to be determined by Maximum Digital Designs, LLC). All Maximum Digital Designs, LLC products carry a ninety day (90) parts and labor warranty on defective parts and assembly (excluding logic devices). Maximum Digital Designs, LLC is not responsible for damaged products that are the result of improper handling, installation, or operation. The customer must handle, install, and operate the device within the guidelines outlined within the operating manual. 3 Intended Use: This product is intended for non-commercial applications and is not INTENDED FOR COMMERCIAL APPLICATIONS. ALL PARTIES USING THIS PRODUCT FOR NON-EDUCATIONAL APPLICATIONS ASSUME ALL RESPONSIBILITES. THIS PRODUCT IS INTENTED FOR EDUCATIONAL USE ONLY WITH NO VIABLE COMMERCIAL USE. Page 5 of 24

6 4 Clocks 4.1 ½ Size Socket There are three (3) half socket clocks on the board. Each CPLD socket has its own dedicated clock as shown below: 44A Device CLK 44S Device CLK 84S Device CLK a. Figure 1 - Clock Sockets Page 6 of 24

7 Typical Clock Pinout: 1. No Connect (NC) 2. NC 3. NC 4. GND 5. Clock 6. NC 7. NC 8. VCC b. Figure 2 - Typical Clock Pinout 4.2 Included Clocks The Multi-CPLD includes (3) ½ size clocks at MHz. These clocks are ideal for generating all types of combinatorial logic, especially video signals. Page 7 of 24

8 5 Grounds 5.1 Ground Planes The Multi-CPLD features full ground plane copper floods on both side of the two layer PCB. The copper floods provide close reference planes for adjacent signals. Further, as the signals are closely coupled to a reference plane, they provide jitter free timing edges. 5.2 Available Grounds All signal pins have adjacent rows of ground pins. These are provided for probe hook-up for various signal devices including oscilloscopes and logic state analyzers Markings Ground signal columns are marked with a G header (circled, red dashes; see figure below). In addition, the four stand-offs and the DB-25 mounting holes are also all tied to the ground plane. Figure 3 - Ground Features Page 8 of 24

9 6 Power 6.1 Board requirements The Multi-CPLD can accept any standard DC wall transformer that supplies at least 500mA per socket that is used. Further, 1500mA is strongly recommended to power all three sockets simultaneously. Recommended input voltage should be between 7V and 15V (20V absolute maximum). Power should be supplied through the blue terminal block marked Power Input ( A in the Figure 4 below). 6.2 Rectification The Multi-CPLD power input is fully rectified for convenience. Therefore, polarity need not be observed ( B in the Figure 4 below). 6.3 Take Off Power Headers supply power taken from the three voltage regulators. The headers are labeled VCC44 (supplying 5V taken from the 44S device voltage regulator), 3v3 (supplying 3.3V from the 44A device voltage regulator) and VCC84 (supplying 5V taken from the 84S device voltage regulator). The headers are labeled C, D and E, respectively, in the Figure 4 below Limits Each of the three voltage regulators is capable of supplying a maximum of 500mA TOTAL. Therefore, careful considerations should be made before using the Multi-CPLD as an external power source (i.e. powering a bread board). The user must calculate the current required by the devices in use plus the external need. This calculation cannot exceed 500mA per device. For more information on calculating CPLD current consumption, see the appropriate data sheet for the device used (for Altera devices, MultiVolt Selection The 84S device supports MultiVolt operation. Briefly, MultiVolt allows I/O pins to be driven at a different voltage level that the core voltage. For complete information on the MultiVolt feature, please refer to the Max7000S data sheet located at MultiVolt I/O pin voltage selection is accomplished through the MultiVolt header ( F in the Figure 4 below). Move the supplied jumper to either 5v or 3v3 to select 5V or 3.3V I/O output voltage. External voltage can be applied directly to the middle pin, which is routed to VCCIO on the 84S device. Page 9 of 24

10 6.5 Available Current per Socket Each socket (and thus voltage regulator) is capable of supplying 500mA per device. This absolute current rating must include device draw AND take off needs. For more information on calculating CPLD current consumption, see the appropriate data sheet for the device used (for Altera devices, Power LED A power LED is provided to indicate that a valid power source is connected ( G in the Figure 4 below). C D G E F B A Figure 4 - Power Features Page 10 of 24

11 7 Programming 7.1 ByteBlasterMV The Multi-CPLD has a native ByteBlasterMV on board and ready to use. A standard DB-25 (male/female) parallel cable (straight thru) is needed to interface with most computers. As noted in System Requirements, the Multi-CPLD requires a computer with an available parallel port. The Multi-CPLD is incompatible with most parallel to USB converters. 7.2 ByteBlasterMV Driver Installation You must install the ByteBlasterMV download cable driver before you can use it to program devices with the Quartus II software. You must have Administrator privileges to install the ByteBlasterMV download cable drivers Driver Installation Sequence Click on the Start menu, and click on Control Panel. Click the Switch to Classic View link if necessary. Double-click the Add Hardware icon to start the Add Hardware Wizard and click Next to continue. Select Yes, I have already connected the hardware and click Next. Select Add a new hardware device in the Installed hardware list, and click Next to continue. Select Install the hardware that I manually select from a list (Advanced) and click Next to continue. Select Sound, video and game controllers, and click Next to continue. Select Have Disk... Browse to the win2000.inf file in the \drivers\win2000 directory of your Quartus II software or MAX+PLUS II software installation and click OK. Click Continue Anyway when the Software Installation warning appears. Select Altera ByteBlaster and click Next to continue. Click Next to install the driver. Click Continue Anyway when the Hardware Installation warning appears. Click Finish in the Completing the Add/Remove Hardware Wizard window. Reboot the computer. Complete your installation by setting up programming hardware Page 11 of 24

12 7.3 Setting Up Programming Hardware in Quartus II Software For earlier versions of either Quartus or Max Plus II, see: Start the Quartus II software. Choose Programmer from the Tools menu. The Programmer window will open. Click the Hardware Setup... button to open the Hardware Setup window. The selected programming hardware is identified as Currently Selected Hardware. Programming hardware that is already set up appears in the Available hardware items window. Click the Add Hardware button to open the Add Hardware window if the programming hardware you would like to use is not listed in the Available hardware items window. Select the appropriate programming cable or programming hardware from the Hardware Type list. Select the appropriate port and baud rate if necessary. Click OK. Select the programming hardware you would like to use by choosing it in the Available hardware items list. Click Close. Your programming hardware has been set up. 7.4 Discrete Device Programming To program the Multi-CPLD, the appropriate jumpers must be moved on the Programming header (circled in Figure 5 below). Figure 5 - Programming Header Page 12 of 24

13 7.4.1 Programming the Max7000S 44 Pin Device To program the Max7000S 44 pin socket, move the two supplied programming jumpers to the positions as shown below: Figure 6 - Max7000S 44 Pin Device Programming Programming the Max3000A 44 Pin Device To program the Max3000A 44 pin socket, move the two supplied programming jumpers to the positions as shown below: Figure 5 - Max3000A 44 Pin Device Programming Programming the Max7000S 84 Pin Device To program the Max7000S 84 pin socket, move the two supplied programming jumpers to the positions as shown below: Figure 6 - Max7000S 84S Pin Device Programming Page 13 of 24

14 8 I/O Pin Locations 8.1 Max7000S 44S 44 Pin Device Pin Map JP7: Outside Inside JP6: Inside Outside GND GND 8.2 VCC44 (5V) Page 14 of 24

MAX3000A 44A 44 PIN DEVICE Pin Map JP5: Outside Inside 6 40 8 41 9 43 11 44 12 1 14 2 16 4 GND 5

15 MAX3000A 44A 44 PIN DEVICE Pin Map JP5: Outside Inside GND 5 JP4: Inside Outside GND GND GND VCC3v3 (3.3V) Page 15 of 24

8.3 Max7000S 84S 84 Pin Device Pin Map JP3: Outside Inside 1 2 4 5 6 8 9 10 11 12 15 16 17 18 20 21 22 24 25 27 28 29 30 31 33 34 35 36 37 39 40 41

16 8.3 Max7000S 84S 84 Pin Device Pin Map JP3: Outside Inside GND JP2: Inside Outside GND VCC84 (5V) Page 16 of 24

17 9 Example Code 9.1 Four-Bit Counter -- MaximumDigitalDesigns, LLC -- 4 bit Counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; Entity counter is port ( clk : in std_logic; reset : in std_logic; r : out std_logic_vector (3 downto 0) end counter; Architecture sequence of counter is signal count: std_logic_vector(3 downto 0 Begin Process(clk, reset) Begin if reset = '0' Then count <= "0000" ; Elsif(clk'event and clk = '1') Then count <= count + '1'; Else count <= count; End If; End Process; r <= count; End sequence; Page 17 of 24

18 9.2 Eight-Bit Register -- MaximumDigitalDesigns, LLC -- 8 Bit Register Array library ieee; use ieee.std_logic_1164.all; entity reg8 is port ( R: in std_logic_vector (7 downto 0 enable, clock: in std_logic; Q: out std_logic_vector (7 downto 0) end reg8; architecture behav of reg8 is begin load: process (clock, enable) begin if (clock'event and clock = '1') then if (enable = '1') then Q <= R; --else Q <= Q; end if; end if; end process load; end behav; Page 18 of 24

19 MuX -- MaximumDigitalDesigns, LLC -- Mux 2 to 1 library ieee; USE ieee.std_logic_1164.all; ENTITY mux2_1 is PORT ( sel : IN STD_LOGIC; i0 : IN STD_LOGIC_VECTOR(7 DOWNTO 0 i1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0 F : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) END mux2_1; ARCHITECTURE case_sel OF mux2_1 IS BEGIN PROCESS (sel) BEGIN CASE sel IS WHEN '0' => f <= i0; WHEN '1' => F <= i1; WHEN OTHERS => f <= " "; END CASE; END PROCESS; END case_sel; Page 19 of 24

20 9.4 8-bit ALU -- MaximumDigitalDesigns, LLC -- ALU8 -- fsel - function f = a + b + ci f = /a + b + ci f = a and b f = a or b f = a xor b f = b << f = b >> f = 0 library ieee; use ieee.std_logic_1164.all; entity ALU_8 is port( a : in std_logic_vector(7 downto 0 b : in std_logic_vector(7 downto 0 fsel : in std_logic_vector(2 downto 0 cin : in std_logic; sli : in std_logic; sri : in std_logic; f : out std_logic_vector(7 downto 0 slo : out std_logic; sro : out std_logic; C : out std_logic; V : out std_logic; S : out std_logic; Z : out std_logic END ALU_8; architecture behavior of ALU_8 is COMPONENT fa_8 port( cin : in std_logic; a : in std_logic_vector(7 downto 0 b : in std_logic_vector(7 downto 0 g : out std_logic_vector(7 downto 0 p : out std_logic_vector(7 downto 0 ci_msb: out std_logic; co_msb: out std_logic; hs : out std_logic_vector(7 downto 0 end COMPONENT; s : out std_logic_vector(7 downto 0 co : out std_logic COMPONENT flags port( f : in std_logic_vector(7 downto 0 Page 20 of 24

21 cout_msb: in std_logic; cin_msb : in std_logic; C : out std_logic; V : out std_logic; S : out std_logic; Z : out std_logic end COMPONENT; COMPONENT not_gate port( a: in std_logic_vector(7 downto 0 b: out std_logic_vector(7 downto 0) END COMPONENT; COMPONENT MUX8_8 is port( i0 : in std_logic_vector(7 downto 0 i1 : in std_logic_vector(7 downto 0 i2 : in std_logic_vector(7 downto 0 i3 : in std_logic_vector(7 downto 0 i4 : in std_logic_vector(7 downto 0 i5 : in std_logic_vector(7 downto 0 i6 : in std_logic_vector(7 downto 0 sel : in std_logic_vector(2 downto 0 z : out std_logic_vector(7 downto 0) end COMPONENT; COMPONENT MUX8_1 is port( i0 : in std_logic; i1 : in std_logic; i2 : in std_logic; i3 : in std_logic; i4 : in std_logic; i5 : in std_logic; i6 : in std_logic; sel : in std_logic_vector(2 downto 0 z : out std_logic end COMPONENT; COMPONENT mux_slo PORT ( END COMPONENT; COMPONENT mux_sro PORT i : IN STD_LOGIC; sel : IN STD_LOGIC_VECTOR(2 downto 0 z : OUT STD_LOGIC Page 21 of 24

22 ( i : IN STD_LOGIC; sel : IN STD_LOGIC_VECTOR(2 downto 0 z : OUT STD_LOGIC END COMPONENT; signal into_01: std_logic_vector(7 downto 0 signal into_2 : std_logic_vector(7 downto 0 signal into_3 : std_logic_vector(7 downto 0 signal into_4 : std_logic_vector(7 downto 0 signal into_a : std_logic_vector(7 downto 0 signal Nout : std_logic_vector(7 downto 0 signal cout, coutmsb, cinmsb: std_logic; signal tmpf : std_logic_vector(7 downto 0 begin f <= tmpf; U0: fa_8 port map( U1: MUX8_8 port map( cin => cin, co => cout, co_msb => coutmsb, ci_msb => cinmsb, a => into_a(7 downto 0), b => b(7 downto 0), s => into_01(7 downto 0), g => into_2(7 downto 0), p => into_3(7 downto 0), hs => into_4(7 downto 0) i0 => into_01(7 downto 0), i1 => into_01(7 downto 0), i2 => into_2(7 downto 0), i3 => into_3(7 downto 0), i4 => into_4(7 downto 0), i5(0) => sli, i5(1) => b(0), i5(2) => b(1), i5(3) => b(2), i5(4) => b(3), i5(5) => b(4), i5(6) => b(5), i5(7) => b(6), i6(7) => sri, i6(6) => b(7), i6(5) => b(6), i6(4) => b(5), i6(3) => b(4), i6(2) => b(3), i6(1) => b(2), i6(0) => b(1), sel => fsel(2 downto 0), z => tmpf(7 downto 0) Page 22 of 24

23 U2: not_gate port map( a => a(7 downto 0), b => Nout(7 downto 0) U3: MUX8_8 port map( U4: mux_sro port map( U5: mux_slo port map( U6: flags port map( i0 => a(7 downto 0), i1 => Nout(7 downto 0), i2 => a(7 downto 0), i3 => a(7 downto 0), i4 => a(7 downto 0), i5 => a(7 downto 0), i6 => a(7 downto 0), sel => fsel(2 downto 0), z => into_a(7 downto 0) i => b(0), sel => fsel, z => sro i => b(7), sel => fsel, z =>slo f => tmpf, cout_msb => coutmsb, cin_msb => cinmsb, C => C, V => V, S => S, Z => Z end behavior; Page 23 of 24

24 10 Support Information Support is available by only. For all support issues, please contact All support questions will be answered in 24 hours. 11 Warranty 11.1 Thirty (90) Day Satisfaction Guarantee To ensure your complete satisfaction, Maximum Digital Designs, LLC will refund your fill purchase price (less any shipping costs, original or return) for any reason thirty (30) days from the date of the initial sale. The product must be returned in a complete and resellable condition. Any defect to the returned product voids this warranty. This warranty does not cover logic devices Ninety (90) Day Guarantee All Maximum Digital Designs, LLC products carry a ninety day (90) parts and labor warranty on defective parts and assembly (excluding logic devices). Maximum Digital Designs, LLC will, at its discretion, repair or replace the defective device. Maximum Digital Designs, LLC is not responsible for damaged products that are the result of improper handling, installation, or operation. The customer must handle, install, and operate the device within the guidelines outlined within the operating manual. 12 System Requirements Quartus II Web Edition Pentium II PC running at 400 MHz or faster Microsoft Windows XP or Windows 2000 Parallel port for use with the native ByteBlasterMV DB-25 (Male/Female) parallel cable DC-DC wall transformer 7-15V (20V Max) capable of supplying at least 1000mA (1500mA recommended) 13 Supported Devices All Max3000A devices in the 44 pin PLCC package All Max7000S devices in the 44 and 84 pin PLCC Package 14 Trademark Information All registered trademark information used in this manual are the property of the owners and used for informational purposes only. Altera, Quartus II, Max3000A, Max7000S, MultiVolt and ByteBlasterMV are the registered trademarks of Altera Corporation. Pentium I I is the registered trademark of Intel Corporation. Microsoft, Windows XP and Windows 2000 are the registered trademarks of Microsoft. Page 24 of 24

ByteBlaster II Download Cable User Guide

ByteBlaster II Download Cable User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com UG-BBII81204-1.1 P25-10324-00 Document Version: 1.1 Document Date: December 2004 Copyright