ICE Emulator for Motorola 68360/349

Transcription

1 ICE Emulator for Motorola 68360/349 TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... ICE In-Circuit Emulator... ICE Target Guides... ICE Emulator for Motorola 68360/ WARNING... 4 Quick Start... 5 Troubleshooting... 6 Hang-Up 6 Dualport Errors 7 FAQ... 8 Configuration Basics Emulation Modes 13 SYStem.Mode Emulation modes 14 SYStem.Access Dualport modes 15 General SYStem Settings and Restrictions General Restrictions 16 SYStem.Option DSACK DTACK mode 17 SYStem.Option Show cycles 17 SYStem.Option Show buserror cycles 17 SYStem.Option DMA modes 18 SYStem.Option Reset configuration 18 SYStem.Option MODCKx PLL mode 19 SYStem.Option Memory access timing 19 SYStem.Option ONCE On-circuit emulation 21 SYStem.Option STBY Standby voltage 22 SYStem.Option TestClock Clock error check 22 SYStem.Line BKPT External BKPT input 22 SYStem.Line ADDR Address mask 22 SYStem.RESetOut Peripheral reset 23 SYStem.TimeDebug Timeout for debug interface 23 SYStem.BdmClock BDM clock speed 23 ICE Emulator for Motorola 68360/349 1

2 SYStem.Option Address lines 24 SYStem.Clock Clock generation 24 Exception Control exception.enable Exception control 25 RESET 26 RESETS 27 HALT Line 28 BERR Line 29 BR Line 29 Mapping MAP.BUS Bus width mapping 30 Memory Classes State Analyzer Keywords for the Trigger Unit 32 Keywords for the Display 33 Dynamic Data Selector 34 Dequeueing 35 Port Analyzer Keywords for the Port Analyzer Compilers rd Party Tool Integrations Realtime Operation Systems Emulation Frequency Emulation Modules Module Overview 43 Order Information 44 Physical Dimensions Adapter ICE Emulator for Motorola 68360/349 2

3 ICE Emulator for Motorola 68360/349 Version 14-Nov-2018 SP:000045EE \\MCC\mcc\.sieb MIX AI E::w.d.l addr/line label mnemonic comment SP:000045E8 addq.l #3,d3 ; #3,.primz 443 primz = i + i + 3; SP:000045EA move.l d3,d1 ;.primz,.k SP:000045EC add.l d2,d1 ;.i,.k SP:000045EE bra $45F6 k = i + primz; 446 E::w.per SP:000045F0 447 SIM Configuration and Protection MCRH 0000 BR040ID 0 E::w.v.tab flags i (0) 1, MCRL 7CFF ASTM AsynFRZ1 Frz FRZ0 Frz BCROID 7 (1) 1, SUPV yes BCLRISM 7 IARB (2) 1, AVR 00 (3) 0, RSR C0 EXT yes POW yes SW no DBF no (4) 1, CLKOCR0C CLKWP np RSTEN no COM2 (5) 1, PLLCR 0000 PLLEN displlwp no PREEN 1 STSIM EXT (6) 0, CDVCR 0000 CDVWP no DEsY 1 DFTM 1 For general informations about the In-Circuit Debugger refer to the ICE User s Guide (ice_user.pdf). All general commands are described in PowerView Command Reference (ide_ref.pdf) and General Commands and Functions. ICE Emulator for Motorola 68360/349 3

4 WARNING NOTE: Do not connect or remove probe from target while target power is ON. Power up: Switch on emulator first, then target Power down: Switch off target first, then emulator ICE Emulator for Motorola 68360/349 4

5 Quick Start tbd. ICE Emulator for Motorola 68360/349 5

6 Troubleshooting Hang-Up If you are not able to stop the emulation, there may be some typically reasons: Double Address Error No DSACK Signal WATCHDOG Clock Error Changing the VCO Low Speed After a double address error the CPU state changes to HALT. Use the SYStem.Up command to start again. Double address errors normally occur when the stack pointer is out of memory. This condition occurs, if no DSACK signal is generated and the bus monitor is not activated. External accesses may be limited by SYStem.TIMEOUT. Internal accesses should be limited by the bus monitor. However some bytes between the peripherals are not monitored and force a hang-up of the emulation system.the CPU internal bus monitor is enabled by clearing bit FRZ0 (Freeze Bus Monitor enable) of register MCR (Module Configuration Register) and setting bit BME (Bus Monitor External enable) of register SYPCR (System Protection Register). In type CPU's the watchdog is enabled on RESET. Don't forget to disable the Software Watchdog (SWE) before starting the emulation. on sysup gosub ( d.s cpu:03ff00 %l d.s sd: %b 40 return )... stop The clock lines between the target and the oscillator replacement are kept as short as possible. But the 32 khz oscillator circuit has a very high impedance and correct operation with a crystal in the target cannot be guaranteed. Using the internal 32 khz clock is recommended in this case. When the VCO of the is reprogrammed, the System.Option TestClock must be turned off to avoid a clock fail error during VCO reloc. If the register is changed manually by the debugger, System.BdmClock must use a fixed frequency and the TimeDebug value must should set at least to 100 ms to prevent debug port access time-outs. When changed by the target program, the access Timeout (Trigger.Set TimeOut) of the emulator will trigger. Low clock frequencies may slow down the speed of the serial debugging interface. If debug errors occur, increase the value TimeDebug to 10 ms. ICE Emulator for Motorola 68360/349 6

7 Dualport Errors To implement the dualport access (emulation memory), the BR-line of the CPU is used. Dualport accesses are only allowed, while no external request to the bus occurs and the CPU cycle is completed. If the emulation CPU is in RESET state, the system controller may always access the emulation memory. Dualport errors may occur in the following conditions: 1. The length of the CPU cycle is extended by wait cycles, so that the request timeout signal is generated. 2. External DMA requests (single cycles) are too long. To solve problems with dualport error first increase the SYStem.TimeReq value. Be sure that the SYStem.TimeOut value is bigger than the access time limit. If it is not possible to solve the problem by changing these values, you must switch to DENIED mode. In this mode no access to memory is possible while running realtime emulation. The internal dualport access can increase the reaction time for external DMA requests. The performance reduction by the dualport access is typically 1% with some data windows (dualported) on the screen and may be at max. 5% when using dynamic emulation memory. ICE Emulator for Motorola 68360/349 7

8 FAQ Debugging via VPN Ref: 0307 The debugger is accessed via Internet/VPN and the performance is very slow. What can be done to improve debug performance? The main cause for bad debug performance via Internet or VPN are low data throughput and high latency. The ways to improve performance by the debugger are limited: In PRACTICE scripts, use "SCREEN.OFF" at the beginning of the script and "SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates. Please note that if your program stops (e.g. on error) without executing "SCREEN.OFF", some windows will not be updated. "SYStem.POLLING SLOW" will set a lower frequency for target state checks (e.g. power, reset, jtag state). It will take longer for the debugger to recognize that the core stopped on a breakpoint. "SETUP.URATE 1.s" will set the default update frequency of Data.List/Data.dump/Variable windows to 1 second (the slowest possible setting). prevent unneeded memory accesses using "MAP.UPDATEONCE [address-range]" for RAM and "MAP.CONST [address--range]" for ROM/FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified address range only once after the core stopped at a breakpoint or manual break. "MAP.CONST" will read the specified address range only once per SYStem.Mode command (e.g. SYStem.Up). ICE Emulator for Motorola 68360/349 8

9 Target Power Supply Switch Ref: 0103 Is there a simple way to control target power supply via the ICE to prevent problems after the ICE has been powered off? Follow the sequence below. If you own an output probe COUT8, connect it to the STROBE output connector. Type PULSE2. and press F1. You will get the pin out of the output probe COUT8. Pin 13 (OUT6) delivers +5 V after the emulator has finished its initialization and 0 V if the emulator is powered off. This can be used to drive a relay via a transistor to switch the target power on and off automatically if the Pulse Generator is not used for other purposes. The schematic of the switching unit can be found in the file TARGETC.CMM. Additionally Pin 13 (OUT6) can be controlled by ICE commands. Target power supply off. "PULSE2.P +" Target power supply on. "PULSE2.P -" The following PRACTICE command file creates 3 buttons in the Toolbox for: Target power on Target power off Target power off and QUIT. Wrong Location after Break Ref: Error Message "Emulation Memory Refresh Fail" Ref: 0016 To show the buttons automatically after starting the TRACE32 software, call the script with the DO command from system-settings.cmm in your TRACE32 system directory (create system-settings.cmm if it does not exist). Why is the location after break wrong? Most emulators use some bytes of user stack for the break system. Therefore it is necessary to have valid stack, if single step or breakpoints are used. Why does the message "emulation memory refresh fail" appears during change of the PLLCR register? The ICE configured with DRAM emulation memory may show this error message at changing the PLLCR register. Workaround: SETUP.REFERR OFF SYStem.TimeReq 10.ms ICE Emulator for Motorola 68360/349 9

10 68360 Problems at PLL Register Modification Ref: 0022 Why does emulation crash when PLL registers are modified? The CPU stopps its clock for a while until the PLL is oscillating stable at the new clock frequency. For this reason the emulator will detect a "ClockFail", an "Emulation Debug Port Fail" or "Dual Port Fail". Workaround: Disable ClockFail detection Increase TimeRequest value Increase TimeDebug value SYStem.Option TestClock OFF SYStem.TimeReq 10.ms SYStem.TimeDebug 10.ms Start-up Ref: 0012 The command "SYS.Up" does not work! The CPU disables the CLKO1 signal on MODCK0 = 1.and. MODCK1 = 0. Therefore the BDM clock cannot be generated by this clock. The TESTCLOCK option must be switched off. Start-up sequence: SYS.RES SYS.O DC SYS.O TESTCLOCK OFF SYS.O MODCK0 1 SYS.O MODCK1 0 SYS.UP For correct trace the CLKO1 line should be switched to FULL Trace Listing does not work What could be the reason if the trace listing does not work? The trace does not work if the CPU's CLK01 line is disabled. Please set the "Clock Output 1 Mode" in the "CLKOCR" register to FULL. Ref: 0027 ICE Emulator for Motorola 68360/349 10

11 Configuration tbd ICE Emulator for Motorola 68360/349 11

12 Basics Frequency The emulation probe supports the MC68360 CPU up to 33 MHz internal clock frequency. Port Analyzer A slot for the port analyzer is available. The port analyzer samples 64 peripheral ports in timing and state mode. Pre-Mapper Additional Trace Channels Buffers The pre-mapper supports full 32 bit mapping in 4 different storage classes. 48 additional trace channels are supplied by the emulation probe. Address lines, strobes and FC signals are not buffered to the target. Target system hardware errors may force malfunction of the emulator, but the emulation system is always able to start up, as the debugging is made via the serial debug interface. Target Addr FC SIZ D BUF D CPU Emulator Debug Interface BDM Interface PLL On-Circuit Emulation Dynamic Data Selector The emulation system uses the integrated debug interface. The debugger interface is hardware based to enable fast download and debug control. However the memory access is much slower (Pyrex. 20 KByte/sec.) than on other emulation probes. The download speed may be increased when using dualport access. The CLKO1 signal should not be switched off. The emulator runs with internal or external clock signals. The emulator system supports a high frequency clock as well as a fixed 32 khz reference clock for the on-chip PLL system. QFP chips may be emulated on board without desoldering the chip. A special clip-over adapter connects emulator module (PGA) and target system (QFP). On prototype systems it is recommended to use either the solder-on adapter or a PGA socket. The emulation probe includes a dynamic data selector to make data triggering very simple in 32 bit systems. ICE Emulator for Motorola 68360/349 12

13 Emulation Modes E::w.sys system Mode Clock TimeReq Option Option Down RESet VCO 1.000ms CONFIG0 ShowTrace Up Analyzer Low TimeOut CONFIG1 ShowBreak Monitor Mid 5.000us CONFIG2 DMATRACE RESet ResetDown High TimeDebug MODCK0 DMATRANS ResetUp AUTO 1.000ms MODCK1 RamWait reset NoProbe VCO*2 BUS16 ResetExt RESetOut AloneInt VCO/100 Line DSACK FastTerm AloneExt 32KHZ BusReq BERR PreMap cpu-type EmulInt ClkSteal BKPT STBY TestClock M68360 EmulExt Line ADDR ONCE ShowBERR 25 MHz Access FFFFFFFF BASE WE Nodelay 00FFF000 PRTY3 ClkSteal Request Denied The emulations head can stay in 6 modes. The modes are selected by the SYStem.Up or the SYStem.Mode command. ICE Emulator for Motorola 68360/349 13

14 SYStem.Mode Emulation modes SYStem.Mode <mode> <mode>: ResetDown ResetUp AloneInt AloneExt EmulInt EmulExt Reset Down Reset Up Alone Internal Alone External Target is down, all drivers are in tristate mode. Target has power, drivers are logically in inactive state, but not tristate. Probe is running with internal clock, DTACK signals are generated by the emulator system. Probe is running with external clock, DTACK signals are generated by the emulator. Emulation Internal Emulation External Probe is running with internal clock, no DTACK signals are generated. Probe is running with external clock, no DTACK signals are generated. In active mode, the power of the target is sensed and by switching down the target the emulator changes to RESET mode. The probe is not supplied by the target. When running without target, the target voltage is simulated by an internal pull-up resistor. The command SYStem.Up in Stand-alone doesn't work correctly. Use SYStem.Mode AloneInt to select correct emulation mode. ICE Emulator for Motorola 68360/349 14

15 SYStem.Access Dualport modes SYStem.Access <option> <option>: Request Denied Request Denied This is the default method to access memory in realtime. No dualport access allowed. On realtime emulation all windows, which need dualport access, are frozen. Breakpoints should not be set while realtime emulation is working. ICE Emulator for Motorola 68360/349 15

16 General SYStem Settings and Restrictions General Restrictions There are some restrictions on the ICE 68360: CLK01 line DRAM Interface FTERM DSACK Control DMA Function Code Program Execution in Onchip RAM Onchip Program Cache (68349) External 32 khz crystals The clock line CLK01 always should be enabled. The emulator uses this signal for running the BDM interface and for AMX bit). DRAM access with multiplexed address lines need additional wait states for the emulation memory, because the full address information is send out 1 or 2 clock cycles later. This can be avoided by replacing the whole external DRAM by emulation memory and programming the CPU to generate a regular access (i.e. disable the address multiplexing by clearing the GAMX bit). FTERM cycles are very fast memory cycles, too fast for the breakpoint system. With frequencies over 10 MHz it is not possible to use FTERM bus cycles. Using software breakpoints allows up to 17 MHz with FTERM read cycles. When the memory controller of the is programmed to generate an internal DSACK, the emulator cannot add extra wait states. The commands SYStem.Option Wait or MAP.Wait cannot work in this case. If extra wait states are required, the memory controller must be reprogrammed. On DMA cycles the FC3 bit should always be set to one. Otherwise the program breakpoint system will not work correctly. Program breakpoints and single stepping doesn't work when executing code in the Standby RAM of the Execution with cache enabled (68349) is possible. When the program cache is used, the SYStem.Option CACHE must be turned on. Program trace with cache enabled is not possible. Reads from the code area must be aligned long words. Reading byte or word data from program area will not work. The cache is invalidated before the emulation is started and before a memory read is made after a memory write. Stopping the emulation is not possible when the CPU makes no external cycles, i.e. is completely running out of cache memory. Setting program breakpoints, while the emulation is running, is not recommended. The SPot system should not be used in ON mode, as this also sets breakpoints while the processor is running. Oscillator circuits with 32 khz crystals need very short lines to the CPU. The max. lin length is exceeded by the emulation probe. If the crystal is not working correctly, the internal 32 khz clock should be used. Internal clock must be used, when On-Circuit Emulation is done. ICE Emulator for Motorola 68360/349 16

17 SYStem.Option DSACK DTACK mode SYStem.Option DSACK [ON OFF] The DTACK lines may be used normally. In this mode WAIT mapping is possible. In the other way the DTACK control system is disabled. The DTACK pins are directly connected to the target system. SYStem.Option Show cycles SYStem.Option ShowBreak [ON OFF] SYStem.Option ShowTrace [ON OFF] Show cycles are CPU access cycles to internal RAM or peripheral. This accesses generate no strobe signals to the external bus, until the bits SHEN0 and SHEN1 in the MCR register are set. ShowTrace enables the analyzer and trigger features for this cycles, ShowBreak the breakpoint memory. As show cycles need only 2 clock states either the emulation memory and trace memory must be faster or the clock frequency should not exceed 12.5 MHz. Synchronous PROGRAM breakpoints will not work in internal memory, as there is no access to the CPU bus possible. NOTE: Don't use the combination 01 if in Request mode (dualport) SYStem.Option Show buserror cycles SYStem.Option ShowBERR [ON OFF] Displays bus errors received when reading memory by the BDM display. The data values will toggle between 0 and 0xff to show a bus error. The feature will work only when the bus monitor is not frozen. ICE Emulator for Motorola 68360/349 17

18 SYStem.Option DMA modes System.Line BusReq [ON OFF] System.Option DMATRACE [ON OFF] System.Option DMATRANS [ON OFF] External DMA circuits and the IDMA circuit on the target CPU work in the same way: both request the main CPU with the BR signal. In realtime emulation the emulation CPU is stopped and the DMA can get control of the bus. When emulation is stopped, no BG signal is generated and the DMA is waiting till realtime emulation is started. SYStem.Line BusReq SYStem.Option DMATRACE SYStem.Option DMATRANS This option allows DMA access without running realtime emulation. External DMA circuits are not stopped on breakpoints. DMA cycles may be traced and trigger system is also active on DMA cycles. The DMA accesses make also writes to emulation memory. On read access to internal mapped memory the data information is driven to the target system. Be sure that there is no memory to avoid bus conflicts. SYStem.Option Reset configuration SYStem.Option CONFIG0 [ON OFF] SYStem.Option CONFIG1 [ON OFF] SYStem.Option CONFIG2 [ON OFF] SYStem.Option PRTY3 [ON OFF] SYStem.Option BUS16 [ON OFF] SYStem.Option ResetExt [ON OFF] On RESET the level on some input lines define the set-up of the CPU. In stand-alone mode or if no option ResetExt is selected, the logic level on the CONFIG and MODCK pins will be supplied by the emulator. ICE Emulator for Motorola 68360/349 18

19 SYStem.Option MODCKx PLL mode SYStem.Option MODCK0 [ON OFF] SYStem.Option MODCK1 [ON OFF] The MODCK signals define the function of the oscillator circuit. MODCKx Target <> <> MODCKx CPU Tristate buffer < SYStem.Option MODCKx < RESETH & /RESetEXT SYStem.Option Memory access timing SYStem.Option RamWait [ON OFF] SYStem.Option FastTerm [ON OFF] SYStem.Option MinWait [OFF FAST ] SYStem.Option DRAM [OFF 1 2 3] RamWait FastTerm MinWait DRAM Inserts one additional wait state in all bus cycles. This option must be used when the system uses fast termination cycles. Defines the minimal number of wait states used by the target system. Must be set if internal address multiplexing is used. This option defines the time when the address multiplexing is ready so that emulation memory (also break memory!) can be accessed with a stable address. The value depends on the clock speed, the memory speed and the TRLXQ bit. Table: GAMX: Global Address Mux Enable (CPU register) RFEN: Refresh Enable (CPU register) RCYC: Refresh Cycle Length (CPU register) TRLXQ: Time Relax (CPU register) SYSTEM.OPTION DRAM x: Memory Access Time: Value for emulator system configuration the resulting emulation memory access time (clk-cycles) ICE Emulator for Motorola 68360/349 19

20 SYSTEM. DRAM Memory OPTION Access GAMX RFEN RCYC TRLXQ DRAM Time (clk-cycles) no OFF TCYC+2 yes no -- no 1..3 TCYC+2..0 yes no -- yes 2..3 TCYC+2..1 yes yes 4/3 no 2..3 TCYC+1..0 yes yes 6/5 no 3 TCYC yes yes 7/5 no 3 TCYC yes yes 8/5 no 3 TCYC yes yes 4/3 yes 3 TCYC+1 yes yes 6/5 yes not supported!!! yes yes 7/5 yes not supported!!! yes yes 8/5 yes not supported!!! The minimum emulation memory access time depends on the speed of the emulation memory in use. It might be necessary to insert wait state (increase TCYC of the DRAM chip select) to get a proper access time for. Example: - 70 ns emulation memory - CPU Clock Speed: 33 MHz --> Clock period about 33ns - Memory Access Time: TCYC+1 (Table content) - Wait states: 0 (TCYC=0) --> Memory access time: (0+1)*clockperiod --> Access time = 33 ns --> too short for 70 ns emulation memory --> insert 2 Wait states --> Memory access time: (2+1)*clockperiod --> Access time = 99 ns o.k. It also might be necessary to modify the wait state configuration for SRAM cycles as result of SYS.OPTION DRAM x. ICE Emulator for Motorola 68360/349 20

21 Table: SYSTEM. OPTION DRAM SRAM Memory Access Time (clk-cyles) OFF TCYC+2 1 TCYC+1 2 TCYC 3 TCYC-1 The additional SRAM wait states can be found as described in the example above. SYStem.Option ONCE On-circuit emulation SYStem.Option ONCE [ON OFF] Set to ON if using the Clip-Over-Adapter with QFP-Packages. The CPU chip on the target board is set to tristate by pulling down the TRIS-pin. The emulation must be set to use the internal clock (EmulInt or AloneInt). ICE Emulator for Motorola 68360/349 21

22 SYStem.Option STBY Standby voltage SYStem.Option STBY [ON OFF] ON OFF The STBY pin is always supplied even if the target power is off. Internal RAM data are lost if target power is off. SYStem.Option TestClock Clock error check SYStem.Option TestClock [ON OFF] ON OFF The clock test circuit is active. Clock fails will be detected by the emulator system. In this case the emulator changes to reset state. No clock check. The clock output may be switched off, but no trace of program and data is possible. SYStem.Line BKPT External BKPT input SYStem.Line BKPT[ON OFF] The BKPT input from the target is used to stop emulation asynchronously. SYStem.Line ADDR Address mask SYStem.Line ADDR <mask> This mask is used for internal dualport access to supply correct address mirrors. sys.line address 0x000fffffh ; address lines A0..A19 are used only ICE Emulator for Motorola 68360/349 22

23 SYStem.RESetOut Peripheral reset SYStem.RESetOut Resets the target system. The function is similar to the RESET instruction of the CPU. SYStem.TimeDebug Timeout for debug interface SYStem.TimeDebug <time> <time>: 1.260ms The serial debug interface signals Debug Error if the CPU doesn't response within this time. SYStem.BdmClock BDM clock speed SYStem.BdmClock <rate> <rate>: 4 8 <fixed> <fixed>: Either the clock frequency divided by 4 or 8 is used as the BDM clock or a fixed clock rate. The fixed clock rate must be used when the operation frequency is very slow. ICE Emulator for Motorola 68360/349 23

24 SYStem.Option Address lines SYStem.Option PreMap [ON OFF] SYStem.Option [ON OFF] The emulator can run in 24, 28 and 32 bit mode. If the upper address lines are not used by the target system, the pre-mapper should be switched off. The WE option must be used, when the upper four address bits are used as write strobes. Bus Width SYStem.Option PreMap SYStem.Option WE 24 OFF ON/OFF 28 ON ON 32 ON OFF For additional information refer to the MAP.PRE command. SYStem.Clock Clock generation SYStem.Clock <option> <option>: VCO High Mid Low Auto 32KHZ VCO/100 VCO*2 VCO Low, Mid, High Auto Variable frequency 1 35 MHz. 2.5, 5.0 or 10.0 MHz. Automatic frequency select in order to the setting on MODCLK field. If MODCLK is low, the VCO is selected (Direct Input). Otherwise the 32 khz fixed frequency signal is used to support the clock input (PLL reference clock). VCO/100 VCO frequency divided by 100. VCO*2 Doubled VCO frequency. ICE Emulator for Motorola 68360/349 24

25 Exception Control exception.enable Exception control E::w.x exception Activate Enable Trigger Puls Puls OFF OFF OFF OFF OFF Single ON CpuReset ON ON CpuReset Width RESet PerReset RESet RESet PerReset 1.000us Delay Halt Halt CpuReset Halt PERiod OFF BusReq BusReq Halt BusReq BusErr BusReq IRQ BusErr IRQ1 Puls IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ICE Emulator for Motorola 68360/349 25

26 RESET The reset line (input and output) is controlled by a bridge with analog switches and diodes. VCC 2.7k +1 Trace/Trigger VCC 2.7k RESET- S2 RESET- Target Emulation CPU S3 S1 S4 GND GND S1 Reset Target X.Activate PerReset X.Puls PerReset S2 Reset Out SYStem.RESetOut Running S3 Reset In X.Enable Reset S4 Internal Reset Emulator Control X.Activate CpuReset X.Puls CpuReset SYStem.RESetOut exception.enable Reset [ON OFF] exception.activate PerReset [ON OFF] exception.activate CpuReset [ON OFF] ICE Emulator for Motorola 68360/349 26

27 RESETS VCC 2.7k +1 Trace/Trigger VCC 2.7k RESET- S2 RESET- Target Emulation CPU S3 S4 GND S1 Reset Target X.Activate PerReset X.Puls PerReset S2 Reset Out SYStem.RESetOut Running S3 Reset In X.Enable ResetS S4 Internal Reset Emulator Control X.Activate ResetS X.Puls ResetS SYStem.RESetOut exception.enable ResetS [ON OFF] exception.activate ResetS [ON OFF] ICE Emulator for Motorola 68360/349 27

28 HALT Line VCC 2.7k +1 Trace/Trigger VCC 2.7k HALT- S5 HALT- Target Emulation CPU S6 S7 GND S5 HALT Out Running S6 HALT In X.Enable HALT S7 Internal Halt Emulator Control X.Activate HALT X.Puls HALT exception.enable Halt [ON OFF] exception.activate Halt [ON OFF] ICE Emulator for Motorola 68360/349 28

29 BERR Line VCC 100K +1 Trace/Trigger BERR- Target >=1 X.Enable X.Puls- & BERR- CPU START- SYStem.Line exception.enable BusErr [ON OFF] SYStem.Line BusERR [ON OFF] BR Line VCC 100K +1 Trace/Trigger BR- Target >=1 X.Enable X.Puls- & BR- CPU Dualport- exception.enable BusReq [ON OFF] exception.activate BusReq [ON OFF] SYStem.Line BusReq [ON OFF] ICE Emulator for Motorola 68360/349 29

30 Mapping MAP.BUS Bus width mapping MAP.BUS8 [<range>] MAP.BUS16 [<range>] MAP.BUS32 [<range>] MAP.BUSEXT [<range>] Every block in the address space of the CPU has either an 8, 16 or 32 bit bus width. The emulator breakpoint and trace system need this information in realtime in order to work correctly. The mapper must be set for all ranges, where internal bus width setting is used. map.bus8 0x0--0x0fffff map.busext ; maps first 1 MB block for 8 bit ; remaps all to external definition The MAP.RESet command sets the bus width definition to external. ICE Emulator for Motorola 68360/349 30

31 Memory Classes Memory Class Description FC0 Function-Code 0 FC1 UD FC2 UP USER-DATA USER-DATA USER-PROGRAM USER-PROGRAM FC3 Function-Code 3 FC4 Function-Code 4 FC5 SD FC6 SP SUPERVISOR-DATA SUPERVISOR-DATA SUPERVISOR-PROGRAM SUPERVISOR-PROGRAM FC7 Function-Code 7 CPU U S D P C E CPU Function-Code User Supervisor Data Program Memory access by CPU Emulation memory access ICE Emulator for Motorola 68360/349 31

32 State Analyzer Keywords for the Trigger Unit DMACycle DMA cycle TimeOut DTACK Timeout (not HA120) Read CPU read cycle Write CPU write cycle Wait0..Wait13 Wait states WaitX Wait states greater 13 WaitFast Fast cycle DMAACK DMA acknowledge RMC Read modify write cycle FC0,FC3,FC4, Function code 0, 3, 4 or FC8..FC15 UserData - FC1 User data area UserProgram - FC2 User program area SupervisorData Supervisor data area FC5 SupervisorProgram Supervisor program area FC6 CPU - FC7 Interrupt acknowledge FC8 - FC15 DMA function codes IACK Supervisor User Data Program ReadData WriteData Interrupt acknowledge Supervisor data or program access User data or program access Data access Program access Data access read Data access write BYTE WORD Byte transfer Word transfer ICE Emulator for Motorola 68360/349 32

33 TRIPLE LONG PORT 3 Byte transfer Long transfer Input line from port analyzer For not CPU-specific keywords, see non-declarable input variables in ICE/FIRE Analyzer Trigger Unit Programming Guide (analyzer_prog.pdf). Keywords for the Display WR AS FC3 DMAACK RMC SIZE SIZE.0 SIZE.1 DSACK DSACK.0 DSACK.1 BR BG BGACK BERR HALT RESETH RESETS CS0.. CS7 Wait Write line Address Strobe DMA Function Code line DMAACK line RMC line Bus transfer size SIZ0 signal SIZ1 signal Bus size DSACK0 signal DSACK1 signal Bus request Bus grant Bus grant acknowledge Bus access error Halt cycle RESETH line RESETS line Chip select lines Number of inserted wait cycles, FT means fast cycle, for more than 13 a Xw appears. ICE Emulator for Motorola 68360/349 33

34 Dynamic Data Selector To allow better triggering in systems with different bus widths, a dynamic data selector is implemented in the emulation probe. This trigger system is activated on byte, word and long data transfers independently of the bus size on the target system. The long word H written to 1001H on a word bus is transferred in 3 different cycles: Address Size D31--D24 D23--D16 D15--D08 D07--D H 4 87H 1002H 3 65H 43H 1003H 1 21H To trigger to this word with the static data selector needs 3 trigger level and a complex trigger set-up. With the dynamic data selector, the word transfer is recognized independent from the bus size and the base address. The dynamic data selector is called by the keywords DATA.Byte DATA.Word DATA.Long The analyzer programming (STU) is like this: addr ab ff ; address definition data.long testdata ; data definition break if testdata:a:ab ; operation Selective trace on byte level within a 32-bit bus is possible without knowing the base address and the data port: addr ab ff data.byte testdata 'A'--'Z' sample if testdata:a:ab The dynamic data selector can only work correctly, when the bus size can be detected. Usually the DTACK signals define the bus size. If the chip-select logic is used, internal DTACK signals will be generated. In this case, the bus size must be defined by the mapper using the commands MAB.BUS8 MAB.BUS16 MAB.BUS32 MAB.BUSEXT Define 8-bit bus Define 16-bit bus Define 32-bit bus Define bus width by DTACK lines ICE Emulator for Motorola 68360/349 34

35 The static data selectors are defined by the keywords DATA.Byte0 DATA.Byte1 DATA.Byte2 DATA.Byte3 DATA.Word0 DATA.Word1 DATA.Word2 DATA.Triple0 DATA.Triple1 DATA.Long0 Dequeueing The disassembled lines in the analyzer are displayed prior to the resulting data cycles. This dequeueing fails for commands which have not a constant number of data cycles. Problems with Prefetches: short forward conditional branches to addresses already prefetched ICE Emulator for Motorola 68360/349 35

36 Port Analyzer Keywords for the Port Analyzer A0..A15 B0..B17 C0..C11 IRQ1..IRQ7 Interrupt request lines DS AS Strobes BCLRO RESETH RESETS HALT BERR PERR BGACK BR BG Bus Clear Hardware Reset Software Reset Halt line BERR input Parity Error BusGrandAckn Busrequest BusGrand ICE Emulator for Motorola 68360/349 36

37 Compilers Language Compiler Company Option Comment ADA ALSYS-ADA IEEE limited support (IEEE) ADA TELESOFT-ADA Telesoft IEEE limited support (IEEE) ASM RTOS IEP GmbH SYM/LOC Source level debugging ASM ASM68K Mentor Graphics Corporation IEEE Source level debugging ASM VERSADOS-ASM NXP Semiconductors VERSADOS symbols only ASM OS-9-ASSEMBLER Radisys Inc. ROF Source level debugging ASM AS68 TASKING IEEE C HP C HP no type/locals info C ORGANON CAD-UL BOUND ElectronicServices GmbH C C68K Cosmic Software COSMIC C GNU-C Free Software ELF/DWARF Foundation, Inc. C GNU-C Free Software COFF Foundation, Inc. C GNU-C Free Software Foundation, Inc. ELF/DWARF C GREEN-HILLS-C Greenhills Software Inc. COFF C ICC68K Introl Corporation ICOFF C MCC Mentor Graphics IEEE Corporation C HT-68K Microchip Technology HITECH Inc. C HICROSS-68K NXP Semiconductors HICROSS C CC68K NXP Semiconductors COFF C ULTRA-C Radisys Inc. ROF OS/9 compilers C OS/9-C Radisys Inc. ROF C CROSSCODE-C SDSI SDS C SCC68K Sierra COFF C SUN3-CC Oracle Corporation DBX C ICC68K TASKING COFF C ICC68K TASKING IEEE C TT-68K TASKING IEEE C TCC68K TASKING AOUT only source and syms C TEKTRONIX-C Tektronix COMFOR ICE Emulator for Motorola 68360/349 37

38 Language Compiler Company Option Comment C D-CC Wind River Systems IEEE C D-CC Wind River Systems ELF/DWARF C++ ORGANON-C++ CAD-UL BOUND ElectronicServices GmbH C++ GNU-C++ Free Software DBX Foundation, Inc. C++ GNU-C++ Free Software ELF/DWARF Foundation, Inc. C++ CCC68K Mentor Graphics IEEE Corporation C++ HICROSS-68K NXP Semiconductors HICROSS C++ CODEWARRIOR NXP Semiconductors ELF/DWARF C++ CROSSCODE-C++ SDSI SDS C++ D-C++ Wind River Systems ELF/DWARF MODULA MOD68K Introl Corporation ICOFF MODULA MCS2 Multichannelsystems COFF GmbH MODULA MCDS NXP Semiconductors MCDS PASCAL MPC Mentor Graphics IEEE Corporation PEARL RTOS IEP GmbH SYM/LOC no type/locals info ICE Emulator for Motorola 68360/349 38

39 3rd Party Tool Integrations CPU Tool Company Host WINDOWS CE PLATF. - Windows BUILDER CODE::BLOCKS - - C++TEST - Windows ADENEO - X-TOOLS / X32 blue river software GmbH Windows CODEWRIGHT Borland Software Windows Corporation CODE CONFIDENCE Code Confidence Ltd Windows TOOLS CODE CONFIDENCE Code Confidence Ltd Linux TOOLS EASYCODE EASYCODE GmbH Windows ECLIPSE Eclipse Foundation, Inc Windows CHRONVIEW Inchron GmbH Windows LDRA TOOL SUITE LDRA Technology, Inc. Windows UML DEBUGGER LieberLieber Software Windows GmbH SIMULINK The MathWorks Inc. Windows ATTOL TOOLS MicroMax Inc. Windows VISUAL BASIC Microsoft Corporation Windows INTERFACE LABVIEW NATIONAL Windows INSTRUMENTS Corporation TPT PikeTec GmbH Windows CANTATA QA Systems Ltd Windows RAPITIME Rapita Systems Ltd. Windows RHAPSODY IN MICROC IBM Corp. Windows RHAPSODY IN C++ IBM Corp. Windows DA-C RistanCASE Windows TRACEANALYZER Symtavision GmbH Windows ECU-TEST TraceTronic GmbH Windows UNDODB Undo Software Linux TA INSPECTOR Vector Windows VECTORCAST UNIT Vector Software Windows TESTING VECTORCAST CODE Vector Software Windows COVERAGE 68K OS68 DEBUGGER Enea OSE Systems - 68K SDT CMICRO IBM Corp. Windows 68K DIAB RTA SUITE Wind River Systems Windows ICE Emulator for Motorola 68360/349 39

40 ICE Emulator for Motorola 68360/349 40

41 Realtime Operation Systems Company Product Comment Atego Ldt. AdaWorld ARTK KadakProducts Ltd. AMX Oracle Corporation ChorusOS CMX Systems Inc. CMX-RTX Synopsys, Inc MQX 2.40 and 2.50, 3.6 MTOS-UX Mentor Graphics Nucleus PLUS Corporation Radisys Inc. OS-9 Enea OSE Systems OSE Classic (OS68) Enea OSE Systems OSE Delta 4.x and 5.x RealTime Craft (XEC68k) Quadros Systems Inc. RTXC 3.2 IBM Corp. SDT-Cmicro - uclinux Kernel Version 2.4 and 2.6, 3.x Mentor Graphics VRTX32 Corporation Mentor Graphics VRTXmc Corporation Mentor Graphics VRTXsa Corporation Wind River Systems VxWorks 5.x and 6.x ICE Emulator for Motorola 68360/349 41

42 Emulation Frequency The emulation probe is designed for running with CPUs up to 33 MHz. The max. speed is limited by the memory speed and the wait states used for memory access. NOTE: When using the internal DRAM controller of the additional wait states are required, as the full address information is later available. Module CPU F-W0-15 F-W0-35 S-W0-15 S-W0-35 S-W1-15 S-W1-35 LA-7008 MC68EN LA-7009 MC68MH DRAM ICE Emulator for Motorola 68360/349 42

43 Emulation Modules Module Overview LA-7001 LA-7002 LA-7003 MC68360 MC68360 PGA LA68360 LA-7008 LA-7003 MC68EN360 MC68EN360 PGA LA68360 LA-7009 LA-7003 MC68MH360 MC68MH360 PGA LA68360 LA-7005 LA-7006 LA-7007 LA-7003 LA-7003 LA-7003 MC68360 PGA V MC68360 LA V MC68EN360 PGA V MC68EN360 LA V MC68MH360 PGA V MC68MH360 LA V LA-7004 MC68349 ET160-QF07 ICE Emulator for Motorola 68360/349 43

44 Order Information Order No. Code Text LA-7001 ICE ICE Base Module LA-7002 M-MC68360-PGA Module MC68360 PGA LA-7003 A-MC68360-P Adapter MC68360 PGA to half-size connectors LA-7008 M-MC68EN360-PGA Module MC68EN360 PGA LA-7009 M-MC68MH360-PGA Module MC68MH360 PGA LA-7005 M-MC68360-PGA-3.3V Module MC68360 PGA 3.3V LA-7006 M-MC68EN360-PGA-3.3V Module MC68EN360 PGA 3.3V LA-7007 M-MC68MH360-PGA-3.3V Module MC68MH360 PGA 3.3V LA-7004 M-MC68349 Module MC68349 ET-1020 ET C PGA to QFP Clip-Over Adapter ET-1022 ET S PGA to QFP Surface Mountable Adapter ET-1023 ET S-BGA PGA to BGA Surface Mountable Adapter Additional Options LA-7710 BDM-68K BDM Debugger for 68K (ICD) LA-7510 MON-68K ROM Monitor for 68K on ESI LA-6450 PA64 Port Analyzer LA-2812L SIMULATOR-68K-FL 1 User Float. Lic. TRACE32 68K Simulator ICE Emulator for Motorola 68360/349 44

45 Physical Dimensions Dimension LA-7002 LA-7008 LA-7009 LA-7005 LA-7006 LA-7007 M-MC68360-PGA M-MC68EN360-PGA M-MC68MH360-PGA M-MC68360-PGA-3.3V M-MC68EN360-PGA-3.3V M-MC68MH360-PGA-3.3V cable (350) 71 MC opt. ET-1020 (QFP Solder-On adapter) SIDE VIEW PGA socket A TOP VIEW (all dimensions in mm) ICE Emulator for Motorola 68360/349 45

46 Dimension LA-7003 A-MC68360-P ICE Emulator for Motorola 68360/349 46

47 Dimension LA-7004 M-MC68349 cable (400) SIDE VIEW PIN 1 Female connectors 77 7 TOP VIEW (all dimensions in mm) ET-1020 ET C ICE Emulator for Motorola 68360/349 47

48 Adapter No adapters necessary! ICE Emulator for Motorola 68360/349 48