Outline. EECS Components and Design Techniques for Digital Systems. Lec 06 Using FSMs Review: Typical Controller: state

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1 Ouline EECS 5 - Componens and Design Techniques for Digial Sysems Lec 6 Using FSMs Review FSMs Mapping o FPGAs Typical uses of FSMs Synchronous Seq. Circuis safe composiion Timing FSMs in verilog David Culler Elecrical Engineering and Compuer Sciences Universiy of California, Berkeley hp:// hp:/ins.eecs.berkeley.edu/~cs5 9/3/7 EECS5 F7 Culler Lec 6 9/3/7 EECS5 F7 Culler Lec 6 2 Review: Typical Conroller: Typical Conroller: + oupu Nex Oupu () = G( () ) Nex i2 i i o2 o o i2 i i o2 o o odd Combinaional Logic Combinaional Logic (+) = F ( () ) Example: Gray Code Sequence (+) = F ( () ) / / / / / / / / 9/3/7 EECS5 F7 Culler Lec 6 3 9/3/7 EECS5 F7 Culler Lec 6 4

2 Typical Conroller: + oupu + inpu Review: Two Kinds of FSMs Oupu () = G( () ) Nex Moore Machine vs Mealy Machine Inpu Combinaional Logic clr i2 i i o2 o o odd Inpu Oupu () = G( ()) Inpu Oupu () = G( (), Inpu ) Combinaional Logic (+) = F ( (), inpu () ) clr= x x x (+) = F ( (), inpu()) (+) = F ( (), inpu) / / / / / / clr= / / clr=? 9/3/7 EECS5 F7 Culler Lec 6 5 Inpu / Ou Inpu Sae Sae / ou 9/3/7 EECS5 F7 Culler Lec 6 6 Review: Finie Sae Machine Represenaions Saes: deermined by possible values in sequenial sorage elemens Transiions: change of Clock: conrols when can change by conrolling sorage elemens In = In = In = In = 9/3/7 EECS5 F7 Culler Lec 6 7 Sequenial Logic Sequences hrough a series of s Based on sequence of values on inpu signals Clock period defines elemens of sequence Review: Formal Design Process Logic equaions from able: OUT = PS NS = PS xor IN Circui Diagram: ps ns Review of Design Seps:. Circui funcional specificaion 2. Sae Transiion Diagram 3. Symbolic Sae Transiion Table 4. Encoded Sae Transiion Table 5. Derive Logic Equaions 6. Circui Diagram FFs for CL for NS and OUT XOR gae for ns calculaion DFF o hold presen no logic needed for oupu Take his seriously! 9/3/7 EECS5 F7 Culler Lec 6 8

3 Formal Design Process bi sream IN CLK Pariy Checker OUT Sae Transiion Diagram circui is in one of wo s. ransiion on each cycle wih each new inpu, over exacly one arc (edge). Oupu deps on which he circui is in. if even pariy if odd pariy example: even even odd even odd odd even ime Formal Design Process Sae Transiion Table: presen nex OUT IN EVEN EVEN EVEN ODD ODD ODD ODD EVEN Inven a code o represen s: Le = EVEN, = ODD presen (ps) OUT IN nex (ns) Derive logic equaions from able (how?): OUT = PS NS = PS xor IN 9/3/7 EECS5 F7 Culler Lec 6 9 9/3/7 EECS5 F7 Culler Lec 6 Review: Wha s an FSM? Which is which? Nex is funcion of and inpu Moore Machine: oupu is a funcion of he inpua Sae / oupu inpub Mealy Machine: oupu is a funcion of and inpu Ofen PLAs How o quickly implemen he Sae Transiion Diagram? Sae inpua/oupua inpub/oupub 9/3/7 EECS5 F7 Culler Lec 6 9/3/7 EECS5 F7 Culler Lec 6 2

4 One Answer: Xilinx 4 CLB Two 4-inpu funcions, regisered oupu 9/3/7 EECS5 F7 Culler Lec 6 3 9/3/7 EECS5 F7 Culler Lec inpu funcion, combinaional oupu Recall: Parallel o Serial Converer //Parallel o Serial converer module ParToSer(LD, X, ou, CLK); inpu [3:] X; inpu LD, CLK; oupu ou; reg ou; reg [3:] Q; assign ou = Q[]; (posedge CLK) begin if (LD) Q <= X; else Q <= { b,q[3:]}; module // ParToSer One common use of FSMs is in adapers from one subsysem o anoher. differen daa widhs differen bi raes differen proocols, 9/3/7 EECS5 F7 Culler Lec 6 5 9/3/7 EECS5 F7 Culler Lec 6 6

5 Example: Bye-bi sream Bye-bi sream wih Rae Maching Bye FIFO ini / LD bi /pop bi pop bi 2 conroller bi 3 Shif regiser LD bi 4 Serial link bi 5 bi 6 bi 7 / LD 9/3/7 EECS5 F7 Culler Lec 6 7 Bye FIFO ini / LD bi /pop ~ bi bi ~ ~ pop bi 2 ~ conroller bi 3 Shif regiser ~ LD bi 4 ~ Serial link bi 5 ~ bi 6 How would you implemen his FSM? ~ bi 7 / LD 9/3/7 EECS5 F7 Culler Lec 6 ~ 8 Anoher example: bus proocols A bus is: shared communicaion link single se of wires used o connec muliple subsysems Example: Penium Sysem Organizaion Processor/Memory Bus Processor Conrol Memory Inpu Daapah Oupu PCI Bus A Bus is also a fundamenal ool for composing large, complex sysems (more laer in he erm) sysemaic means of absracion 9/3/7 EECS5 F7 Culler Lec 6 9 I/O Busses 9/3/7 EECS5 F7 Culler Lec 6 2

6 Arbiraion for he bus Simple Synchronous Proocol Gran Device Req Device 2 Device N BReq BG I wan he bus nope I sill wan he bus You go i I m done afer his Bus Arbier CMD Address Rd+Addr Mem grabs addr Proc grabs daa Daa Daa Daa2 Cenral arbiraion shown here Used in essenially all processor-memory busses and in highspeed I/O busses 9/3/7 EECS5 F7 Culler Lec 6 2 Even memory busses are more complex han his memory (slave) may ake ime o respond i need o conrol daa rae 9/3/7 EECS5 F7 Culler Lec 6 22 Processor Side of Proocol - skech Simple Synchronous Proocol (con) Idle ~BR proc read Reques bus BR BG Address ~BG BR,RD, addr_enable Daa BR, MDR_enable BReq BG CMD Address Daa I wan he bus nope I sill wan he bus You go i Rd+Addr Mem grabs addr Daa Proc grabs daa I m done afer his Daa2 Memory wais? Addiional oupus? Memory side? Daa 2 ~BR, MDR_enable idle req req w-addr r-daa r-daa2 idle 9/3/7 EECS5 F7 Culler Lec /3/7 EECS5 F7 Culler Lec 6 24

7 Announcemens Reading 8.-4 (sligh change in ordering) HW 2 due omorrow HW 3 will go ou oday Lab lecure on Verilog synhesis Nex week feedback survey Inpu on discussion secions Technology in he News iphone unlocked iphone price drops by $2 Fundamenal Design Principle Divide circui ino combinaional logic and Localize feedback loops and make i easy o break cycles Implemenaion of sorage elemens leads o various forms of sequenial logic Inpus Sae Inpus Combinaional Logic Sorage Elemens Oupus Sae Oupus 9/3/7 EECS5 F7 Culler Lec /3/7 EECS5 F7 Culler Lec 6 26 Forms of Sequenial Logic Asynchronous sequenial logic changes occur whenever inpus change (elemens may be simple wires or delay elemens) Synchronous sequenial logic changes occur in lock sep across all sorage elemens (using a periodic waveform - he clock) General Model of Synchronous Circui clock inpu inpu CL reg CL reg opion feedback oupu Clock 9/3/7 EECS5 F7 Culler Lec 6 27 All wires, excep clock, may be muliple bis wide. Regisers (reg) collecions of flip-flops clock disribued o all flip-flops ypical rae? oupu Combinaional Logic Blocks (CL) no inernal (no feedback) oupu only a funcion of inpus Paricular inpus/oupus are opional Opional Feedback ALL CYCLES GO THROUGH A REG! 9/3/7 EECS5 F7 Culler Lec 6 28

8 Composing FSMs ino larger designs Composing Moore FSMs FSM FSM Moore Moore CL CL CL nex s a e oupu CL nex s a e oupu Synchronous design mehodology preserved 9/3/7 EECS5 F7 Culler Lec /3/7 EECS5 F7 Culler Lec 6 3 Composing Mealy FSMs Recall: Wha makes Digial Sysems ick? Mealy FSM Oupu Oupu Combinaional CL s a e Nex CL s a e Nex Logic Synchronous design mehodology violaed!!! Why do designers used hem? Few s, ofen more naural in isolaion Safe if lach all he oupus» Looks like a mealy machine, bu isn really» Wha happens o he iming? 9/3/7 EECS5 F7 Culler Lec 6 3 clk ime 9/3/7 EECS5 F7 Culler Lec 6 32

9 Recall 6C: Single-Cycle MIPS Recall 6C: 5-cycle Daapah - pipeline IR PC +4 insrucion memory x 3 imm regisers 7 reg[] ALU reg[]+7 Daa memory MEM[r+7] PC +4 insrucion memory x 3 imm regisers 7 reg[] ALU reg[]+7 Daa memory MEM[r+7]. Insrucion Fech LW r3, 7(r) 2. Regiser Read 3. Execue 4. Memory 5. Reg. Wrie. Insrucion Fech LW r3, 7(r) 2. Regiser Read 3. Execue 4. Memory 5. Reg. Wrie 9/3/7 EECS5 F7 Culler Lec /3/7 EECS5 F7 Culler Lec 6 34 FSM iming How long mus his be? Finie Sae Machines in Verilog Sae Time (Clock Period) Mealy oupus Clock Inpus Wha deermines his? inpus combinaional logic nex combinaional logic Moore oupus curren Oupus Sae (inernal) Oupu logic propagaion delay Sae regiser propagaion delay Wha deermines min FSM cycle ime (max clock rae)? 9/3/7 EECS5 F7 Culler Lec /3/7 EECS5 F7 Culler Lec 6 36

10 Verilog FSM - Reduce s example Change he firs o in each sring of s Example Moore machine implemenaion module Reduce(Ou, Clock, Rese, In); oupu Ou; inpu Clock, Rese, In; reg Ou; reg [:] CurrenSae; // regiser reg [:] NexSae; // Sae assignmen localparam STATE_Zero = 2 h, STATE_One = 2 h, STATE_Twos = 2 h2, STATE_X = 2 hx; zero [] one [] wos [] or CurrenSae) begin NexSae = CurrenSae; Ou = b; case (CurrenSae) STATE_Zero: begin // las inpu was a zero if (In) NexSae = STATE_One; STATE_One: begin // we've seen one if (In) NexSae = STATE_Twos; else NexSae = STATE_Zero; STATE_Twos: begin // we've seen a leas 2 ones Ou = ; if (~In) NexSae = STATE_Zero; defaul: begin // in case we reach a bad Ou = bx; Moore Verilog FSM: combinaional par case NexSae = STATE_X; zero [] one [] wos [] include all signals ha are inpu o and oupu equaions 9/3/7 EECS5 F7 Culler Lec 6 37 Compue: oupu = G() 9/3/7 EECS5 F7 Culler Lec 6 nex = F(, in) 38 Moore Verilog FSM: par // Implemen he regiser (posedge Clock) begin module if (Rese) CurrenSae <= STATE_Zero; else CurrenSae <= NexSae; Noe: posedge Clock requires NONBLOCKING ASSIGNMENT. Blocking Assignmen <-> Combinaional Logic Nonblocking Assignmen <-> Sequenial Logic (Regisers) 9/3/7 EECS5 F7 Culler Lec 6 39 zero [] one [] wos [] Mealy Verilog FSM for Reduce-s example module Reduce(Clock, Rese, In, Ou); inpu Clock, Rese, In; oupu Ou; reg Ou; reg CurrenSae; // regiser reg NexSae; localparam STATE_Zero = b, STATE_One = b; Clock) begin if (Rese) CurrenSae <= else CurrenSae <= (In or CurrenSae) begin NexSae = Ou = case (CurrenSae) zero: if (In) NexSae = STATE_Zero; NexSae; CurrenSae; b; STATE_One; one: begin // we've seen one if (In) NexSae = STATE_One; else NexSae = STATE_Zero; Ou = In; case module 9/3/7 EECS5 F7 Culler Lec 6 4 / zero [] one [] / / / Noe: smaller machine Oupu = G(, inpu)

11 Resriced FSM Implemenaion Syle Mealy machine requires wo always blocks Regiser needs posedge Clock block Inpu o oupu needs combinaional block Moore machine can be done wih one always block, bu. E.g. simple couner Very bad idea for general FSMs» This will cos you hours of confusion, don ry i» We will no accep labs wih his syle for general FSMs Use wo always blocks! Moore oupus Share wih regiser, use suiable encoding Single-always Moore Machine (No Allowed!) module reduce (clk, rese, in, ou); inpu clk, rese, in; oupu ou; reg ou; reg [:] ; // regiser parameer zero =, one =, wos = 2; zero [] one [] wos [] 9/3/7 EECS5 F7 Culler Lec 6 4 9/3/7 EECS5 F7 Culler Lec 6 42 Single-always Moore Machine (No Allowed!) All oupus are regisered clk) case () zero: begin ou <= ; if (in) <= one; else <= zero; one: if (in) begin <= wos; ou <= ; else begin <= zero; ou <= ; wos: This is confusing: he oupu does no change unil he nex clock cycle if (in) begin <= wos; ou <= ; else begin <= zero; ou <= ; defaul: begin <= zero; ou <= ; case module 9/3/7 EECS5 F7 Culler Lec 6 43 Finie Sae Machines inpus combinaional logic nex Mealy oupus combinaional logic curren Moore oupus Recommed FSM Verilog implemenaion syle Implemen combinaional logic using one always block Implemen an explici regiser using a second always block 9/3/7 EECS5 F7 Culler Lec 6 44

12 Summary FSMs are criical ool in your design oolbox Adapers, Proocols, Daapah Conrollers, They ofen inerac wih oher FSMs Imporan o design each well and o make hem work ogeher well. Keep your verilog FSMs clean Separae combinaional par from updae Good machine design is an ieraive process 9/3/7 EECS5 F7 Culler Lec 6 45