BLOCK DIAGRAM PIN ASSIGNMENT ICS LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL- TO-LVDS FANOUT BUFFER PRELIMINARY ICS854210

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1 LOW SKEW, DUAL, 1-TO-5 DIFFERENTIAL- TO-LVDS FANOUT BUFFER ICS GENERAL DESCRIPTION The ICS is a low skew, high performance ICS dual 1-to-5 Differential-to-LVDS Fanout Buffer HiPerClockS and a member of the HiPerClockS family of High Performance Clock Solutions from IDT. The ICS is characterized to operate from a power supply. Guaranteed output and partto-part skew characteristics make the ICS ideal for those clock distribution applications demanding well defined performance and repeatability. FEATURES Two differential LVDS bank outputs Two differential LVPECL clock input pairs x, x pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL Maximum output frequency: 2GHz Translates any single ended input signal to LVDS levels with resistor bias on x input Output skew: Part-to-part skew: Propagation delay: 280ps (typical) supply voltage -40 C to 85 C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT A A B B Pulldown Pullup/Pulldown Pulldown Pullup/Pulldown QA0 nqa0 QA1 nqa1 QA2 nqa2 QA3 nqa3 QA4 nqa4 QB0 nqb0 QB1 nqb1 QB2 nqb2 QB3 nqb3 QB4 nqb4 VDDO nqa2 QA2 nqa1 QA1 nqa0 QA0 VDDO QA3 nqa3 QA4 nqa4 QB0 nqb0 QB1 nqb ICS VDD nc A A nc B B GND Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View VDDO QB2 nqb2 QB3 nqb3 QB4 nqb4 VDDO The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT / ICS LVDS FANOUT BUFFER 1 ICS854210CY REV. C MAY 6, 2008

2 TABLE 1. PIN DESCRIPTIONS Number Name 1 V DD 2, 5 nc 3 A 4 A 6 B 7 B 8 GND 9, 16, 25, 32 V DDO 10, 11 nqb4, QB4 12, 13 nqb3, QB3 14, 15 nqb2, QB2 17, 18 nqb1, QB1 19, 20 nqb0, QB0 21, 22 nqa4, QA4 23, 24 nqa3, QA3 26, 27 nqa2, QA2 28, 29 nqa1, QA1 30, 31 nqa0, QA0 NOTE: Type ower nused Description Power supply pin No connect P ulldown Non-inverting differential LVPECL clock input. Inverting differential LVPECL clock input. P. U. Pullup/ Pulldown V D D /2 default when left floating. P ulldown Non-inverting differential LVPECL clock input. Pullup/ Inverting differential LVPECL clock input. Pulldown V D D /2 default when left floating. P ower Power supply ground. P ower Output supply pins. to internal input resistors. See Table 2, Pin Characteristics, for typical P ullup and Pulldown refer values. TABLE 2. PIN CHARACTERISTICS Symbol R PULLDOWN R VDD/ 2 Parameter nput Pulldown Resistor ullup/pulldown Resistors Test Conditions Minimum Typical Maximum I 75 kω P 50 kω Units TABLE 3. CLOCK INPUT FUNCTION TABLE A or B s A or B QA0:QA4, QB0:QB4 0 1 LOW 1 0 HIGH 0 Biased; NOTE 1 LOW 1 Biased; NOTE 1 HIGH Biased; NOTE 1 0 HIGH Biased; NOTE 1 1 LOW NOTE 1: Please refer to the Application Information, Outputs "Wiring nqa0:nqa4, nqb0:nqb4 HIGH LOW HIGH LOW LOW HIGH the Differential to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential to Accept Single Ended Polarity Non Inverting Non Inverting Non Inverting Non Inverting Inverting Inverting Levels". IDT / ICS LVDS FANOUT BUFFER 2 ICS854210CY REV. C APRIL 7, 2008

3 ABSOLUTE MAXIMUM RATINGS Supply Voltage, V DD 4.6V Negative Supply Voltage, V EE -4.6V s, V I -0.5V to V DD + 0.5V Outputs, I O Continuous Current 10mA Surge Current 15mA Operating Temperature Range, T A -40 C to +85 C Storage Temperature, T STG -65 C to 150 C Package Thermal Impedance, θ JA 47.9 C/W (0 lfpm) (Junction-to-Ambient) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods mayaffect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V DD = V DDO = ± 5%, TA = -40 C TO 85 C Symbol V DD V DDO I DD I DDO Parameter ower Supply Voltage utput Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum Typical.. Maximum P V O V Units ma ma TABLE 4B. LVPECL DC CHARACTERISTICS, V DD = V DDO = ± 5%, TA = -40 C TO 85 C Symbol Parameter Test Conditions Minimum Typical Maximum Units A, B V I IH High Current DD = V IN = 3.465V 150 µ A A, B V DD = V IN = 3.465V 150 µ A A, B V I IL Low Current DD = 3.465V, V = 0V -150 µ A IN A, B V DD = 3.465V, V = 0V -10 µ A IN V TH Differential High Threshold Voltage 100 mv V TL Differential Low Threshold Voltage -100 mv V PP Peak-to-Peak Voltage 0.15 V V CMR Common Mode Voltage; NOTE 1, 2 GND V NOTE 1: Common mode voltage is defined as V. I H NOTE 2: For single ended applications, the maximum input voltage for A, A and B, B is V + 0.3V. D D IDT / ICS LVDS FANOUT BUFFER 3 ICS854210CY REV. C APRIL 7, 2008

4 TABLE 4C. LVDS DC CHARACTERISTICS, V DD = V DDO = ± 5%, TA = -40 C TO 85 C Symbol Parameter Min -40 C 25 C 85 C Typ Max V OD Differential Output Voltage 3 0 mv Δ V OD V OD Magnitude Change 50 mv V OS Offset Voltage 1.25 V Δ V OS V OS Magnitude Change 50 mv NOTE 1: Refer to Parameter Measurement Information, " Output Load Test Circuit" diagram. Min Typ 5 Max Min Typ Max Units TABLE 5. AC CHARACTERISTICS, V DD = V DDO = ± 5%, TA = -40 C TO 85 C Symbol Parameter Min -40 C 25 C 85 C Typ fmax Output Frequency GHz t PD Propagation Delay; NOTE ps t sk(o) Output Skew; NOTE 2, 4 ps t sk(pp) Part-to-Part Skew; NOTE 3, 4 ps t R /t F Rise/Fall Time 20% to 80% ps NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. Max Min Typ Max Min Typ Max Units IDT / ICS LVDS FANOUT BUFFER 4 ICS854210CY REV. C APRIL 7, 2008

5 PARAMETER MEASUREMENT INFORMATION V DD ±5% POWER SUPPLY + Float GND V DD, V DDO LVDS Qx nqx SCOPE V PP Cross Points V CMR GND OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nqx Qx nqx PART 1 Qx nqy Qy tsk(o) nqy PART 2 Qy tsk(pp) OUTPUT SKEW PART-TO-PART SKEW V DD V DD out out DC LVDS DC LVDS 100 V OD /Δ V OD out V OS /Δ V OS out V OS SETUP V OD SETUP nqax, nqbx QAx, QBx 20% 80% 80% t R t F 20% V OD A, B A, B nqax, nqbx QAx, QBx t PD OUTPUT RISE/FALL TIME PROPAGATION DELAY IDT / ICS LVDS FANOUT BUFFER 5 ICS854210CY REV. C APRIL 7, 2008

6 APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD /2 is generated by the bias resistors, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V DD =, V_REF should be 1.25V and R2/ = VDD Single Ended Clock 1K V_REF C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: / INPUTS For applications not requiring the use of a differential input, both the and pins can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from to ground. OUTPUTS: LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. IDT / ICS LVDS FANOUT BUFFER 6 ICS854210CY REV. C APRIL 7, 2008

7 LVPECL CLOCK INPUT INTERFACE The / accepts LVPECL, CML, SSTL and other differential signals. Both V SWING and V OH must meet the V PP and V CMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS / input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. CML 50 R2 50 HiPerClockS / CML Built-In Pullup 100 HiPerClockS / FIGURE 2A. HIPERCLOCKS / INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER FIGURE 2B. HIPERCLOCKS / INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER R3 125 R4 125 LVPECL C1 R3 84 R4 84 LVPECL 84 R2 84 HiPerClockS R R C2 125 R2 125 HiPerClockS / FIGURE 4C. HIPERCLOCKS / INPUT DRIVEN BY A LVPECL DRIVER FIGURE 2D. HIPERCLOCKS / INPUT DRIVEN BY A LVPECL DRIVER WITH AC COUPLE 2.5V 2.5V SSTL Zo = 60 Ohm Zo = 60 Ohm R3 120 R4 120 HiPerClockS / LVDS R5 100 C1 C2 R3 1K R4 1K HiPerClockS / 120 R K R2 1K FIGURE 2E. HIPERCLOCKS / INPUT DRIVEN BY AN SSTL DRIVER FIGURE 2F. HIPERCLOCKS / INPUT DRIVEN BY A LVDS DRIVER IDT / ICS LVDS FANOUT BUFFER 7 ICS854210CY REV. C APRIL 7, 2008

8 LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. LVDS_Driv er Ohm Differiential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION IDT / ICS LVDS FANOUT BUFFER 8 ICS854210CY REV. C APRIL 7, 2008

9 RELIABILITY INFORMATION TABLE 7. θ JA VS. AIR FLOW TABLE FOR 32L LQFP θ by Velocity (Linear Feet per Minute) JA Single-Layer PCB, JEDEC Standard Test Boards 67.8 C/W 55.9 C/W 50.1 C/W Multi-Layer PCB, JEDEC Standard Test Boards 47.9 C/W 42.1 C/W 39.4 C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS is: 394 IDT / ICS LVDS FANOUT BUFFER 9 ICS854210CY REV. C APRIL 7, 2008

10 PACKAGE OUTLINE - Y SUFFIX FOR 32L LQFP TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM N 32 A A A b c D 9.00 BASIC D1 2 E E BASIC 5.60 Ref 9.00 BASIC 7.00 BASIC D. E Ref. e 0.80 BASIC L θ ccc Reference Document: JEDEC Publication 95, MS-026 IDT / ICS LVDS FANOUT BUFFER 10 ICS854210CY REV. C APRIL 7, 2008

11 TABLE 9. ORDERING INFORMATION Part/Order Number ICS854210CY ICS854210CYT ICS854210CYLF ICS854210CYLFT NOTE: Parts that are ordered Marking ICS854210CY ICS854210CY ICS854210CYL ICS854210CYL with an "LF" suffix Package Shipping Packaging Temperature 32 lead LQFP tray -40 C to 85 C 32 lead LQFP 1000 tape & reel -40 C to 85 C 32 Lead "Lead-Free" LQFP tray -40 C to 85 C 32 Lead "Lead-Free" LQFP 1000 tape & reel -40 C to 85 C to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT / ICS LVDS FANOUT BUFFER 11 ICS854210CY REV. C APRIL 7, 2008

12 Innovate with IDT and accelerate your future networks. Contact: For Sales (inside USA) (outside USA) Fax: For Tech Support Corporate Headquarters Integrated Device Technology, Inc Silver Creek Valley Road San Jose, CA United States (inside USA) (outside USA) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA