PI6C49S1510 Rev J

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1 High Performance Differential Fanout Buffer Features ÎÎ10 differential outputs with 2 banks ÎÎUser configurable output signaling standard for each bank: LVDS or LVPECL or HCSL ÎÎLVCMOS reference output up to 200MHz ÎÎUp to 1.5GHz output frequency for differential outputs ÎÎUltra low additive phase jitter: < 0.03 ps (typ) (differential MHz, 12KHz to 20MHz integration range); < 0.02 ps (typ) (differential MHz, 10kHz to 1MHz integration range) ÎÎSelectable reference inputs support either single-ended or differential or Xtal ÎÎLow skew between outputs within banks (<40ps) ÎÎLow delay from input to output (Tpd typ. < 1.7ns) ÎÎSeparate Input output supply voltage for level shifting ÎÎ2.5V / 3.3V power supply ÎÎIndustrial temperature support ÎÎTQFN-48 package Block Diagram Description The is a high performance fanout buffer devicewhich supports up to 1.5GHz frequency. It also integrates a unique feature with user configurable output signaling standards on per bank basis which provide great flexibilities to users. The device also uses Pericom's proprietary input detection technique to make sure illegal input conditions will be detected and reflected by output states. This device is ideal for systems that need to distribute low jitter clock signals to multiple destinations. Applications ÎÎNetworking systems including switches and Routers ÎÎHigh frequency backplane based computing and telecom platforms Pin Configuration (48-Pin TQFN) QBO+ QBO- QB1+ QB1- QB2+ QB2- QB3+ QB3- QB4+ QB4- GND OPMODEA_0 VDD X1 X2 GND IN_SEL_0 IN0+ IN0- IN_SEL_1 OPMODEB_0 GND GND OPMODEA_1 Sync_OE Ref_Out GND VDD IN1+ IN1- OPMODEB_1 Iref GND OPMODEA[1:0] QA[0:4] 5 QAO+ QAO X1 X2 IN0+ IN0- IN1+ IN1- OSC OPMODEB[1:0] QB[0:4] 5 Ref_Out QA1+ QA1- QA2+ QA IN_SEL[1:0] Sync_OE Iref Sync QA3+ QA3- QA4+ QA

2 Pinout Table Pin # Pin Name Type Description 1,2 3,4 QA0+ QA1+ Bank A differential output pair 0. Pin selectable Bank A differential output pair 1. Pin selectable 5,8,29,32,45 Power Power supply pins for IO 6,7 9,10 11,12 QA2+ QA3+ QA4+ QA0- QA1- QA2- QA3- QA4-13,18,24,37,43,48 GND Power Power supply ground 14,47 OPMODEA Input Pulldown Bank A differential output pair 2. Pin selectable Bank A differential output pair 3. Pin selectable Bank A differential output pair 4. Pin selectable mode select for Bank A. See Table 2 for functions, LVCMOS/LVTTL interface levels 15,42 V DD Power Power supply pins 16 X1 Input XTAL input, can also be used as single ended input pin 17 X2 19,22 IN_SEL Input Pulldown 20 IN0+ Input Pulldown Reference input 0 21 IN0- Input Pull-up/ Pulldown 23,39 OPMODEB Input Pulldown 26,25 28,27 31,30 34,33 QB4+ QB3+ QB2+ QB1+ QB4- QB3- QB2- QB1- XTAL output. If X1 is used as a single ended input pin, X2 is to be left open Input clock sele ct. See Table 1 for function. LVC- MOS/LVTTL interface levels. Inverted reference input 0, internal bias to V DD/2 mode select for Bank B. See Table 2for functions, LVCMOS/LVTTL interface levels Bank B differential output pair 4. Pin selectable Bank B differential output pair 3. Pin selectable Bank B differential output pair 2. Pin selectable Bank B differential output pair 1. Pin selectable 2

3 Pinout Table (Continued..) Pin # Pin Name Type Description 36,35 QB0+ QB0-38 Iref 40 IN1- Input Pull-up/ Pulldown Bank B differential output pair 0. Pin selectable A fixed precision resistor (475ohm) from this pin to ground provides a reference current for HCSL mode. If LVPECL or LVDS mode chosen, pin can be left open Inverted reference input, internal bias to V DD/2 41 IN1+ Input Pulldown Reference input 1 44 Ref_Out Reference output, CMOS 46 Sync_OE Input Pulldown Synchronous output enable for Ref_Out, see Table 3 for functions Function Table Table 1: Input select function IN_SEL [1] IN_SEL [0] Function 0 0 IN0 is the selected reference input 0 1 IN1 is the selected reference input 1 X XTAL is the selected input Table 2: Mode select function OPMODEA/B [1] OPMODEA/B [0] Bank A / Bank B Mode 0 0 LVPECL 0 1 LVDS 1 0 HCSL 1 1 Hi-Z Table 3: Reference output enable function Sync_OE Ref_Out 0 Hi-Z 1 enabled Table 4: Illegal input level function Input illegal status Input open Input both high Input both low status Logic Low Logic Low Logic Low 3

4 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested) Storage temperature to +150ºC Supply Voltage to Ground Potential (V DD ) to +4.6V Inputs (Referenced to GND) to V DD +0.5V Clock (Referenced to GND) to V DD +0.5V Latch up...200ma ESD Protection (Input) V min (HBM) Junction Temperature C max Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Power Supply Characteristics and Operating Conditions Symbol Parameter Test Condition Min. Typ. Max. Units V DD Core Supply Voltage V V DDO Supply Voltage V I DD Core Power Supply Current I DDO All LVPECL outputs unloaded ma Power Supply Current All LVDS outputs loaded All HCSL outputs unloaded T A Ambient Operating Temperature C DC Electrical Specifications - Differential Inputs Symbol Parameter Min. Typ. Max. Units I IH Input High current Input = V DD 150 ua I IL Input Low current Input = GND -150 ua C IN Input capacitance 3 PF V IH Input high voltage V DD+0.3 V V IL Input low voltage -0.3 V V ID Input Differential Amplitude PK-PK 0.15 V DD-0.85 V V CM Common model input voltage GND V DD-0.85 V ISO MUX MUX isolation -89 dbc 4

5 DC Electrical Specifications - LVCMOS Inputs Symbol Parameter Conditions Min. Typ. Max. Units I IH Input High current Input = V DD 150 ua I IL Input Low current Input = GND -150 ua V IH Input high voltage V DD=3.3V 2.0 V DD+0.3 V V IL Input low voltage V DD=3.3V V V IH Input high voltage V DD=2.5V 1.7 V DD+0.3 V V IL Input low voltage V DD=2.5V V DC Electrical Specifications- LVPECL s Parameter Description Conditions Min. Typ. Max. Units V OH High voltage V DDO-1.4 V DDO-0.9 V V OL Low voltage V DDO-2.1 V DDO-1.7 V DC Electrical Specifications- LVDS s Parameter Description Conditions Min. Typ. Max. Units V OH High voltage V V OL Low voltage V Vocm commode voltage 1.25 V DVocm Change in Vocm between completely output states 50 mv Ro impedance W DC Electrical Specifications HCSL s Parameter Description Conditions Min. Typ. Max. Units V OH High voltage mv V OL Low voltage mv 5

6 DC Electrical Specifications LVCMOS Parameter Description Conditions Min. Typ. Max. Units V OH V OL V OH V OL R IUT High voltage V DDO=3.3V +/-5%, I OH = 8mA 2.3 V V DDO=2.5V +/- 5%, I OH = 8mA 1.5 V Low voltage V DDO=3.3V +/-5%, I OL = -8mA 0.5 V V DDO=2.5V +/- 5%, I OL = -8mA 0.4 V High voltage V DDO=3.3V +/-5%, I OH = 24mA 2.1 V V DDO=2.5V +/- 5%, I OH = 16mA 1.5 V Low voltage V DDO=3.3V +/-5%, I OL = -24mA 1 V V DDO=2.5V +/- 5%, I OL = -16mA 0.8 V Impedance V DDO = 3.3V ± 5% 17 Ω V DDO = 2.5V ± 5% 22 Ω AC Electrical Specifications Differential s Parameter Description Conditions Min. Typ. Max. Units F OUT Clock output frequency T r rise time From 20% to 80% T f fall time From 80% to 20% T ODC duty cycle Frequency<650MHz V PP T j swing Single-ended Buffer additive jitter RMS LVPECL, LVDS 1500 HCSL LVPECL LVDS HCSL LVPECL LVDS HCSL LVPECL, HCSL LVDS LVPECL <1GHz LVPECL >1GHz 400 LVDS outputs MHz, 12kHz to 20MHz 0.03 ps MHz, 10kHz to 1MHz 0.02 ps V CROSS Absolute crossing voltage HCSL 460 mv DV CROSS Total variation of crossing voltage HCSL 140 mv T SK T PD Skew Propagation Delay 10 outputs devices, outputs in same tank, with same load, at DUT. MHz ps ps % mv ps LVPECL, 3.3V, 100MHz 1650 ps 3.3V, 100MHz 2000 ps

7 T OD Valid to HiZ 200 ns T OE HiZ to valid 200 ns T P2P Skew Part to Part Skew ps Notes: 1. This parameter is guaranteed by design AC Electrical Specifications CMOS Parameter Description Conditions Min. Typ. Max. Units F OUT T j Ref_Out frequency XTAL input MHz Reference input 200 MHz Buffer additive jitter RMS XTAL input 0.3 ps Reference input 0.03 ps t r/ t f Rise time, Fall time C L = 10pF 1.5 ns T ODC duty cycle C L = 10pF % t PD Propagation delay 3.3V, 25MHz 2700 ps t S Setup time 300 ps t SOD Clock edge to output disable Ref_Out 2 4 cycles t SOE Clock edge to output enable Ref_Out 2 4 cycles Crystal Characteristics Parameter Min. Typ. Max. Units Mode of Oscillation Fundamental Frequency Range MHz Equivalent Series Resistance (ESR) 70 Ω Shunt Capacitance 7 pf Load Capacitance pf Drive Level 500 µw Recommended Crystals Pericom recommends: a) GC XTAL 49S/SMD(4.0 mm), 25M, CL=18pF, +/-30ppm b) FY , SMD 5x3.2(4P), 25M, CL=18pF, +/-30ppm c) FL , SMD 3.2x2.5(4P), 25M, CL=18pF, +/-20ppm 7

8 Propagation Delay Skew Skew T SK Propagation Delay T PD VOH IN+/IN- TPLHx TPHLx VOL VOH IN+/INtPD tpd VOH CLKn VOL QA/QB VOL TSK TSK VOH tr tf CLKn+1 VOL TPLHy TPHLy TSK = TPLHy - TPLHx or TSK = TPHLy - TPHLx Part to Part Skew Part-to-Part Skew VOH IN+/IN- TPLH1 TPHL1 VOL VOH Part1 CLK VOL TSK TSK VOH Part2 CLK VOL TPLH2 TPHL2 TSK = TPLH2 - TPLH1 or TSK = TPHL2 - TPHL1 8

9 LVPECL/ LVDS Swing vs. Frequency Propagation Delay vs. Temperature 1.5GHz LVEPCL/ LVDS Waveform 2.5V LVPECL Waveform 3.3V LVPECL Waveform 2.5V LVDS Waveform 3.3V LVDS Waveform Rev J August 2016

Additive jitter = ( jitter 2 - Input jitter 2 ) Total phase jitter with 25MHz XTAL ~ 264fs RMS (12kHz

10 Phase Noise and Additive Jitter phase noise (Dark Blue) vs Input Phase noise (light blue) Additive jitter is calculated at MHz~27fs RMS (12kHz to 20MHz). Additive jitter = ( jitter 2 - Input jitter 2 ) Total phase jitter with 25MHz XTAL ~ 264fs RMS (12kHz ~20MHz) Configuration Test Load Board Termination for LVPECL/ LVDS s LVPECL/ LVDS Buffer V DDQx Z = o L = 0 ~ 10 in. 100Ω Z = o 1* 1* *Remove for LVDS 10

11 Configuration Test Load Board Termination for HCSL s DUT Rs 33Ω 5% Rs 33Ω 5% TLA TLB Clock Clock# 475Ω 1% Rp 49.9Ω 1% Rp 49.9Ω 1% 2pF 5% 2pF 5% Configuration Test Load Board Termination for LVCMOS s 3.3V ±5% V DD V DDO GND 10pF 11

12 Application Information Wiring the differential input to accept single ended levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V DD /2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to postion the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and V DD = 3.3V, V_REF should be 1.25V and R1/R2 = V DD Single Ended Clock Input R1 1K CLK /CLK C1 0.1µ R2 1K Power Supply Filtering Techniques Figure 1. Single-ended input to Differential input device As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. All power pins should be individually connected to the power supply plane through vias, and 0.1μF an 1μF bypass capacitors should be used for each pin. V DD V DD 1µF 1µF 12

13 Driving X1 with a Single Ended Input Single Ended Input, AC couple CMOS Clock Rs X1 X2 Osc Input CMOS Clock Rs Differential Clock Input Single Ended Input, DC couple VDD Single Ended Input, DC couple CMOS Clock Rs VDD 100Ω 100Ω Differential Clock Input CMOS Clock Rs Differential Clock Input LVPECL, AC Couple, Thevenin Equivalent LVPECL, DC Couple, Thevenin Equivalent QAn+/ QBn+ RPU QAn+/ QBn+ RPU LVPECL QAn-/ QBn- RT RPD 100Ω Differential RPU RT RPD RT RPU RPD 3.3V 160Ω 2.5V 91Ω 120Ω 82Ω Ω LVPECL Receiver LVPECL QAn-/ QBn- 100Ω Differential RPU RPD 3.3V 120Ω 82Ω 2.5V Ω RPD RPU RPD LVPECL Receiver 13

14 LVDS DC Couple LVDS AC Couple at Load QAn+/ QBn+ QAn+/ QBn+ LVDS 100Ω Differential 100Ω LVDS Receiver LVDS 100Ω Differential 100Ω kω Vbias kω QAn-/ QBn- QAn-/ QBn- LVDS AC Couple with Internal Termination Single Ended LVPECL, DC Couple - 2V LVDS QAn+/ QBn+ 100Ω Differential Vbias LVPECL QAn+/ QBn+ - 2V QAn-/ QBn- QAn-/ QBn- Single Ended LVPECL, DC Couple, Thevenin Equivalent Single Ended LVPECL, AC Couple, Thevenin Equivalent LVPECL QAn+/ QBn+ RPU RPU RPD 3.3V 120Ω 82Ω RPU RPD LVPECL QAn+/ QBn+ RT RT Load QAn-/ QBn- RPD 2.5V Ω QAn-/ QBn- RT 3.3V 160Ω 2.5V 91Ω 14

15 Clock IC crystal input guide LVPECL/ LVDS AC and DC input Clock IC Rf *Remove for LVDS 0.1uF (For AC Couple Only) IN+ C_in XTL_IN C_out XTL_OUT 1* 100Ω Differential 100Ω Input Cb Crystal (CL) Cb IN- 1* 0.1uF (For AC Couple Only) C1 C2 15

16 Clock IC Crystal loading cap. design guide Clock IC Rf CL =crystal spec. loading cap. C_in XTL_IN Cb C_out XTL_OUT C_in/out = (3~5pF) of IC pin cap. Cb = PCB trace (2~4pF) C1,C2 = load cap. of design Crystal (CL) Cb Rd = 50 to 100ohm drive level limit C1 C2 Design guide: C1=C2=2 *CL - (Cb +C_in/out) to meet target +/-ppm < 20 ppm Example1: Select CL=18 pf crystal, C1=C2=2*(18pF) (4pF+5pF)=27pF, check datasheet too Example2: For higher frequency crystal (=>20MHz), can use formula C1=C2=2*(CL-6), can do fine tune of C1, C2 for more accurate ppm if necessary Thermal Information Symbol Description Condition Θ JA Junction-to-ambient thermal resistance Still air C/W Θ JC Junction-to-case thermal resistance 9.10 C/W 16

17 Packaging Mechanical: 48-Pin TQFN (ZD) Ordering Information Ordering Code Package Code Package Type Operating Temperature ZDIE ZD Pb-free & Green, 48-pin TQFN -40 C to 85 C ZDIEX ZD Pb-free & Green, 48-pin TQFN, Tape & Reel -40 C to 85 C Notes: 1. Thermal characteristics can be found on the company web site at 2. E denotes Pb-free and Green 3. Adding an X at the end of the ordering code denotes tape and Reel packaging Pericom Semiconductor Corporation

PI6LC48L0201A 2-Output LVDS Networking Clock Generator

PI6LC48L0201A 2-Output LVDS Networking Clock Generator Features ÎÎTwo differential LVDS output pairs ÎÎSelectable crystal oscillator interface or LVCMOS/LVTTL single-ended clock input ÎÎSupports the following output frequencies: 62.5MHz, 125MHz, 156.25MHz