Instructors: Randy H. Katz David A. PaHerson hhp://inst.eecs.berkeley.edu/~cs61c/fa10. Fall Lecture #9. Agenda

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1 CS 61C: Great Ideas in Computer Architecture (Machine Structures) Instructors: Randy H. Katz David A. PaHerson hhp://inst.eecs.berkeley.edu/~cs61c/fa10 Fall Lecture #9 1 Agenda InstrucTon Stages Revisited Administrivia Technology Break Rise of the Warehouse- Scale Computer Fall Lecture #9 2 1

2 Agenda InstrucTon Stages Revisited Administrivia Technology Break Rise of the Warehouse- Scale Computer Fall Lecture #9 3 InstrucTon Level Parallelism P 1 P 2 P 3 P 4 P 5 P 6 P 7 P 8 P 9 P 10 P 11 P 12 Instr 1 IF ID ALU MEM WR Instr 2 IF ID ALU MEM WR IF ID ALU MEM WR Instr 3 IF ID ALU MEM WR Instr 4 Instr 5 Instr 6 Instr 7 Instr 8 IF ID ALU MEM WR IF ID ALU MEM WR IF ID ALU MEM WR IF ID ALU MEM WR IF ID ALU MEM WR Fall Lecture #8 4 2

3 Conceptual MIPS Datapath Fall Lecture #9 5 Stages of the Datapath (1/5) There is a wide variety of MIPS instructons: so what general steps do they have in common? Stage 1: Instruc(on Fetch No maher what the instructon, the 32- bit instructon word must first be fetched from memory (the cache- memory hierarchy) Also, this is where we Increment PC (that is, PC = PC + 4, to point to the next instructon: byte addressing so + 4) Fall Lecture #8 6 3

4 Stages of the Datapath (2/5) Stage 2: Instruc(on Decode Upon fetching the instructon, we next gather data from the fields (decode all necessary instructon data) First, read the opcode to determine instructon type and field lengths Second, read in data from all necessary registers For add, read two registers For addi, read one register For jal, no reads necessary Fall Lecture #8 7 Stages of the Datapath (3/5) Stage 3: ALU (ArithmeTc- Logic Unit) Real work of most instructons is done here: arithmetc (+, -, *, /), shihing, logic (&, ), comparisons (slt) What about loads and stores? lw $t0, 40($t1) Address we are accessing in memory = the value in $t1 PLUS the value 40 So we do this additon in this stage Fall Lecture #8 8 4

5 Stages of the Datapath (4/5) Stage 4: Memory Access Actually only the load and store instructons do anything during this phase; the others remain idle during this phase or skip it all together Since these instructons have a unique step, we need this extra phase to account for them As a result of the cache system, this phase is expected to be fast Fall Lecture #8 9 Stages of the Datapath (5/5) Stage 5: Register Write Most instructons write the result of some computaton into a register E.g.,: arithmetc, logical, shihs, loads, slt What about stores, branches, jumps? Don t write anything into a register at the end These remain idle during this fihh phase or skip it all together Fall Lecture #8 10 5

6 Latency: the Tme to access first item Bandwidth: # of items accessed per unit Tme Historically, bandwidth has improved much faster than latency Why? Limits to Performance: Latency vs. Bandwidth Bandwidth improves faster than latency Latency improves faster than bandwidth Fall Lecture #8 11 Latency vs. Bandwidth: Physical Analogy Time to first drop Time to fill glass Water per Tme Water Tank Glass Glass Length and diameter of pipes affects latency and bandwidth Fall Lecture #8 12 6

7 Latency vs. Bandwidth: Which is Faster? SD SF, 1 Truck, 10 hours, 1000 by 1 TByte Disks (1 PByte) Time to first byte: Time to last byte: Bandwidth: SD SF, 100 gbps fiber link (10 GB per sec) Time to first byte: Time to last byte: Bandwidth: Fall Lecture #8 13 Latency vs. Bandwidth: Which is Faster? SD SF, 1 Truck, 10 hours, 1000 by 1 TByte Disks (1 PByte) Time to first byte: 10 hours Time to last byte: 10 hours Bandwidth: 100 TBytes/hr (222 Gbps) SD SF, 100 Gbps fiber link (10 GB per sec) Time to first byte: 2.6 ms (speed of 500 mi!) Time to last byte: 28 hours Bandwidth: 10 GB/s Fall Lecture #8 14 7

8 Agenda Stages of an InstrucTon Revisited Administrivia Technology Break Rise of the Warehouse- Scale Computer Fall Lecture #9 15 Administrivia Due dates for Project 2/First Part (Saturday, 18 September) and Project 2/Second Part (Saturday, 25 September) Midterm ExaminaTon, 6 October, 6-9 PM, 1 Pimentel Fall Lecture #9 16 8

9 Agenda Stages of an InstrucTon Revisited Administrivia Technology Break Rise of Warehouse- Scale Computers Fall Lecture #9 17 Agenda Stages of an InstrucTon Revisited Administrivia Technology Break Rise of Warehouse- Scale Computers Fall Lecture #9 18 9

10 Growth in Access Devices Fall Lecture #9 19 The ARM Inside the iphone Fall Lecture #

11 iphone Innards 1 GHz ARM Cortex A8 Fall Lecture #8 21 E.g., Google s Oregon Datacenter Fall Lecture #

12 Energy ProporTonal CompuTng The Case for Energy- ProporTonal CompuTng, Luiz André Barroso, Urs Hölzle, IEEE Computer December 2007 It is surprisingly hard to achieve high levels of utlizaton of typical servers (and your home PC or laptop is even worse) Figure 1. Average CPU utlizaton of more than 5,000 servers during a six- month period. Servers are rarely completely idle and seldom operate near their maximum utlizaton, instead operatng Fall Lecture #9 most of the Tme at between 10 and 50 percent of their maximum 24 Energy ProporTonal CompuTng The Case for Energy- ProporTonal CompuTng, Luiz André Barroso, Urs Hölzle, IEEE Computer December 2007 Doing nothing well NOT! Energy Efficiency = UTlizaTon/Power Figure 2. Server power usage and energy efficiency at varying utlizaton levels, from idle to peak performance. Even an energy- efficient server stll consumes about half its full power when doing virtually no work. Fall Lecture #

13 Energy ProporTonal CompuTng The Case for Energy- ProporTonal CompuTng, Luiz André Barroso, Urs Hölzle, IEEE Computer December 2007 CPU energy improves, but what about the rest of the server architecture? Figure 3. CPU contributon to total server power for two generatons of Google servers at peak performance (the first two bars) and Fall 2010 for the - - Lecture later generaton #9 at idle (the rightmost bar). 26 Energy ProporTonal CompuTng The Case for Energy- ProporTonal CompuTng, Luiz André Barroso, Urs Hölzle, IEEE Computer December 2007 Doing nothing VERY well Design for wide dynamic power range and ac(ve low power modes Energy Efficiency = UTlizaTon/Power Figure 4. Power usage and energy efficiency in a more energy- proportonal server. This server has a power efficiency of more than 80 percent of its peak value for utlizatons of 30 percent and above, with efficiency remaining above 50 percent for utlizaton levels as low as 10 percent. Fall Lecture #

14 Energy Use In Datacenters Datacenter Energy Overheads Fall Lecture #9 28 Michael PaHerson, Intel LBNL Datacenter Power Peak Power % Fall Lecture #

15 Nameplate vs. Actual Peak Component CPU Memory Disk PCI Slots Mother Board Fan System Total Peak Power 40 W 9 W 12 W 25 W 25 W 10 W Count Total 80 W 36 W 12 W 50 W 25 W 10 W 213 W Nameplate peak Measured Peak 145 W (Power- intensive workload) In Google s world, for given DC power budget, deploy as many machines as possible X. Fan, W- D Weber, L. Barroso, Power Provisioning for a Fall Lecture #9 Warehouse- sized Computer, ISCA 07, San Diego, (June 2007). 32 Server Innards Fall Lecture #

16 Server Internals Fall Lecture #8 34 Server Internals Google Server Fall Lecture #

17 Summary Five Stages/Phases of an InstrucTon InstrucTon Fetch (IF) InstrucTon Decode (ID) Execute (ALU) Memory (MEM) Write Results (WR) Bandwidth vs. Latency Easier to increase bandwidth than reduce latency Rise of the Warehouse- Scale Computer Energy ProporTonal CompuTng Power (WaHs), Energy (Power x Time, WaH- hours) Subject to responsiveness goals, drive nodes to higher utlizaton to achieve beher energy efficiency Fall Lecture #