VMIVME Scanning 14-bit Analog-to-Digital Converter Board with Programmable Gain Memory

Transcription

1 Scanning 14-bit Analog-to-Digital Converter Board with Programmable Gain Memory 64 differential or single-ended inputs 14-bit A/D conversion 58 khz conversion rate Program-selectable scanning of 16, 32, 48, or 64 channels Continually digitizes all input channels and stores the results Six operating modes Autoscanning mode Single channel random polling mode Timed burst mode Locally triggered burst mode Remotely triggered burst mode Gain loading mode Programmed VMEbus interrupts User-programmable interval timer Software-programmable gain 1, 10, 100 External trigger to synchronize multiple boards simultaneously Jumper-selectable A/D ranges of 0 to +5, 0 to +10, ± 2.5, ±5, and ±10 V Optional low pass filter Overvoltage protected inputs 1,024-word data buffer (16-word deep buffer x 64 channels) Selectable output coding Powers up in autoscanning mode with gain of 1 APPLICATIONS Factory automation and instrumentation Process control and monitoring Laboratory instrumentation Machine monitoring Data acquisition and control INTRODUCTION This product is designed to support 64 channels of differential or single-ended wide range (±25 mv to ±10 V) analog inputs. The board supports the following operating modes which are described below: Autoscanning Single Channel Random Polling Timed Burst Locally Triggered Burst Remotely Triggered Burst Gain Loading One thousand and twenty-four dual-port Data Registers provide storage for continuous scanning of all channels. The scanning modes are executed automatically at powerup, system reset, or are entered under program control. The dual-port registers allow VMEbus access at any time to read the latest stored data. Channel gain can be jumper selected as x1, x10, or x100, or can be software programmed individually for each channel. Scan rate is programmable up to 58 kcps (thousand channels/s. Low pass input filters are available. A functional block diagram is provided in Figure 1, and the Ordering Options are provided on the first page of this specification. Ordering Options April 14, E A B C D E F * 0 A = Input Filter Options 0 = No Filter 1 = 10 Hz ±24% (-3 db) 2 = 50 Hz ±24% (-3 db) 3 = 100 Hz ±24% (-3 db) 4 = 500 Hz ±24% (-3 db) 9 = 1.6 khz ±24% (-3 db) B = 0 (Option reserved for future use) C = Input Option 0 = 64 Diff/SE Analog Input Channels 1 = 64 SE Analog Inputs with Improved High Frequency Rejection Connector Data Style Recommended Connecting Component P3 and P4 I/O Connectors 64-pin IDC 96-pin Discrete Wire Mating Connector (64-pin) Strain Relief (for 64-pin Connectors) Mating Connector (96-pin Discrete) Female Crimp Contacts (96-pin Discrete) Connector Housing (for 96-pin Connectors) Panduit E Panduit AMP AMP ** Harting pin IDC Mating Connector (96-pin Mass Terminated) ERNI inch Ribbon Cable ERNI (96-pin Mass Terminated) Strain Relief Insert (0.033-inch Ribbon Cable) Connector Housing (for 96-pin Connectors) PC Board I/O Connector Part Number Notes Harting Harting Panduit A * -9BC must be ordered when VMIC signal conditioning products are coupled with the. ** AMP crimp tool part number For Ordering Information, Call: or FAX (256) info@vmic.com Web Address: Copyright March 1995 by VMIC Specifications subject to change without notice. VMIC South Memorial Parkway Huntsville, Alabama

2 The employs an unbuffered 64-channel input multiplexer. Systems Integrators must consider source impedances and cable length when using this board unless the VMIVME-3413, VMIVME-3417A, VMIVME-3418, or other signal conditioning is used. If these signal conditioning products are used with the, then the -9BC must be ordered. In those applications where no signal conditioning board is used or where extremely low noise is required, VMIC recommends the VMIVME FUNCTIONAL CHARACTERISTICS (Typical at +25 C and rated power supplies, unless otherwise stated.) Operating Modes: Autoscanning Mode: This default operating mode is selected by a reset operation, or by clearing both CSR Mode control bits. All active channels are scanned continuously in this mode, and any channel value can be read at any time. Single Channel Random Polling Mode: Each input channel is accessed individually, and the digitized channel value is read from the Converter Data Register (CDR). Timed Burst Mode: A single data burst (scan of all buffer locations) is acquired at the end of a programmed interval, or the process can be repetitive. Locally Triggered Burst: A single burst is initiated through the Control and Status Register (CSR). Remotely Triggered Burst: A single data burst (scan of all enabled channels) is initiated through the P2 connector by an external TTL trigger source. Gain Loading Mode: If the board is jumper configured for automatic gain control, gain loading is performed by first selecting the gain loading mode, and by then loading the gain code for each channel into a 64-location gain buffer. The gain codes (0 for x1, 1 for x10, 2 for x100) for all channels are initialized to zero (gain = x1) automatically after a reset operation. Channel Autogain: The unique gain code for each channel is loaded from the VMEbus into a gain buffer (see Gain Loading Mode). The assigned code is retrieved from the buffer in real-time for each channel acquisition. Synchronization: A single scan or burst, can be initiated by an external TTL trigger through the P2 connector (Remotely Triggered Burst), or locally through the CSR (Locally Triggered Burst). Either event generates a P2 trigger output, which can be used to synchronize up to 15 boards. Board Address: Jumper located on word boundary anywhere in the short I/O A16 space, or the standard A24 space. Required word boundary is 1000h in either space. VMEbus Access: Response to address modifiers is jumper-selectable as: Short I/O A16 or standard A24 address space Supervisory or user privilege, or both Data or program access VMEbus Compliance: This product complies with VMEbus Specification ANSI/IEEE STD IEC 821 and 297 with the following mnemonics: A24/A16:D16/D8 (EO) DTB Slave Interrupter I(1 to 7) ROAK (DYN) Interrupter Vector: D08 (O) (DYN) 6U form factor VMEbus Interrupt: An interrupt request can be generated at the end of a buffer scan in all modes except autoscanning mode. Response vectors are controlled through Interrupt Vector Registers. Data Ready Flag: A data ready flag in the CSR is set when the data buffer is filled (endscan) or half-filled (midscan). Interval Timer: Bursts intervals of up to 536 s are provided by a programmable interval timer. Reset Operations: Board reset occurs in response to a system reset or by setting a reset bit in the CSR. For programming-free initial operation, a reset operation automatically establishes the following default conditions: Autoscanning mode 64-channel block size 64-channel data buffer Channel Gain = x1 PGA: Channel gains of x1, x10, and x100 are selected through a Programmable Gain Amplifier (PGA). PGA gain can be jumper configured with a single gain for all channels, or it can be controlled in real-time with unique gains assigned for each channel. See Channel Autogain. Panel Indicator: Program-controlled front panel LED is energized during reset, and is extinguished through the CSR. Board Identification: A Board Identification Register (BIR) contains the identification code. INPUT CHARACTERISTICS Number of Input Channels: 64 differential or single-ended channels 2 For Ordering Information, Call: or FAX (256)

3 Full-Scale Input Ranges: ±2.5, ±5, ±10, 0 to +5, 0 to +10 V; jumper-selectable Channel Gain: Program selected or jumper selected as x1, x10, or x100. See Channel Autogain. Full-Scale Input Range: ±25 mv to ±10 V Input Offset Voltage: ( /G k) mv; where: G = PGA gain K = Sample rate per channel, KSPS e.g.: The maximum input offset voltage with a PGA gain of x10 and a sample rate of 0.5 KSPS per channel would be 1.2 mv ( ) Input Bias Current: 50 na maximum at zero input Input Impedance: 5 MΩ in parallel with 50 pf Input Noise: 0.3 mv RMS, DC to 100 Hz Input Filters: Optional low pass single-pole filters: -3 db at 10 Hz ±24% -3 db at 50 Hz ±24% -3 db at 100 Hz ±24% -3 db at 500 Hz ±24% -3 db at 1.6 khz ±24% Overvoltage Protection: Sustained Overvoltage Maximum Option Power On Power Off -000 ±16 V ±4 V -100 ±31 V ±23 V -200 ±21 V ±10 V -300 ±21 V ±10 V -400 ±21 V ±10 V -900 ±16 V ±4 V -001 ±24 V ±16 V -101 ±40 V ±33 V -201 ±24 V ±16 V -301 ±24 V ±16 V -401 ±24 V ±16 V -901 ±17 V ±5 V TRANSFER CHARACTERISTICS Resolution: 14 bit Input Sampling: Sequential, starting at channel 00 Integral Nonlinearity: ±0.005 percent maximum; from best straight line Differential Nonlinearity: ± percent; typical at MSB transition Quantization Error: ±1/2 LSB Missing Codes: None Conversion Cycle Time * : 17 µs, total time for acquisition, A/D conversion, and storage A/D Conversion Rate: 58 KSPS (thousand samples per second) Channel Sample Rate (Maximum): KSPS (58 KSPS number of channels in scanning block, 16 channels minimum) Timed Burst Interval: 305 µs to 536 s Interchannel Crosstalk: Filter Option Cross Talk Cross Talk (Maximum) (Maximum) (Adjacent (Alt. Channels) Channels) None -80 db -110 db 10 Hz -70 db -110 db 50 Hz -70 db -110 db 100 Hz -70 db -110 db 500 Hz -70 db -110 db 1.6 khz -77 db -110 db Common-Mode Voltage: CMV = ±9 V; maximum input voltage = ±11 V on either input line for linear operation. Common-Mode Rejection: CMRR = 82 db, DC to 100 Hz, 64-channel block size. Data Coding: Program selectable as two s complement, or straight/offset binary. 14-bit data is left-justified in a 16-bit data word. ACCURACY PGA Nonlinearity, DC: G=1: ±0.005 percent FSR (Full-Scale Range) G=10: ±0.005 percent FSR G=100: ±0.01 percent FSR * Each channel is sampled during the A/D conversion of the preceding channel. VMIC South Memorial Parkway Huntsville, Alabama

4 Gain Accuracy (Including Nonlinearity): G=1: ±0.008 percent FSR G=10: ±0.06 percent FSR G=100: ±0.06 percent FSR STABILITY (Over Temperature Range) PGA Offset Voltage Drift: ±(3 + 15/G) µv/ C System Accuracy Drift: G=1: ±20 PPM/ C G=10: ±50 PPM/ C G=100: ±90 PPM/ C Total Noise: 4,500 µv maximum at GAIN = 1 and FS = ±10 V DATA BUFFER MEMORY Buffer Size: 16 to 1,024 contiguous 16-bit data words, in six equal ratios of 2:1; program controlled. Block Size: 16, 32, 48, or 64 channels; program controlled. VMEbus Access: D8 or D16 Availability: Accessible at any time from the VMEbus. Buffer and block sizes are controlled through a Buffer Control Register (BCR). PHYSICAL/ENVIRONMENTAL Temperature: 0 to +55 C, operating (standard VME slot) -40 to +85 C, storage Humidity: 10 to 80 percent relative, noncondensing Altitude: Operation to 10,000 ft (3,048 m) Cooling: Forced air convection (standard VMEbus slot) Dimensions: Double height Eurocard (6U) board, 160 x mm Input Connectors (P3, P4): 96-pin DIN connector, center row grounded (accepts 64- and 96-pin mating connectors). Power Requirements: 4.0 A (maximum) at +5 VDC MTBF: 131,900 hours (217F) TRADEMARKS The VMIC logo is a registered trademark of VMIC. Other registered trademarks are the property of their respective owners. APPLICATION AND CONFIGURATION GUIDES The following Application and Configuration Guides are available from VMIC to assist the user in the selection, specification, and implementation of systems based on VMIC s products. Title Document No. Digital Input Board Application Guide Change-of-State Board Application Guide Digital I/O (with Built-in-Test) Product Line Description Synchro/Resolver (Built-in-Test) Subsystem Configuration Guide Analog I/O Products (with Built-in-Test) Configuration Guide Connector and I/O Cable Application Guide Integration of the VMIVME-5588 with GE Fanuc PLC Data Acquisition Noise Reduction Application Guide IOWorks Base Package Application Guide IOWorks Systems Application Guide For Ordering Information, Call: or FAX (256)

5 P3 P4 32 DIFF. 32 DIFF. LOW PASS FILTERS (OPTIONAL) LOW PASS FILTERS (OPTIONAL) (8) (8) 8 DIFF. 8 DIFF. (1) PROGRAMMABLE GAIN AMPLIFIER (PGA) 2 DIFF. (SE) HOLD TRACK-AND- HOLD AMPLIFIER CONV BOARD 14-bit 4 CONV COMPL 14 P1 SELECT DUAL-PORT GAIN REGISTERS 2 DUAL-PORT REGISTERS AND CONTROL VMEbus FOUNDATION LOGIC TIMING 4 CONTROL EXT CNVT TRIGGER 14 DATA P2 EOC INT COUNT COMPL BUS INTERRUPTER MODULE (BIM) PROGRAMMABLE TIMER Figure 1. Functional Block Diagram CMRR db Figure 2. Common-Mode Rejection Ratio Versus Frequency VMIC South Memorial Parkway Huntsville, Alabama Log (f)