Algorithms to Accelerate Multiple Regular Expressions Matching for Deep Packet Inspection
|
|
- Carmel Clark
- 5 years ago
- Views:
Transcription
1 Algorithms to Aelerate Multiple Regular Expressions Mathing for Deep Paket Inspetion Sailesh Kumar Washington University Computer Siene an Engineering St. Louis, MO Sarang Dharmapurikar Washington University Computer Siene an Engineering St. Louis, MO Fang Yu University of California, Berkeley Department of Computer Siene Berkeley, CA Patrik Crowley Washington University Computer Siene an Engineering St. Louis, MO Jonathan Turner Washington University Computer Siene an Engineering St. Louis, MO ABSTRACT There is a growing eman for network evies apale of examining the ontent of ata pakets in orer to improve network seurity an provie appliation-speifi servies. Most high performane systems that perform eep paket inspetion implement simple string mathing algorithms to math pakets against a large, ut finite set of strings. However, there is growing interest in the use of regular expression-ase pattern mathing, sine regular expressions offer superior expressive power an flexiility. Deterministi finite automata (DFA) representations are typially use to implement regular expressions. However, DFA representations of regular expression sets arising in network appliations require large amounts of memory, limiting their pratial appliation. In this paper, we introue a new representation for regular expressions, alle the Delaye Input DFA (D FA), whih sustantially reues spae requirements as ompare to a DFA. A D FA is onstrute y transforming a DFA via inrementally replaing several transitions of the automaton with a single efault transition. Our approah ramatially reues the numer of istint transitions etween states. For a olletion of regular expressions rawn from urrent ommerial an aaemi systems, a D FA representation reues transitions y more than 9%. Given the sustantially reue spae requirements, we esrie an effiient arhiteture that an perform eep paket inspetion at multi-gigait rates. Our arhiteture uses multiple on-hip memories in suh a way that eah remains uniformly oupie an aesse over a short uration, thus effetively istriuting the loa an enaling high throughput. Our Permission to make igital or har opies of all or part of this work for personal or lassroom use is grante without fee provie that opies are not mae or istriute for profit or ommerial avantage an that opies ear this notie an the full itation on the first page. To opy otherwise, or repulish, to post on servers or to reistriute to lists, requires prior speifi permission an/or a fee. SIGCOMM'06, Septemer -, 006, Pisa, Italy. Copyright 006 ACM /06/ $.00. arhiteture an provie ost-effetive paket ontent sanning at OC-9 rates with memory requirements that are onsistent with urrent ASIC tehnology. Categories an Sujet Desriptors C..0 [Computer Communiation Networks]: General Seurity an protetion (e.g., firewalls) General Terms Algorithms, Design, Seurity. Keywors DFA, regular expressions, eep paket inspetion.. INTRODUCTION Many ritial network servies hanle pakets ase on payloa ontent, in aition to the struture information foun in paket heaers. Forwaring pakets ase on ontent (either for the purpose of appliation-level loa-alaning in a we swith or seurity-oriente filtering ase on ontent signatures) requires new levels of support in networking equipment. Traitionally, this eep paket inspetion has een limite to omparing paket ontent to sets of strings. State-of-the-art systems, however, are replaing string sets with regular expressions, ue to their inrease expressiveness. Several ontent inspetion engines have reently migrate to regular expressions, inluing: Snort [], Bro [], Com s TippingPoint X0 [0], an various network seurity applianes from Ciso Systems []. Ciso, in fat, has integrate the regular expression ase ontent inspetion apailities into its Internetworking Operating System (IOS) []. Aitionally, layer 7 filters ase on regular expressions [0] are availale for the Linux operating system. While flexile an expressive, regular expressions have traitionally require sustantial amounts of memory, whih severely limits performane in the networking ontext. To see why, we must onsier how regular expressions are implemente. A regular expression is typially represente y a
2 eterministi finite automaton (DFA). For any regular expression, it is possile to onstrut a DFA with the minimum numer of states [, ]. The memory neee to represent a DFA is, in turn, etermine y the prout of the numer of states an the numer of transitions from eah state. For an ASCII alphaet, eah state will have 6 outgoing eges. Typial sets of regular expressions ontaining hunres of patterns for use in networking yiel DFAs with tens of thousans of states, resulting in storage requirements in the hunres of megaytes. Tale ompression tehniques are not effetive for these tales ue to the relatively high numer of unique next-states from a given state. Consequently, traitional approahes quikly eome infeasile as rule sets grow. In this paper, we introue a highly ompat DFA representation. Our approah reues the numer of transitions assoiate with eah state. The main oservation is that groups of states in a DFA often have iential outgoing transitions an we an use this upliate information to reue memory requirements. For example, suppose there are two states s an s that make transitions to the same set of states, {S}, for some set of input haraters, {C}. We an eliminate these transitions from one state, say s, y introuing a efault transition from s to s that is followe for all the haraters in {C}. Essentially, s now only maintains unique next states for those transitions not ommon to s an s an uses the efault transition to s for the ommon transitions. We refer to a DFA augmente with suh efault transitions as a Delaye Input DFA (D FA). In pratie, the proper an effetive onstrution of the efault transitions leas to a traeoff etween the size of the DFA representation an the memory anwith require to traverse it. In a stanar DFA, an input harater leas to a single transition etween states; in a D FA, an input harater an lea to multiple efault transitions efore it is onsume along a normal transition. Our approah ahieves a ompression ratio of more than 9% on typial sets of regular expressions use in networking appliations. Although eah input harater potentially requires multiple memory aesses, the high ompression ratio enales us to keep the ata struture in on-hip memory moules, where the inrease anwith an e provie effiiently. To explore the feasiility of this approah, we esrie a singlehip arhiteture that employs a moest of amount on-hip memory, organize in multiple inepenent moules. Moern VLSI tehnology easily enales this sort of integration of several emee memories on a single ie; for example, IBM s ASIC fariation tehnology [] an integrate up to 00 Mits of emee memory on one hip. We use multiple emee memories to provie ample anwith. However, in orer to eterministially exeute the ompresse automata at high rates, it is important that the memory moules are uniformly populate an aesse over short perios of time. To this en, we evelop loa alaning algorithms to map our automata to the memory moules in suh a way that eterministi worst-ase performane an e guarantee. Our algorithms an maintain throughput at 0 Gps while mathing thousans of regular expressions. To summarize, our ontriutions are a) the D FA representation of regular expressions whih signifiantly reues the amount of memory require, ) a single-hip arhiteture that uses the D FA representation, an ) a loa alaning algorithm whih ensures that on-hip resoures are uniformly use, therey enaling worst-ase performane guarantees. The remainer of the paper is organize as follows. Bakgroun on regular expressions an relate work are presente in Setion. Setion esries the D FA representation. Details of our onstrution algorithm an the ompression results are presente in Setion. Setion presents the system arhiteture, loa alaning algorithms an throughput results. The paper ens with onluing remarks in Setion 6.. BACKGROUND AND RELATED WORK Deep paket inspetion has reently gaine popularity as it provies the apaility to aurately lassify an ontrol traffi in terms of ontent, appliations, an iniviual susriers. Ciso an others toay see eep paket inspetion happening in the network an they argue that Deep paket inspetion will happen in the ASICs, an that ASICs nee to e moifie [9]. Some important appliations requiring eep paket inspetion are liste elow: Network intrusion etetion an prevention systems (NIDS/NIPS) generally san the paket heaer an payloa in orer to ientify a given set of signatures of well known seurity threats. Layer 7 swithes an firewalls provie ontent-ase filtering, loa-alaning, authentiation an monitoring. Appliationaware we swithes, for example, provie salale an transparent loa alaning in ata enters. Content-ase traffi management an routing an e use to ifferentiate traffi lasses ase on the type of ata in pakets. Deep paket inspetion often involves sanning every yte of the paket payloa an ientifying a set of mathing preefine patterns. Traitionally, rules have een represente as exat math strings onsisting of known patterns of interest. Naturally, ue to their wie aoption an importane, several high spee an effiient string mathing algorithms have een propose reently. Some of the stanar string mathing algorithms suh as Aho- Corasik [7] Commentz-Walter [8], an Wu-Maner [9], use a preproesse ata-struture to perform high-performane mathing. A large oy of researh literature has onentrate on enhaning these algorithms for use in networking. In [], Tuk et al. presents tehniques to enhane the worst-ase performane of Aho-Corasik algorithm. Their algorithm was guie y the analogy etween IP lookup an string mathing an applies itmap an path ompression to Aho-Corasik. Their sheme has een shown to reue the memory require for the string sets use in NIDS y up to a fator of 0 while improving performane y more than 0%. Many researhers have propose high-spee pattern mathing harware arhitetures. In [] Tan et al. propose an effiient algorithm that onverts an Aho-Corasik automaton into multiple inary state mahines, therey reuing the spae requirements. In [], the authors present an FPGA-ase esign whih uses harater pre-eoing ouple with CAM-ase pattern mathing. In [], Yusuf et al. use harware sharing at the it level to exploit logi esign optimizations, therey reuing the area y a further 0%. Other work [, 6, 7, 8, 9] presents several effiient string mathing arhitetures; their performane an spae effiieny are well summarize in []. In [], Sommer an Paxson note that regular expressions might prove to e funamentally more effiient an flexile as
3 ompare to exat-math strings when speifying attak signatures. The flexiility is ue to the high egree of expressiveness ahieve y using harater lasses, union, optional elements, an losures, while the effiieny is ue to the effetive shemes to perform pattern mathing. Open soure NIDS systems, suh as Snort an Bro, use regular expressions to speify rules. Regular expressions are also the language of hoie in several ommerial seurity prouts, suh as TippingPoint X0 [0] from Com an a family of seurity applianes from Ciso Systems []. Although some speialize engines suh as RegEx from Tarari [] report paket san rates up to Gps, the throughput of most suh evies remains limite to su-gigait rates. There is great interest in an inentive for enaling multigigait performane on regular expressions ase rules. Consequently, several researhers have reently propose speialize harware-ase arhitetures whih implement finite automata using fast on-hip logi. Sinhu et al. [] an Clark et al. [6] have implemente noneterministi finite automata (NFAs) on FPGA evies to perform regular expression mathing an were ale to ahieve very goo spae effiieny. Implementing regular expressions in ustom harware was first explore y Floy an Ullman [8], who showe that an NFA an e effiiently implemente using a programmale logi array. Mosola et al. [7] have use DFAs instea of NFAs an emonstrate signifiant improvement in throughput although their atasets were limite in terms of the numer of expressions. These approahes all exploit a high egree of parallelism y enoing automata in the parallel logi resoures availale in FPGA evies. Suh a esign hoie is guie partly y the aunane of logi ells on FPGA an partly y the esire to ahieve high throughput as suh levels of throughput might e iffiult to ahieve in systems that store automata in memory. While suh a hoie seems promising for FPGA evies, it might not e aeptale in systems where the expression sets nees to e upate frequently. More importantly for systems whih are alreay in eployment, it might prove iffiult to quikly resynthesize an upate the regular expressions iruitry. Therefore, regular expression engines whih use memory rather than logi, are often more esirale as they provie higher egree of flexiility an programmaility. Commerial ontent inspetion engines like Tarari s RegEx alreay emphasize the ease of programmaility provie y a ense multiproessor arhiteture ouple to a memory. Content inspetion engines from other venors [, ], also use memoryase arhitetures. In this ontext, Yu et al. [0] have propose an effiient algorithm to partition a large set of regular expressions into multiple groups, suh that overall spae neee y the automata is reue ramatially. They also propose arhitetures to implement the groupe regular expressions on oth general-purpose proessor an multi-ore proessor systems, an emonstrate an improvement in throughput of up to times. In this paper, we exten these memory-ase arhitetures an propose algorithms whih an enale the effiient implementation of regular expressions at multi-gigait rates while preserving the flexiility provie y programmaility.. DELAYED INPUT DFAS It is well-known that for any regular expression set, there exists a DFA with the minimum numer of states []. The memory neee to represent a DFA is etermine y the numer of transitions from one state to another, or equivalently, the numer of eges in the graph representation. For an ASCII alphaet, there an e up to 6 eges leaving eah state, making the spae requirements exessive. Tale ompression tehniques an e applie to reue the spae in situations when the numer of istint next-states from a given state is small. However, in DFAs that arise in network appliations, these methos are typially not very effetive eause on average, there are more than 0 istint next-states from various states of the automaton. We introue a moifiation to the stanar DFA that an e represente muh more ompatly. Our moifiations are ase on a tehnique use in the Aho-Corasik string mathing algorithm [7]. We exten their tehnique an apply it to DFAs otaine from regular expressions, rather than simple string sets.. Motivating Example We introue our approah using an example. The left sie of Figure shows a stanar DFA efine on the alphaet {a,,,} that reognizes the three patterns, p =a +, p = +, an p = * + (in these expressions, the asterisk represents 0 or more repetitions of the immeiately preeing su-expression, while the plus sign represents one or more repetitions). In this DFA, state is the initial state, an states, an are math states for the three patterns p, p an p, respetively. The right sie of Figure shows an alternate type of DFA, whih inlues unlaele eges that are referre to as efault transitions. When mathing an input string, a efault transition is use to etermine the next state, whenever the urrent state has no outgoing ege laele with the urrent input harater. When following a efault transition the urrent input harater is retaine. Consier the operation of the two automata on the input string aa. For this input, the sequene of states visite y the left-han automaton is, where the unerline states are the math states that etermine the output value for this input string. The right-han automaton visits states. Notie that the sequene of math states is the same, so if the seon output assoiates these states with the same three patterns, it proues the same output as the first one. Inee, it is not iffiult to show that the two automata visit the same sequene of math states for any input string. That is, they proue the same output, for all inputs an are hene equivalent. Note that the right-han automaton in Figure has just nine eges, while the one on the left has 0. We fin that for the more omplex DFAs that arise in network appliations, we an generally reue the numer of eges y more than 9%, ramatially reuing the spae neee to represent the DFA. There is a prie for this reution of ourse, sine no input is onsume when efault eges are followe. In the example in Figure, no state with an inoming efault transition also has an outgoing efault transition, meaning that for every two eges traverse, we are guarantee to onsume at least one input harater. Allowing states to have oth inoming an outgoing efault transitions leas a more ompat representation, at the ost of some reution in the worst-ase performane.. Prolem Statement We refer to an automaton with efault transitions as a Delaye Input DFA (D FA). We represent a D FA y a irete graph,
4 a a a a a a Figure. Example of automata whih reognize the expressions a +, +, an * + whose verties are alle states an whose eges are alle transitions. Transitions may e laele with symols from a finite alphaet Σ. Eah state may have at most one unlaele outgoing transition, alle its efault transition. One state is esignate as the initial state an for every state s, there is a (possily empty) set of mathing patterns, µ(s). For any input string x Σ, we efine the estination state, δ(x) to e the last state reahe y starting at the initial state an following transitions laele y the haraters of x, using efault transitions whenever there is no outgoing transition that mathes the next harater of x (so, for the D FA on the right sie of Figure, δ(a)= an δ(a)=). We generalize δ to aept an aritrary starting state as a seon argument; so for the D FA on the right sie of Figure, δ(a,) =. Consier two D FAs with estination state funtions δ an δ, an mathing pattern funtions µ an µ. We say that the two automata are equivalent if for all strings x, µ (δ (x))=µ (δ (x)). In general, given a DFA that reognizes some given set of regular expressions, our ojetive is to fin an equivalent D FA that is sustantially more memory-effiient. We an oun the worst-ase performane of a D FA in terms of the length of its longest efault path (that is, a path omprising only efault transitions). In partiular, if the longest efault path has k transitions, then for all input strings, the D FA will onsume at least one harater for every k transitions followe. To ensure that a D FA meets a throughput ojetive, we an plae a limit on the length of the longest efault path. This leas to a more refine version of the prolem statement, in whih we seek the smallest equivalent D FA that satisfies a speifie oun on efault path length.. Converting DFAs to D FAs Although, we are in general intereste in any equivalent D FA, for a given DFA, we have no general proeure for synthesizing a D FA iretly. Consequently, our proeure for onstruting a D FA proees y transforming an orinary DFA, y introuing efault transitions in a systemati way, while maintaining equivalene. Our proeure oes not hange the state set, or the set of mathing patterns for a given state. Hene, we an maintain equivalene y ensuring that the estination state funtion δ(x), oes not hange. Consier two states u an v, where oth u an v have a transition laele y the symol a to a ommon thir state w, an no efault transition. If we introue a efault transition from u to v, we an eliminate the a-transition from u without affeting the estination state funtion δ(x). A slightly more general version of this oservation is state elow. Lemma. Consier a D FA with istint states u an v, where u has a transition laele y the symol a, an no outgoing efault transition. If δ(a,u)=δ(a,v), then the D FA otaine y introuing a efault transition from u to v an removing the transition from u to δ(a,u) is equivalent to the original DFA. Note that y the same reasoning, if there are multiple symols a, for whih u has a laele outgoing ege an for whih δ(a,u)=δ(a,v), the introution of a efault ege from u to v allows us to eliminate all these eges. Our proeure for onverting a DFA to a smaller D FA applies this transformation repeately. Hene, the equivalene of the initial an final D FAs follows y inution. The D FA on the right sie of Figure was otaine from the DFA on the left, y applying this transformation to state pairs (,), (,), (,) an (,). For eah state, we an have only one efault transition, so it s important to hoose our efault transitions arefully to allow us to get the largest possile reution. We also restrit the hoie of efault transitions to ensure that there is no yle efine y efault transitions. With this restrition, the efault transitions efine a olletion of trees with the transitions irete towars the tree roots an we an ientify the set of transitions that gives the largest spae reution y solving a maximum weight spanning tree prolem in an unirete graph whih we refer to as the spae reution graph. The spae reution graph for a given DFA is a omplete, unirete graph, efine on the same vertex set as the DFA. The ege joining a pair of verties (states) u an v is assigne a weight w(u,v) that is one less than the numer of symols a for whih δ(a,u)=δ(a,v). The spae reution graph for the DFA on the left sie of Figure is shown in Figure. Notie that the spanning tree of the spae reution graph that orrespons to the efault transitions for the D FA in Figure has a total weight of +++=, whih is the ifferene in the numer of transitions in the two automata. Also, note that this is a maximum weight spanning tree for this graph. Figure shows D FAs orresponing
5 a a Figure. Spae reution graph for DFA in Figure. to two ifferent maximum weight spanning trees. Note that while these two automata use the same numer of eges as the one in Figure, they have efault paths of length an, respetively, meaning that their worst-ase performane will not e as goo.. BOUNDING DEFAULT PATHS If our only ojetive was minimizing the spae use y a D FA, it woul suffie to fin a maximum weight spanning tree in the spae reution graph. The tree eges orrespon to the state pairs etween whih we reate efault transitions. The only remaining issue is to etermine the orientation of the efault transitions. Sine eah vertex an have only one outgoing efault transition, it suffies to pik some aritrary state to e the root of the efault transition tree an iret all efault transitions towars this state. Unfortunately, when this proeure is applie to DFAs arising in typial network appliations, the resulting efault transition tree has many long paths, implying that the D FA may nee to make many transitions for eah input harater onsume. We an improve the performane somewhat, y seleting a tree root that is entrally loate within the spanning tree. However, this still leaves us with many long efault paths. The natural way to avoi long efault paths is to onstrut a maximum weight spanning tree with a speifie oune iameter. Unfortunately, the onstrution of suh spanning trees is NP-har [9]. It s also not lear that suh a spanning tree leas to the smallest D FA. What we atually require is a olletion of oune iameter trees of maximum weight. While this prolem an e solve in polynomial time if the iameter oun is (this is simply maximum weight mathing), the prolem remains NP-har for larger iameters. Fortunately, we have foun that fairly simple methos, ase on lassial maximum spanning tree algorithms, yiel goo results for D FA onstrution. One oneptually straight-forwar metho uils a olletion of trees inrementally. The metho (whih is ase on Kruskal s algorithm [6]) examines the eges in ereasing orer of their weight. An ege {u,v} is selete as a tree-ege so long as u an v o not alreay elong to the same tree, an so long as the aition of the ege will not reate a tree whose iameter exees a speifie oun. One all the eges have een onsiere, the tree eges efine efault transitions. We orient the efault transitions in eah tree y ireting them towars a selete root for that tree, where the roots are selete so as to minimize the istane to the root from any leaf. The one ompliation with this metho is heking the iameter ouns. We an o this effiiently y maintaining for eah vertex u a value (u) whih speifies the numer of eges in the longest Figure. D FAs orresponing to two ifferent maximum weight spanning trees tree path from u to a vertex in the same tree. These values an e use to hek that the aition of a new ege will not violate the iameter oun. When a new tree ege is ae, the istane values must e upate for verties in the tree forme y the aition of the new ege. This an e one in linear time for eah upate. Consequently, the total time neee to maintain the istane values is O(n ). Sine Kruskal s algorithm, on whih our algorithm is ase, requires O(n log n) time on omplete graphs, the iameter heking oes not inrease the asymptoti running time of the algorithm. One refinement to this fairly simple algorithm is shown elow. While examining the eges in ereasing orer of their weights, we also look for an ege among all equal weight eges, whih results in the minimum expansion in the iameter of the trees joine. In pratie, sine there are only ifferent weight values, at any point in time, there will often e plenty of equal weight eges to hoose from. The resulting refine algorithm egins with the weighte unirete spae reution graph G=(V,W) an moifies an ege set efault whih form the efault transition trees. First it onsiers all eges of weight, an inrementally onstruts efault trees of small iameters. Then it repeately onsiers smaller weight eges an as them to the efault transition trees. It turns out that the refinement generally leas to efault transition trees with signifiantly smaller iameter as ompare to a normal proeure refinemaxspantree (graph G=(V, W), moifies set ege efault); () vertex u, v; set eges; set weight-set[]; () efault := {}; eges := W; () for ege (u, v) eges () if weight(u, v) > 0 () a (u, v) to weight-set[weight(u, v)]; (6) fi (7) for integer i = to (8) o weight-set[i] [ ] (9) Selet (u, v) from weight-set[i] whih leas to the (0) smallest growth in the iameter of the efault tree () if verties u an v elongs to ifferent efault trees () if efault U (u, v) maintains the iameter oun () efault := efault U (u, v); () fi () fi (6) o (7) rof en;
6 Figure. Default transition trees forme y the spanning tree algorithm an y our refine version spanning tree, whih remains olivious aout the iameter uilup of the trees until the iameter oun is reahe. In a setup, where the iameter oun is not applie, refine spanning tree algorithm reates efault transition trees of equal weight ut relatively smaller iameter. When iameter oun is applie, the refine algorithm reates trees with higher weight too. This happens, eause a normal spanning tree, in its proess, quikly reates several trees whose iameter is too large an hene an not e further linke to any tree. The refine version ensures that tree iameter remains small; hene more trees an e linke, resulting in higher weight. In orer to illustrate the effet of this refinement, we take a syntheti DFA, whih onsists of states. All pairs of states u an v were assigne transitions on a ranom numer (rawn from a geometri istriution with suess proaility, π = 0.0, thus mean, E(X) = 9) of symols a suh that δ(a,u)=δ(a,v). Thus the weight of the eges in the spae reution graph was geometrially istriute. When we ran the normal an refine versions of spanning tree algorithms without any iameter oun, they reate spanning trees of weight 77, as shown in Figure. While the weights of oth trees are maximum, their iameters are an 0 respetively. If we hoose noes 8 an 9, respetively, as the root of these two trees, the longest efault paths will ontain 7 an eges, while the average length of efault paths will e.8 an.8, respetively. Clearly, the refinement in the spanning tree algorithm reues the memory aesses neee y a D FA for every harater. We will see in setion. that when iameter ouns are applie, refine spanning tree reates even smaller D FAs as ompare to the normal spanning tree. When we oune the iameter of the spanning tree to 7, an ran our algorithm on the same syntheti DFA, it reate three efault Figure. Default transition trees (forest) forme y the refine spanning tree with the tree iameter oune to 7 7 transition trees, as shown in Figure. The total weight of all three trees was 6, whih suggests that the resulting DF A will require slightly more spae as ompare to the one with no iameter restraint. However, ouning the iameter to 7 ensures an important property that the length of all efault paths an e easily limite to an hene the D FA will require at most memory aesses per harater.. Results on some regular expression sets In orer to evaluate the spae reutions ahieve y a elaye input DFA, or D FA, we performe experiments on regular expression sets use in a wie variety of networking appliations. Our most important ataset are the regular expression sets use in eep paket inspetion applianes from Ciso Systems [8]. This set ontains more than 70 moerately omplex expressions, whih are use to etet the anomalies in the traffi. It is wiely use aross several Ciso seurity applianes an Ciso ommonly employs general purpose proessors with a gigayte or more memory to implement them. In aition to this set, we also onsiere the regular expressions use in the open soure Snort an Bro NIDS, an in the Linux layer-7 appliation protool lassifier. Linux layer-7 protool lassifier onsists of 70 expressions. Snort ontains more than a thousan an half expressions, although, they on t nee to e mathe simultaneously. An effetive way to implement the Snort rules is to ientify the expressions for eah heaer rule an then group the expressions orresponing to the overlapping rules (the set of heaer rules a single paket an math to). We use this approah. For the Bro NIDS, we present results for the HTTP signatures, whih onsist of 68 regular expressions. Given these regular expression sets, as the first step to onstrut DFAs with a small numer of states, we use the set splitting tehniques propose y Yu et al. in [0]. It splits the regular expressions into multiple sets so that eah set reates a small DFA. We reate 0 sets of rules from the Ciso regular expressions, an were ale to reue the total memory footprint to 9 MB, as there were a total of 808 states, an eah iniviual DFA ha less than 6K states, (thus ytes enoes a state). Clearly, suh effiient grouping resulte in signifiant spae reution over more than a gigayte spae require otherwise. We split the Linux layer-7 expressions into three sets, suh that the total numer of states was For the Snort set, we present results for the heaer rule tp $EXTERNAL_NET any -> $HTTP_SERVERS $HTTP_PORTS, whih onsists of omplex
7 Soure Tale. Our representative regular expression groups # of regular expressio ns Avg. ASCII length of expressions % expressions using wilars (*, +,?) % expressions length restritions {,k,+} Ciso Ciso Ciso Linux Linux Snort Snort Bro expressions. Sine Snort rules were omplex, with long length restrition on various harater lasses, we applie rewriting tehniques propose in [0] to some rules an split them further into four sets. Bro regular expressions were generally simple an effiient therefore we were ale to ompile all of them in a single automaton. The key properties of our representative regular expression groups are summarize in Tale. In orer to estimate the reution ojetives of D FA, we introue a term upliate transition. Transitions are upliate if there exists more than one of them leaing to the same next state for the same input harater. For example in Figure, if the transitions on input from states is terme original then the ones from state,, an are upliates. Even though, it may not e possile to eliminate all upliate transitions, it still gives a goo estimate on the upper oun of the numer of transitions that an e eliminate y onstruting a D FA from the DFA. After onstruting the minimum state DFAs from these regular expressions, we use oth normal an refine versions of spanning tree to onstrut the orresponing D FAs. The reution in the numer of transitions is shown in Tale with no iameter ouns applie. The length of efault paths, whih gives an estimate of the ae memory anwith a D FA will nee over a DFA, are also shown. It is lear that, D FAs eliminates nearly all upliate transitions from the DFAs. It is also apparent that refine version of spanning tree reates sustantially smaller efault paths as ompare to a normal spanning tree. In orer to get a sense of the istriution of the numer of laele transitions Numer of states Numer of transitions at a state Figure 6. Distriution of numer of transitions per state in the D FA onstrute from the Ciso90 expression set per states of a D FA, we plot it in Figure 6, for the Ciso regular expression group ontaining 90 expressions. Majority of states has or fewer laele transitions. Note that most states have transitions eause most rules are ase insensitive, like [-ed-e0-9\-_][/\\][^/\\\r\n?\x6\s\t:]*[.][nn][uu]. Sine the aove results are with no iameter restritions, efault transition paths are quite long. In orer to ahieve smaller efault paths, we ran our algorithm with the iameter restrite to a small onstant. In this ase, we first ompare the reutions ahieve y normal spanning tree an y our refine version. In Tale, we report the numer of transitions in the resulting D FA, with the length of efault paths oune to eges. Clearly, refine version of spanning tree yiels relatively more ompat D FA. In Figure 7, we plot the reution in the numer of transitions of a Tale. Numer of transitions in D FA with efault path length oune to DFA Normal spanning tree Refine spanning tree Ciso Ciso Ciso Linux Linux0 9 0 Snort Bro Tale. Original DFA an the D FA onstrute using the normal an the refine spanning tree, without any iameter oun Original DFA Delaye input DFA, D FA Normal spanning tree Refine spanning tree DFA Total # of Total # of Total # of Total # of % Total # of % Avg. Max. Total # of % Avg. Max. states transitions istint upliate upli transitions reuti efault efault transitions reuti efault efault transitions transitions ates on length length on length length Ciso Ciso Ciso Linux Linux Snort Bro
8 # transitions (as fration of the # of istint transitions in original DFA) Ciso90 Ciso0 Ciso7 Linux6 Linux0 Snort Bro Maximum efault path length Average efault path length Ciso90 Ciso0 Ciso7 Linux6 Linux0 Snort Bro Maximum efault path length Figure 7. Plotting total numer of laele transitions in D FAs for various maximum efault path length ouns DFA, as ratio of numer transitions in the D FA an numer of istint transitions (transitions leaing to istint next states ) in the original DFA, y applying the refine version of spanning tree an ouning the efault paths at ifferent values. It is ovious that smaller efault path restritions proue D FAs with relatively higher numer of laele transitions. Note that, the reution numers plotte are with respet to the total numer of istint transitions (leaing to ifferent next states ) at various states in the original DFA, an not all transitions. Clearly this metri is onservative an suggests the spae reution y D FA over a DFA using the est (possily hypothetial) tale ompression sheme whih enales it to store only the istint transitions. If we woul use the total transitions in a DFA as our metri, D FA will result in even higher reution. Figure 8 plots the average length of efault paths in these experiments. It is apparent that, the average length of efault paths (whih etermines the average performane) remains almost two times smaller than the longest ones.. Summarizing the results The results suggest that a elaye input DFA or D FA an sustantially reue the spae requirements of the regular expression sets ommonly use in many networking appliations. For example, using D FA, we were ale to reue the spae requirements of regular expressions use in eep paket inspetion applianes of Ciso Systems to less than MB. We also saw signifiant reution in the Bro an Linux layer-7 expressions. Snort expressions resulte in moerate improvements (aoring to our onservative metri) as there were fewer istint transitions per state. D FA reues the spae requirements at the ost of multiple memory aesses per harater. In fat, splitting an expression set into multiple groups as to the numer of memory aesses as it reates multiple D FAs, all of whih nees to e exeute in Memory Memory Memory... Memory D FA sanner D FA sanner D FA sanner Figure 9. Logial struture of the memory susystem... Figure 8. Plotting the average efault path length in D FAs for various maximum efault path length ouns parallel. Although, D FA performs equally well on expression sets whih are not split, we eie to split, in orer to reue the total numer of states in the DFA to egin with (e.g. 9 MB for 9 partitions of the Ciso rules versus + GB without lever rule partitioning). Suh a esign hoie makes sense in our ontext, eause we use multiple emee memories, whih provies us with ample anwith, ut limite apaity. We now present our arhiteture an algorithms to map the D FAs onto them.. REGEX SYSTEM ARCHITECTURE In this setion, we propose an effiient regular expression engine onsisting of multiple emee memories an proessors. We also propose algorithms to effiiently map the D FA onto the arhiteture. One of our esign ojetives is flexiility, so we preominantly use emee memories in orer to store the automata rather than synthesizing them in logi gates [8]. Using memory rather than logi allows the arhiteture to remain flexile in the fae of frequently upating regular expressions. In aition to ense ASIC emee memory tehnologies like IBM s [], moern FPGAs suh as the Xilinx Virtex- ontain several hunres of 8Kit memory loks [] proviing several megaytes in aggregate. The emee memories in FPGAs have multiple ports an lok rates of up to 00 MHz. Of ourse, ASIC tehnologies provie higher egree of flexiility, with the numer of ports, the size of eah memory, an the lok rate all eing esign speifi. Thus, a memory-ase esign is eminently pratial. Given this, we esign our emee memory arhiteture with the following points in min. While small memories often lok at higher rates, every aitional memory as to the overhea of the ontrol iruitry. Therefore, we inten to use an aequate numer of reasonaly size memories, so that the overall anwith remains appropriate while maintaining reasonale ontrol omplexity. Using multiple, equally-size emee memories will enale the arhiteture to sale apaity an anwith linearly with inreasing on-hip transistor ensity. A ie with several equally size memories an ahieve effiient plaement an routing, resulting in minimal waste ie area. Therefore, our esign will use memories of equal size, inepenent of the harateristis of any partiular ata set. In
9 Throughput (Gps) memory moules average performane 8 memory moules memory moules Synthetially generate worst-ase input ata memory moule 6 memory moules Numer of onurrently sanne pakets Figure 0. Throughput with efault path length oune to 7 an using the ranomize mapping fat, using several small equally size memories is a natural hoie given that the kin of expressions an the resulting automata are likely to hange very often. The resulting arhiteture onsists of a symmetri tile of equally size emee memories; the logial organization of this system is shown in Figure 9. Note that FPGAs, with hunres of fix-size memory moules, fall within the sope of this arhiteture. As an e seen, there are multiple memories, eah aessile y an array of regular expression engines. Eah engine is apale of sanning one paket at a time. Multiple engines are present to exploit the paket- an flow-level parallelism availale in most paket proessing ontexts. While throughput for an iniviual paket will e limite to that of a single memory, overall system throughput an approah the aggregate memory anwith. To o so, we must map the D FA to these memories in suh a way that, a) there is minimal fragmentation of the memory spae, so that every memory remains uniformly oupie; an ) eah memory reeives a nearly equal numer of aesses, so that none of them eomes a throughput ottlenek. We now propose algorithms to ahieve these ojetives.. Ranomize Mapping A simple uniformly ranom mapping of states to memory moules an provie salale average-ase performane. The expetation is that over a long perio of time, eah memory will reeive a nearly equal fration of all referenes. Thus, with a reasonale numer of onurrent pakets, average throughput an remain high. Consier a ase of m memory moules an p onurrently sanne pakets. If eah paket generates a rea request at an interval of l yles (i.e, the memory rea lateny), we nee to san m l pakets onurrently in orer to keep the m memories usy. In pratie, we nee more pakets ue to ranom onflits. The prolem an e moele as a alls an ins prolem. There are m ins (memory moules) an alls (memory requests) arrive to them ranomly. Only one an e servie at eah in per yle, so any remaining alls must wait for susequent memory yles. If m alls arrive ranomly, -e - will serve an rest has to wait for next yle. Thus only 6% of the memories will e usy. As more alls arrive, more memories will remain usy. Thus, sanning many pakets onurrently improves the overall throughput, while iniviual pakets are serve relatively slowly. We report the throughput of suh a ranomize arhiteture in Figure 0, assuming a ual-port emee memory running at 00 MHz an a rea aess lateny of yles. In this experiment, we have limite the longest efault paths in the D FA to 7. The input ata was generate from the MIT DARPA Intrusion Detetion Data Sets []. We inserte aitional ata into these sets so that the automaton will etet approximately % mathes. It is evient from the plots that as we inrease the numer of onurrently sanne pakets, the overall throughput sales up. Moreover, as the numer of emee memories inreases, the throughput sales almost linearly up to 8 memories, eyon whih there is little improvement. This saturation is ue to signifiant spatial loality in the automata traversal in whih some states are visite more often than the others. In fat, in some ases, we foun that a single state is visite almost 0% of the time. If suh a state resies in memory moule k, it is likely that memory moule k will limit the overall performane irrespetive of the numer of moules. However, suh situations are rare, an the average performane remains exellent. A ranomize system is also likely to have a very low worst-ase throughput as shown in Figure 0. This an e explaine as follows. A D FA often nees to traverse multiple efault transitions for a harater; if the maximum efault path length is limite to 7, then 8 state traversals might e neee for a harater. Sine the state to memory mapping is ranom, there may exist efault paths along whih all states resie in the same memory moule (or in a small numer of moules). If the input ata is suh that the automaton repeately traverses suh efault paths, then throughput will egrae. Moreover, when we map multiple automata (one for eah regular expression group) onto memory moules ranomly, efault paths of ifferent automata may map to the same memory moule. In this ase, pakets traversing those paths will e effetively proesse serially, an overall system throughput oul iminish even further. Sine this ranomize approah is sujet to these pathologial worst-ase onitions, we now propose eterministi mapping algorithms apale of maintaining worst-ase guarantees.. Deterministi an Roust Mapping The first goal of a roust an eterministi mapping is to ensure that all automata, whih are exeute simultaneously, are store in ifferent memory moules. This will ensure that eah exeutes in parallel without any memory onflits. Ahieving this goal is straight-forwar, provie that there are more memory moules than automata. The seon goal is to ensure that all states along any efault path map to ifferent memory moules. Thus, no pathologial onition an arise for long efault paths as a memory moule will e referre at most one. Another enefit of this approah is that we will nee fewer onurrent pakets to ahieve a given level of throughput, ue to the etter utilization of. Prolem Formulation: We an formulate the aove prolem as a graph oloring prolem, where olors represent memory moules an efault paths of D FA represent the graph. As we have seen, these paths form a forest, where verties represent states an irete eges represent efault transitions. Our goal is to olor the verties of the forest so that all verties along any path from a leaf to the root are olore with ifferent olors. Moreover, we
10 nee to ensure that every olor is nearly equally use, so that memories remains uniformly oupie. Clearly, if is the longest efault path, i.e. the epth of the eepest tree, then we nee at least + olors. We present two heuristi algorithms, to olor the trees in the forest... Deterministi an Roust Mapping The max-min algorithm is similar to the first-fit, ereasing inpaking heuristi [7], one of the est known heuristis for solving the NP-omplete in paking prolem. The algorithm is formally esrie aove, where the irete graph D represents the efault transitions an C the set of all olors. The algorithm proees y orering the efault transition trees aoring to their size (i.e., the numer of verties times the size of eah vertex). Then, in ereasing orer of size, it olors eah tree suh that all verties at ifferent epths are olore with one of the + olors. Sine there are a total of + olors an the maximum epth of a tree is, verties along all efault paths are guarantee to get ifferent olors. In orer to ensure that olors are nearly equally use, max-min heuristis are use. For a urrently selete tree, it groups the verties at ifferent epths an sorts the group with respet to the size of all verties in the group. Then, it assigns the most use olor to the smallest group an the least use olor to the largest group. When the forest onsists of a large numer of trees, max-min oloring ensures that olors are nearly equally use; therey ensuring that ifferent memory moules will remain uniformly oupie. However, when there are a small numer of trees, the max-min algorithm often leas to uneven memory usage. A simple example is shown on the left han sie of Figure, where there are two trees whih are olore with olors. With the maxmin algorithm, olor is use to olor 7 verties, while olors, an are eah use to olor only verties. An alternative oloring, whih uses eah olor uniformly an also ensures that verties along a efault path uses ifferent olors, is shown on the right han sie in the same figure. We now propose an algorithm whih proues suh oloring... Aaptive oloring algorithm The max-min algorithm performs poorly eause it oes not exploit situations when multiple olors are availale to olor a vertex. For instane, in the example shown in figure, the maxmin algorithm assigne olor to all verties at epth, although five of these six verties an e olore with either olor or. In pratie, a D FA reates efault trees with many suh opportunities. This aaptive algorithm exploits this power of multiple hoies an results in a more uniform olor usage. A natural way to onstrut a D FA is to limit the efault path length to the numer of memory moules (olors) availale to it Figure. Left iagram shows two trees olore y max-min algorithm. Right iagram shows a etter oloring proeure max-min-oloring (graph D(V, W), set olor C); () heap h,, l; () for tree t D () for vertex u t size(t) := size(t) + size(u); rof () h.insert(t, size(t)); () rof (6) for olor j C.insert(j, 0); rof (7) o h [ ] (8) t := h.finmax(); h.remove(t); (9) for all epth values i t (0) l.insert(i, size of all verties at epth i); () rof () olor j :=.finmax(); () o l [ ] () epth i := l.finmin(); size s := l.key(i); l.remove(); () Color verties at epth i in tree t with olor j; (6).hangekey(j,.key(j) + s); (7) j :=.finnextmax(); (8) o (9) o en; proeure aaptive-oloring (graph D(V, W), set olor C); () heap h; () for olor C use[] := 0; eprive[] := 0; rof () for vertex u V () set olor olors[u] := C; () h.insert(u, epth(u)); (6) rof (7) o h [ ] (8) u := h.finmax(); h.remove(u); (9) if olors[u] > assign-olor(u, D, C); fi (0) o en; proeure assign-olor (vertex u, graph D(V, W), set olor C); () olor ; () Pik from olors[u] with min use[] an max eprive[]; () olors[u] := ; () use[] := use[] + size(u); () for v esenents(u) olors[v] := olors[v] ; rof (6) for v anestors(u) olors[v] := olors[v] ; rof (7) alulate-eprive(d, C); (8) if ef-trans(u) NULL assign-olor(ef-trans(u), D, C); fi en; proeure alulate-eprive (graph D(V, W), set olor C); () for olor C eprive[] := 0; rof () for vertex u V () if olors[u] = () olor := olors[u]; () for v esenents(u) (6) if olors[v] > eprive[] += size(v); fi (7) rof (8) fi (9) rof en;
11 {,,,} {,,,} {} {,,,} {} {} {,,,} {,,,} {,,,} {,,,} {} {,,} {,,,} {,,,} {} {,,} {,,} {} {,,,} {,,,} {} {,,,} {} {} {,,,} {,,,} {,,,} {,,,} {,,,} {,} {,} {,,} {,,} {,,} {,} {,} {,,} {,,} {,,} {,,,} {} {} {} {} use[] = 0 eprive[] = 0 use[] = 0 eprive[] = 0 use[] = 0 eprive[] = 0 use[] = 0 eprive[] = 0 {,,,} {,,,} use[] = eprive[] = 0 use[] = eprive[] = 0 use[] = eprive[] = use[] = eprive[] = 6 {,,,} {,,,} use[] = eprive[] = 0 use[] = eprive[] = use[] = eprive[] = use[] = eprive[] = 6 Colore impliitly as its olor set is left with a single olor {} {} {} {} {} {} {} {,,} {,,} {} {} {} {,,} {} {} {} {} {} {} {} {} {} {,,} {,,} {,,} use[] = eprive[] = 0 use[] = eprive[] = use[] = eprive[] = 0 use[] = eprive[] = {} {} {} {} {} {} {} {} {,} {,} use[] = eprive[] = 0 use[] = eprive[] = use[] = eprive[] = 0 use[] = eprive[] = {} {} {} {} {} {} {} {} {} {} use[] = eprive[] = 0 use[] = eprive[] = 0 use[] = eprive[] = 0 use[] = eprive[] = 0 {} {} {} Figure. Various steps involve in the oloring of two trees with aaptive algorithm (assuming equally size verties) Max isrepany in olor usage Numer of efault transition trees in the forest Figure. Plotting maximum isrepany in olor usage, irles for max-min an squares for aaptive algorithm It egins y assigning a set of all C olors to all verties an then removes olors from eah set until every vertex is fully olore (i.e. a single olor left in their set). In orer to remove appropriate olors, it keeps trak of two variales for every olor. The first variale use traks the total numer of verties olore y eah olor, an the seon variale eprive traks the future hoies of olors that remain in the sets of those verties not yet fully olore. More speifially, for every olor, eprive maintains the numer of the verties, whih are eprive of using it, as it has een remove from their olor set an use maintains the numer of verties olore with it. Clearly, the goal is to more often use olors a) whih most of the verties are eprive of an ) with whih fewest verties are fully olore with. After initializing the olor sets of eah vertex, the next step is to eie an orering of the verties, in whih olors will e remove from their olor set. An effetive orering is to first hoose verties whih o not have a high egree of freeom in hoosing olors. Sine verties along longer efault paths have fewer hoies (e.g. verties along x eep efault paths an pik one of x+ olors), they shoul e olore first. Therefore, aaptive algorithm proesses verties of all trees simultaneously, in a ereasing orer of the epth values. It hooses a vertex, an removes all ut one olor from its olor set, thus effetively oloring it. Whenever a vertex u is olore with olor, olor is remove from the olor set of all anestors an esenents of u, sine it an t e use to olor any of them. Then, all anestor verties of u are reursively olore. The algorithm is formally presente aove. A set olors is kept for every vertex an initially it ontains all C olors. One all ut one olor is remove from this set, the vertex gets olore. The steps involve in the oloring of two trees y the aaptive algorithm using four olors are illustrate in Figure... Coloring results In orer to evaluate, how uniformly the min-max an aaptive algorithms utilize various olors, we generate D FA suh that they have ifferent numers of efault transition trees in the orresponing forest. This was ahieve y limiting the efault path length to ifferent values. We also limite ourselves to use only + olors (where is the longest efault path), as allowing the use of more olors makes the oloring far easier. Our prinipal metri of oloring effiieny is the maximum isrepany in olor usage. If use(i) is the size (numer of verties times the numer of transitions it has) of all verties using the i-th olor, then the maximum olor usage isrepany will e, ( max use ( i) min use( i)) max use( i) i i Clearly, smaller values of isrepany reflet more uniform usage of various olors. We plot the maximum isrepany in olor usage in Figure, for ifferent numer of efault transition trees in the forest. It is apparent that aaptive algorithm uses olors more uniformly. Using the aaptive oloring algorithm, one we limite the efault paths to 7 or less, we were ale to map all of our D FA to memory moules suh that there was a maximum isrepany of less than 7 ytes in the memory oupany. i
Advanced Algorithms for Fast and Scalable Deep Packet Inspection
Avane Algorithms for Fast an Salale Deep Paket Inspetion Sailesh Kumar Washington University sailesh@arl.wustl.eu Jonathan Turner Washington University jon.turner@wustl.eu John Williams Ciso Systems jwill@iso.om
More information1 Disjoint-set data structure.
CS 124 Setion #4 Union-Fin, Greey Algorithms 2/20/17 1 Disjoint-set ata struture. 1.1 Operations Disjoint-set ata struture enale us to effiiently perform operations suh as plaing elements into sets, querying
More informationKeeping Things Simple: Finding Frequent Item Sets by Recursive Elimination
Keeping Things Simple: Fining Frequent Item Sets y Reursive Elimination Christian Borgelt Department of Knowlege Proessing an Language Engineering Shool of Computer Siene, Otto-von-Guerike-University of
More informationHEXA: Compact Data Structures for Faster Packet Processing
Washington University in St. Louis Washington University Open Sholarship All Computer Siene and Engineering Researh Computer Siene and Engineering Report Number: 27-26 27 HEXA: Compat Data Strutures for
More informationSolutions to Tutorial 2 (Week 9)
The University of Syney Shool of Mathematis an Statistis Solutions to Tutorial (Week 9) MATH09/99: Disrete Mathematis an Graph Theory Semester, 0. Determine whether eah of the following sequenes is the
More informationPartial Character Decoding for Improved Regular Expression Matching in FPGAs
Partial Charater Deoding for Improved Regular Expression Mathing in FPGAs Peter Sutton Shool of Information Tehnology and Eletrial Engineering The University of Queensland Brisbane, Queensland, 4072, Australia
More informationLAB 4: Operations on binary images Histograms and color tables
LAB 4: Operations on binary images Histograms an olor tables Computer Vision Laboratory Linköping University, Sween Preparations an start of the lab system You will fin a ouple of home exerises (marke
More informationThis fact makes it difficult to evaluate the cost function to be minimized
RSOURC LLOCTION N SSINMNT In the resoure alloation step the amount of resoures required to exeute the different types of proesses is determined. We will refer to the time interval during whih a proess
More informationSmartCuckoo: A Fast and Cost-Efficient Hashing Index Scheme for Cloud Storage Systems
SmartCukoo: A Fast an Cost-Effiient Hashing Inex Sheme for Clou Storage Systems Yuanyuan Sun an Yu Hua, Huazhong University of Siene an Tehnology; Song Jiang, University of Texas, Arlington; Qiuyu Li,
More informationUnsupervised Segmentation of Stereoscopic Video Objects: Proposal. and Comparison of Two Depth-Based Approaches
Unsupervise Segmentation of Stereosopi Vieo Objets: Proposal an Comparison of Two Depth-Base Approahes Klimis S. Ntalianis an Athanasios S.Drigas Net Meia Lab, NCSR Demokritos, Athens, Greee E-mail: kntal@image.ntua.gr
More informationInverse Design of Urban Procedural Models
Inverse Design of Uran Proeural Moels Carlos A. Vanegas Purue University U.C. Berkeley Ignaio Garia-Dorao Purue University Daniel G. Aliaga Purue University Development site Paul Waell U.C. Berkeley Non-optimize
More informationPath Sharing and Predicate Evaluation for High-Performance XML Filtering*
Path Sharing and Prediate Evaluation for High-Performane XML Filtering Yanlei Diao, Mihael J. Franklin, Hao Zhang, Peter Fisher EECS, University of California, Berkeley {diaoyl, franklin, nhz, fisherp}@s.erkeley.edu
More informationRegister Allocation III. Interference Graph Allocators. Computing the Interference Graph (in MiniJava compiler)
Register Alloation III Announements Reommen have interferene graph onstrution working by Monay Last leture Register alloation aross funtion alls Toay Register alloation options Interferene Graph Alloators
More informationRegister Allocation III. Interference Graph Allocators. Coalescing. Granularity of Allocation (Renumber step in Briggs) Chaitin
Register Alloation III Last time Register alloation aross funtion alls Toay Register alloation options Interferene Graph Alloators Chaitin Briggs CS553 Leture Register Alloation III 1 CS553 Leture Register
More informationExtracting Partition Statistics from Semistructured Data
Extrating Partition Statistis from Semistrutured Data John N. Wilson Rihard Gourlay Robert Japp Mathias Neumüller Department of Computer and Information Sienes University of Strathlyde, Glasgow, UK {jnw,rsg,rpj,mathias}@is.strath.a.uk
More informationComparing Fisheye and Full-Zoom Techniques for Navigation of Hierarchically Clustered Networks
Comparing Fisheye an Full-Zoom Tehniques for Navigation of Hierarhially Clustere Networks Doug Shaffer*, Zhengping Zuo, Lyn Bartram, John Dill, Shelli Dus, Saul Greenerg*, Mark Roseman* 1 * Dept of Computer
More informationEfficient and scalable trie-based algorithms for computing set containment relations
Effiient and salale trie-ased algorithms for omputing set ontainment relations Yongming Luo #1, George H. L. Flether #2, Jan Hidders 3, Paul De Bra #4 # Eindhoven University of Tehnology, The Netherlands
More informationPipelined Multipliers for Reconfigurable Hardware
Pipelined Multipliers for Reonfigurable Hardware Mithell J. Myjak and José G. Delgado-Frias Shool of Eletrial Engineering and Computer Siene, Washington State University Pullman, WA 99164-2752 USA {mmyjak,
More informationFigure 1. LBP in the field of texture analysis operators.
L MEHODOLOGY he loal inary pattern (L) texture analysis operator is defined as a gray-sale invariant texture measure, derived from a general definition of texture in a loal neighorhood. he urrent form
More informationOptimization of Image Processing in Video-based Traffic Monitoring
http://x.oi.org/0.5755/j0.eee.8.8.634 Optimization of Image Proessing in Vieo-base Traffi Monitoring Fei Zhu, Jiamin Ning, Yong Ren, Jingyu Peng Shool of Computer Siene an Tehnology, Soohow University,
More informationIncremental Mining of Partial Periodic Patterns in Time-series Databases
CERIAS Teh Report 2000-03 Inremental Mining of Partial Periodi Patterns in Time-series Dataases Mohamed G. Elfeky Center for Eduation and Researh in Information Assurane and Seurity Purdue University,
More informationGeneralized Buffering of PTL Logic Stages using Boolean Division and Don t Cares
Generalize Buffering of PTL Logi Stages using Boolean Division an Don t Cares Rajesh Garg Sunil P Khatri Department of ECE, Texas A&M University, College Station, TX 77843 Abstrat Pass Transistor Logi
More informationXML Data Streams. XML Stream Processing. XML Stream Processing. Yanlei Diao. University of Massachusetts Amherst
XML Stream Proessing Yanlei Diao University of Massahusetts Amherst XML Data Streams XML is the wire format for data exhanged online. Purhase orders http://www.oasis-open.org/ommittees/t_home.php?wg_abbrev=ubl
More informationThe Thresholding MLEM Algorithm
Journal of Meial an Biologial Engineering, 24(2: 85-9 85 The Thresholing MLEM Algorithm Keh-Shih Chuang, Meei-Ling Jan,2 Jay Wu Sharon Chen Yu-Ching Ni Ying-Kai Fu 2 epartment of Nulear Siene, National
More informationEnumerating pseudo-triangulations in the plane
Enumerating pseuo-triangulations in the plane Sergey Bereg Astrat A pseuo-triangle is a simple polygon with exatly three onvex verties. A pseuo-triangulation of a finite point set S in the plane is a partition
More informationAutomatic Physical Design Tuning: Workload as a Sequence Sanjay Agrawal Microsoft Research One Microsoft Way Redmond, WA, USA +1-(425)
Automati Physial Design Tuning: Workload as a Sequene Sanjay Agrawal Mirosoft Researh One Mirosoft Way Redmond, WA, USA +1-(425) 75-357 sagrawal@mirosoft.om Eri Chu * Computer Sienes Department University
More informationMachine Vision. Laboratory Exercise Name: Student ID: S
Mahine Vision 521466S Laoratory Eerise 2011 Name: Student D: General nformation To pass these laoratory works, you should answer all questions (Q.y) with an understandale handwriting either in English
More informationMulti-Channel Wireless Networks: Capacity and Protocols
Multi-Channel Wireless Networks: Capaity and Protools Tehnial Report April 2005 Pradeep Kyasanur Dept. of Computer Siene, and Coordinated Siene Laboratory, University of Illinois at Urbana-Champaign Email:
More informationOn - Line Path Delay Fault Testing of Omega MINs M. Bellos 1, E. Kalligeros 1, D. Nikolos 1,2 & H. T. Vergos 1,2
On - Line Path Delay Fault Testing of Omega MINs M. Bellos, E. Kalligeros, D. Nikolos,2 & H. T. Vergos,2 Dept. of Computer Engineering and Informatis 2 Computer Tehnology Institute University of Patras,
More informationAn Experimental Study of Fractional Cooperation in Wireless Mesh Networks
An Experimental tudy of Frational Cooperation in Wireless Mesh Networks Anthony Cale, Nariman Farsad, and Andrew W. Ekford Dept. of Computer iene and Engineering, York University 47 Keele treet, Toronto,
More informationDynamic Restoration in Multi-layer IP/MPLS-over- Flexgrid Networks
Dynami Restoration in Multi-layer IP/MPLS-over- Flexgri Networks Alberto Castro, Luis Velaso, Jaume Comellas, an Gabriel Junyent Universitat Politènia e Catalunya (UPC), Barelona, Spain E-mail: aastro@a.up.eu
More informationWhat are Cycle-Stealing Systems Good For? A Detailed Performance Model Case Study
What are Cyle-Stealing Systems Good For? A Detailed Performane Model Case Study Wayne Kelly and Jiro Sumitomo Queensland University of Tehnology, Australia {w.kelly, j.sumitomo}@qut.edu.au Abstrat The
More informationAn Object Model and Algebra for the Implicit Unfolding of Hierarchical Structures 0
An Ojet Moel an Algera for te Impliit Unfoling of Hierarial Strutures 0 Mattew C. Jones an Elke A. Runensteiner Software Systems Resear La University of Miigan, Ann Aror {mjones,runenst}@ees.umi.eu Astrat
More informationMultitarget Data Association with Higher-Order Motion Models
Multitarget Data Assoiation with Higher-Orer Motion Moels Robert T. Collins The Pennsylvania State University University Park, PA 16802, USA Abstrat We present an iterative approximate solution to the
More informationarxiv: v2 [cs.hc] 28 Apr 2018
Clustrophile 2: Guie Visual Clustering Analysis Maro Cavallo an Çağatay Demiralp a arxiv:1804.03048v2 [s.hc] 28 Apr 2018 Fig. 1: Clustrophile 2 is an interative tool for guie exploratory lustering analysis.
More informationA Full-Featured, Error Resilient, Scalable Wavelet Video Codec Based on the Set Partitioning in Hierarchical Trees (SPIHT) Algorithm
A Full-Feature, Error Resilient, Salable Wavelet Vieo Coe Base on the Set Partitioning in Hierarhial Trees (SPIHT) Algorithm Sungae Cho an William A. Pearlman Center for Next Generation Vieo Researh Rensselaer
More informationInternational Journal of Advancements in Research & Technology, Volume 3, Issue 3, March-2014 ISSN
International Journal of Advanements in Researh & Tehnology, Volume 3, Issue 3, Marh-204 ISSN 2278-773 47 Phrase Based Doument Retrieving y Comining Suffix Tree index data struture and Boyer- Moore faster
More informationECE 242 Fall Tilman Wolf 1. Character- by- character processing Special operators
State Mahines University of Massahuse4s Amherst ECE 242 Data Strutures an Algorithms Leture 24 ECE 242 Fall 2013 2013 Tilman Wolf 1 Regular expressions Metho to esrie pa4erns of text Charater- y- harater
More informationAccommodations of QoS DiffServ Over IP and MPLS Networks
Aommodations of QoS DiffServ Over IP and MPLS Networks Abdullah AlWehaibi, Anjali Agarwal, Mihael Kadoh and Ahmed ElHakeem Department of Eletrial and Computer Department de Genie Eletrique Engineering
More informationCOST PERFORMANCE ASPECTS OF CCD FAST AUXILIARY MEMORY
COST PERFORMANCE ASPECTS OF CCD FAST AUXILIARY MEMORY Dileep P, Bhondarkor Texas Instruments Inorporated Dallas, Texas ABSTRACT Charge oupled devies (CCD's) hove been mentioned as potential fast auxiliary
More informationMenu. X + /X=1 and XY+X /Y = X(Y + /Y) = X
Menu K-Maps and Boolean Algera >Don t ares >5 Variale Look into my... 1 Karnaugh Maps - Boolean Algera We have disovered that simplifiation/minimization is an art. If you see it, GREAT! Else, work at it,
More informationLARGE-SCALE INVERSE MICROWAVE BACKSCATTER MODELING OF SEA ICE
LARGE-SCALE INVERSE MICROWAVE BACKSCATTER MODELING OF SEA ICE Quinn P Remun Mirowave Earth Remote Sensing Laboratory Brigham Young University Provo Utah Abstrat Polar sea ie harateristi provie important
More information1 The Knuth-Morris-Pratt Algorithm
5-45/65: Design & Analysis of Algorithms September 26, 26 Leture #9: String Mathing last hanged: September 26, 27 There s an entire field dediated to solving problems on strings. The book Algorithms on
More informationAnchoring quartet-based phylogenetic distances and applications to species tree reconstruction
Anhoring quartet-base phylogeneti istanes an appliations to speies tree reonstrution Erfan Sayyari an Siavash Mirarab Department of Eletrial an Computer Engineering University of California at San Diego
More informationConflicts Analysis for Inter-Enterprise Business Process Model
Conflits Analysis for nter-enterprise Business Proess Moel Wei DNG, Zhong TAN, Jian WANG, Jun ZHU, Haiqi LANG,Lei ZHANG {ingw, tianz, wangwj, zhujun, lianghq, lzhang}@n.ibm.om BM China Researh Lab, BM
More informationAn Efficient Image Distortion Correction Method for an X-ray Digital Tomosynthesis System
An Effiient Image Distortion Corretion Metho for an X-ray Digital Tomosynthesis System J.Y. Kim Dept. of Mehatronis Engineering, Tongmyong University of Information Tehnology, 55 Yongang-ong, Nam-gu, Busan
More informationA DYNAMIC ACCESS CONTROL WITH BINARY KEY-PAIR
Malaysian Journal of Computer Siene, Vol 10 No 1, June 1997, pp 36-41 A DYNAMIC ACCESS CONTROL WITH BINARY KEY-PAIR Md Rafiqul Islam, Harihodin Selamat and Mohd Noor Md Sap Faulty of Computer Siene and
More informationSearching for Entities: When Retrieval Meets Extraction
Searhing for Entities: When Retrieval Meets Extration Qi Li, Daqing He Shool of Information Sienes, University of Pittsburgh Pittsburgh, Pennsylvania, U. S. {qili, aqing}@sis.pitt.eu Abstrat. Retrieving
More informationGray Codes for Reflectable Languages
Gray Codes for Refletable Languages Yue Li Joe Sawada Marh 8, 2008 Abstrat We lassify a type of language alled a refletable language. We then develop a generi algorithm that an be used to list all strings
More informationSparse Certificates for 2-Connectivity in Directed Graphs
Sparse Certifiates for 2-Connetivity in Direted Graphs Loukas Georgiadis Giuseppe F. Italiano Aikaterini Karanasiou Charis Papadopoulos Nikos Parotsidis Abstrat Motivated by the emergene of large-sale
More informationRouting Protocols for Wireless Ad Hoc Networks Hybrid routing protocols Theofanis Kilinkaridis
Routing Protools for Wireless Ad Ho Networks Hyrid routing protools Theofanis Kilinkaridis tkilinka@.hut.fi Astrat This paper presents a partiular group of routing protools that aim to omine the advantages
More informationLearning Non-Linear Reconstruction Models for Image Set Classification
Testing Training Learning Non-Linear Reonstrution Moels for Image Set Classifiation Munawar Hayat, Mohamme Bennamoun, Senian An Shool of Computer Siene an Software Enginnering The University of Western
More informationMulti-Piece Mold Design Based on Linear Mixed-Integer Program Toward Guaranteed Optimality
INTERNATIONAL CONFERENCE ON MANUFACTURING AUTOMATION (ICMA200) Multi-Piee Mold Design Based on Linear Mixed-Integer Program Toward Guaranteed Optimality Stephen Stoyan, Yong Chen* Epstein Department of
More informationA Support-Based Algorithm for the Bi-Objective Pareto Constraint
A Support-Based Algorithm for the Bi-Ojetive Pareto Constraint Renaud Hartert and Pierre Shaus UCLouvain, ICTEAM, Plae Sainte Bare 2, 1348 Louvain-la-Neuve, Belgium {renaud.hartert, pierre.shaus,}@ulouvain.e
More informationTest Case Generation from UML State Machines
Test Case Generation from UML State Mahines Dirk Seifert Loria Université Nany 2 Campus Sientifique, BP 239 F-54506 Vandoeuvre lès Nany edex Dirk.Seifert@Loria.fr inria-00268864, version 2-23 Apr 2008
More informationA Support-Based Algorithm for the Bi-Objective Pareto Constraint
Proeedings of the Twenty-Eighth AAAI Conferene on Artifiial Intelligene A Support-Based Algorithm for the Bi-Ojetive Pareto Constraint Renaud Hartert and Pierre Shaus UCLouvain, ICTEAM, Plae Sainte Bare
More informationImplementing Load-Balanced Switches With Fat-Tree Networks
Implementing Load-Balaned Swithes With Fat-Tree Networks Hung-Shih Chueh, Ching-Min Lien, Cheng-Shang Chang, Jay Cheng, and Duan-Shin Lee Department of Eletrial Engineering & Institute of Communiations
More informationCOSSIM An Integrated Solution to Address the Simulator Gap for Parallel Heterogeneous Systems
COSSIM An Integrated Solution to Address the Simulator Gap for Parallel Heterogeneous Systems Andreas Brokalakis Synelixis Solutions Ltd, Greee brokalakis@synelixis.om Nikolaos Tampouratzis Teleommuniation
More informationDirect-Mapped Caches
A Case for Diret-Mapped Cahes Mark D. Hill University of Wisonsin ahe is a small, fast buffer in whih a system keeps those parts, of the ontents of a larger, slower memory that are likely to be used soon.
More informationAutomated Test Generation from Vulnerability Signatures
Automated Test Generation from Vulneraility Signatures Adulaki Aydin, Muath Alkhalaf, and Tevfik Bultan Computer Siene Department University of California, Santa Barara Email: {aki,muath,ultan}@s.us.edu
More informationOutline. CS38 Introduction to Algorithms. Administrative Stuff. Administrative Stuff. Motivation/Overview. Administrative Stuff
Outline CS38 Introdution to Algorithms Leture 1 April 1, 2014 administrative stuff motivation and overview of the ourse stale mathings example graphs, representing graphs graph traversals (BFS, DFS) onnetivity,
More informationCMSC 430 Introduction to Compilers. Spring Register Allocation
CMSC 430 Introuction to Compilers Spring 2016 Register Allocation Introuction Change coe that uses an unoune set of virtual registers to coe that uses a finite set of actual regs For ytecoe targets, can
More informationPerformance Benchmarks for an Interactive Video-on-Demand System
Performane Benhmarks for an Interative Video-on-Demand System. Guo,P.G.Taylor,E.W.M.Wong,S.Chan,M.Zukerman andk.s.tang ARC Speial Researh Centre for Ultra-Broadband Information Networks (CUBIN) Department
More informationAccelerating Multiprocessor Simulation with a Memory Timestamp Record
Aelerating Multiproessor Simulation with a Memory Timestamp Reord Kenneth Barr Heidi Pan Mihael Zhang Krste Asanovi Marh, 5 Massahusetts Institute of Tehnology Intelligent sampling gives est speed-auray
More informationAlgorithms for External Memory Lecture 6 Graph Algorithms - Weighted List Ranking
Algorithms for External Memory Leture 6 Graph Algorithms - Weighted List Ranking Leturer: Nodari Sithinava Sribe: Andi Hellmund, Simon Ohsenreither 1 Introdution & Motivation After talking about I/O-effiient
More informationMessage Transport With The User Datagram Protocol
Message Transport With The User Datagram Protocol User Datagram Protocol (UDP) Use During startup For VoIP an some vieo applications Accounts for less than 10% of Internet traffic Blocke by some ISPs Computer
More informationChapter 9. Greedy Technique. Copyright 2007 Pearson Addison-Wesley. All rights reserved.
Chpter 9 Greey Tehnique Copyright 2007 Person Aison-Wesley. All rights reserve. Greey Tehnique Construts solution to n optimiztion prolem piee y piee through sequene of hoies tht re: fesile lolly optiml
More informationPerformance Enhancement Techniques for InfiniBand TM Architecture
Performane Enhanement Tehniques for InfiniBand TM Arhiteture Eun Jung Kim? Ki Hwan Yum y Chita R. Das? Mazin Yousif z JoséDuato x? Department of Computer Siene and Engineering The Pennsylvania State University
More informationAnalysis of input and output configurations for use in four-valued CCD programmable logic arrays
nalysis of input and output onfigurations for use in four-valued D programmable logi arrays J.T. utler H.G. Kerkhoff ndexing terms: Logi, iruit theory and design, harge-oupled devies bstrat: s in binary,
More informationRecommendation Subgraphs for Web Discovery
Reommation Subgraphs for Web Disovery Arda Antikaioglu Department of Mathematis Carnegie Mellon University aantika@andrew.mu.edu R. Ravi Tepper Shool of Business Carnegie Mellon University ravi@mu.edu
More informationOverview. Operating Systems I. Simple Memory Management. Simple Memory Management. Multiprocessing w/fixed Partitions.
Overview Operating Systems I Management Provie Services processes files Manage Devices processor memory isk Simple Management One process in memory, using it all each program nees I/O rivers until 96 I/O
More informationEstablishing Secure Ethernet LANs Using Intelligent Switching Hubs in Internet Environments
Establishing Seure Ethernet LANs Using Intelligent Swithing Hubs in Internet Environments WOEIJIUNN TSAUR AND SHIJINN HORNG Department of Eletrial Engineering, National Taiwan University of Siene and Tehnology,
More informationThe influence of defeated arguments in defeasible argumentation
The influene of efeate arguments in efeasible argumentation Bart Verheij University of Limburg, Department of Metajuriia P.O. Box 616, 6200 MD Maastriht, The Netherlans fax: +31 43 256538 email: bart.verheij@metajur.rulimburg.nl
More informationA Partial Sorting Algorithm in Multi-Hop Wireless Sensor Networks
A Partial Sorting Algorithm in Multi-Hop Wireless Sensor Networks Abouberine Ould Cheikhna Department of Computer Siene University of Piardie Jules Verne 80039 Amiens Frane Ould.heikhna.abouberine @u-piardie.fr
More informationPredicting Project Outcome Leveraging Socio-Technical Network Patterns
203 7th European Conferene on Software Maintenane an Reengineering Preiting Projet Outome Leveraging Soio-Tehnial Network Patterns Dii Surian, Yuan Tian, Davi Lo, Hong Cheng an Ee-Peng Lim Shool of Information
More informationChapter 2: Introduction to Maple V
Chapter 2: Introdution to Maple V 2-1 Working with Maple Worksheets Try It! (p. 15) Start a Maple session with an empty worksheet. The name of the worksheet should be Untitled (1). Use one of the standard
More informationCluster-based Cooperative Communication with Network Coding in Wireless Networks
Cluster-based Cooperative Communiation with Network Coding in Wireless Networks Zygmunt J. Haas Shool of Eletrial and Computer Engineering Cornell University Ithaa, NY 4850, U.S.A. Email: haas@ee.ornell.edu
More informationExploiting Longer Cycles for Link Prediction in Signed Networks
Exploiting Longer Cyles for Link Predition in Signed Networks Kai-Yang Chiang kyhiang@s.utexas.edu Nagarajan Natarajan naga86@s.utexas.edu Inderjit S. Dhillon inderjit@s.utexas.edu Amuj Tewari amuj@s.utexas.edu
More informationCapturing Large Intra-class Variations of Biometric Data by Template Co-updating
Capturing Large Intra-lass Variations of Biometri Data by Template Co-updating Ajita Rattani University of Cagliari Piazza d'armi, Cagliari, Italy ajita.rattani@diee.unia.it Gian Lua Marialis University
More informationDynamic Algorithms Multiple Choice Test
3226 Dynami Algorithms Multiple Choie Test Sample test: only 8 questions 32 minutes (Real test has 30 questions 120 minutes) Årskort Name Eah of the following 8 questions has 4 possible answers of whih
More informationZippy - A coarse-grained reconfigurable array with support for hardware virtualization
Zippy - A oarse-grained reonfigurable array with support for hardware virtualization Christian Plessl Computer Engineering and Networks Lab ETH Zürih, Switzerland plessl@tik.ee.ethz.h Maro Platzner Department
More informationA Compressed Breadth-First Search for Satisfiability
A Compressed Breadth-First Searh for Satisfiaility DoRon B. Motter and Igor L. Markov Department of EECS, University of Mihigan, 1301 Beal Ave, Ann Aror, MI 48109-2122 dmotter, imarkov @ees.umih.edu Astrat.
More informationThe Happy Ending Problem
The Happy Ending Problem Neeldhara Misra STATUTORY WARNING This doument is a draft version 1 Introdution The Happy Ending problem first manifested itself on a typial wintery evening in 1933 These evenings
More informationAbstract. We describe a parametric hybrid Bezier patch that, in addition. schemes are local in that changes to part of the data only aect portions of
A Parametri Hyrid Triangular Bezier Path Stephen Mann and Matthew Davidhuk Astrat. We desrie a parametri hyrid Bezier path that, in addition to lending interior ontrol points, lends oundary ontrol points.
More informationCompilation Lecture 11a. Register Allocation Noam Rinetzky. Text book: Modern compiler implementation in C Andrew A.
Compilation 0368-3133 Leture 11a Text book: Modern ompiler implementation in C Andrew A. Appel Register Alloation Noam Rinetzky 1 Registers Dediated memory loations that an be aessed quikly, an have omputations
More information3D Drone-Cell Deployment Optimization for Drone Assisted Radio Access Networks
3D Drone-Cell Deployment Optimization for Drone Assiste Raio Aess Networks (Invite Paper) Weisen Shi, Junling Li, Wenhao Xu, Haibo Zhou, Ning Zhang, an Xuemin (Sherman) Shen, Department of Eletrial an
More informationA Load-Balanced Clustering Protocol for Hierarchical Wireless Sensor Networks
International Journal of Advanes in Computer Networks and Its Seurity IJCNS A Load-Balaned Clustering Protool for Hierarhial Wireless Sensor Networks Mehdi Tarhani, Yousef S. Kavian, Saman Siavoshi, Ali
More informationA Dual-Hamiltonian-Path-Based Multicasting Strategy for Wormhole-Routed Star Graph Interconnection Networks
A Dual-Hamiltonian-Path-Based Multiasting Strategy for Wormhole-Routed Star Graph Interonnetion Networks Nen-Chung Wang Department of Information and Communiation Engineering Chaoyang University of Tehnology,
More informationUplink Channel Allocation Scheme and QoS Management Mechanism for Cognitive Cellular- Femtocell Networks
62 Uplink Channel Alloation Sheme and QoS Management Mehanism for Cognitive Cellular- Femtoell Networks Kien Du Nguyen 1, Hoang Nam Nguyen 1, Hiroaki Morino 2 and Iwao Sasase 3 1 University of Engineering
More informationBoosted Random Forest
Boosted Random Forest Yohei Mishina, Masamitsu suhiya and Hironobu Fujiyoshi Department of Computer Siene, Chubu University, 1200 Matsumoto-ho, Kasugai, Aihi, Japan {mishi, mtdoll}@vision.s.hubu.a.jp,
More informationMining Edge-Weighted Call Graphs to Localise Software Bugs
Mining Edge-Weighted Call Graphs to Loalise Software Bugs Frank Eihinger, Klemens Böhm, and Matthias Huer Institute for Program Strutures and Data Organisation (IPD), Universität Karlsruhe (TH), Germany
More informationLearning Convention Propagation in BeerAdvocate Reviews from a etwork Perspective. Abstract
CS 9 Projet Final Report: Learning Convention Propagation in BeerAdvoate Reviews from a etwork Perspetive Abstrat We look at the way onventions propagate between reviews on the BeerAdvoate dataset, and
More informationA Dictionary based Efficient Text Compression Technique using Replacement Strategy
A based Effiient Text Compression Tehnique using Replaement Strategy Debashis Chakraborty Assistant Professor, Department of CSE, St. Thomas College of Engineering and Tehnology, Kolkata, 700023, India
More informationStriD 2 FA: Scalable Regular Expression Matching for Deep Packet Inspection
StriD FA: Scalale Regular Expression Matching for Deep Packet Inspection Xiaofei Wang Junchen Jiang Yi Tang Yi Wang Bin Liu Xiaojun Wang School of Electronic Engineering, Dulin City University, Dulin,
More informationAbstract. Key Words: Image Filters, Fuzzy Filters, Order Statistics Filters, Rank Ordered Mean Filters, Channel Noise. 1.
Fuzzy Weighted Rank Ordered Mean (FWROM) Filters for Mixed Noise Suppression from Images S. Meher, G. Panda, B. Majhi 3, M.R. Meher 4,,4 Department of Eletronis and I.E., National Institute of Tehnology,
More informationOutline: Software Design
Outline: Software Design. Goals History of software design ideas Design priniples Design methods Life belt or leg iron? (Budgen) Copyright Nany Leveson, Sept. 1999 A Little History... At first, struggling
More informationSystem-Level Parallelism and Throughput Optimization in Designing Reconfigurable Computing Applications
System-Level Parallelism and hroughput Optimization in Designing Reonfigurable Computing Appliations Esam El-Araby 1, Mohamed aher 1, Kris Gaj 2, arek El-Ghazawi 1, David Caliga 3, and Nikitas Alexandridis
More informationDETECTION METHOD FOR NETWORK PENETRATING BEHAVIOR BASED ON COMMUNICATION FINGERPRINT
DETECTION METHOD FOR NETWORK PENETRATING BEHAVIOR BASED ON COMMUNICATION FINGERPRINT 1 ZHANGGUO TANG, 2 HUANZHOU LI, 3 MINGQUAN ZHONG, 4 JIAN ZHANG 1 Institute of Computer Network and Communiation Tehnology,
More informationThe Minimum Redundancy Maximum Relevance Approach to Building Sparse Support Vector Machines
The Minimum Redundany Maximum Relevane Approah to Building Sparse Support Vetor Mahines Xiaoxing Yang, Ke Tang, and Xin Yao, Nature Inspired Computation and Appliations Laboratory (NICAL), Shool of Computer
More informationFlow Demands Oriented Node Placement in Multi-Hop Wireless Networks
Flow Demands Oriented Node Plaement in Multi-Hop Wireless Networks Zimu Yuan Institute of Computing Tehnology, CAS, China {zimu.yuan}@gmail.om arxiv:153.8396v1 [s.ni] 29 Mar 215 Abstrat In multi-hop wireless
More information