On - Line Path Delay Fault Testing of Omega MINs M. Bellos 1, E. Kalligeros 1, D. Nikolos 1,2 & H. T. Vergos 1,2

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1 On - Line Path Delay Fault Testing of Omega MINs M. Bellos, E. Kalligeros, D. Nikolos,2 & H. T. Vergos,2 Dept. of Computer Engineering and Informatis 2 Computer Tehnology Institute University of Patras, , Rio, Greee 3, Kolokotroni Str., Patras, Greee {tarka, kalliger}@eid.upatras.gr, {nikolosd, vergos}@ti.gr Abstrat This paper studies path delay fault testing of Omega Multistage Interonnetion Networks (MINs). Taking advantage of the MIN s parallelism, we show that although the number of physial paths is O(n 2 ), all these paths an be tested optimally for path delay faults applying O(n) test pairs. Having derived the test set, we also show how the test set appliation as well as the verifiation an be done either by a dediated low ost tester or online using the system resoures. I. Introdution Many kinds of MINs have been proposed and built for use in massively parallel omputers [, 2]. In this paper we onsider Omega MINs with entralized ontrol. Testing of MINs has been widely onsidered with respet to the state stuk-at fault model, the link fault model and the swith fault model, for example [3, 4]. However, physial defets in integrated iruits an degrade iruit performane without altering their logi funtionality. Apart from this, inreasing performane requirements of the ontemporary VLSI iruits makes it diffiult to design them with large timing margins. Thus impreise delay modeling and the statistial variations of the parameters during the manufaturing proess may result in iruits with longer than the expeted delays. The hange in the timing behavior of the iruit in this paper is modeled aording to the path delay fault model under whih a path is delared faulty if it fails to propagate a transition from the path input to the path output within a speified time interval [5]. The path delay fault model, sine it aptures the umulative effet of small delay variations in gates along a path as well as the faults aused by a single gate, is deemed to be the most general among all delay fault models. Two major problems disourage the use of the path delay fault model. The first is that only a very small subset of the paths of a design an be robustly tested for path delay faults (under either the stringent Single Path Propagating Hazard Free or the more relaxed Validatable Robustly Testable limitations). In this paper sine we onsider that eah swith of the MIN is implemented by multiplexers, a robust two pattern test for eah path an be derived [6]. The seond problem is that the number of physial paths in a ontemporary IC is exessively large for testing every path. Usually, a subset of the physial paths is seleted for path delay fault testing based either on their propagation delay or on funtional approahes [7]. However the number of paths seleted by both methods is so large in general that all the seleted paths annot be tested, espeially in performane optimized iruits [8]. This is espeially true in the ase of Omega MINs where most of the physial paths are of ritial delay. To this end, by taking advantage of the parallelism of the MIN, we show that although the number of physial paths is O(n 2 ), all these paths an be tested optimally for path delay faults applying O(n) test pairs. In this paper we onsider nxn Omega MINs, with n=2 k, implemented as a set of b/m M-bit slies [9], where b is the size of the bus of eah soure and destination onneted by the network, M b and eah slie has been implemented as a VLSI hip. For M = b the network has been implemented on a single hip (probably on a single wafer). In this paper, apart from deriving an optimal test set, we will also present : a) a low-ost tester for prodution testing of the MIN and b) the way that this test set an be applied to the MIN and how its s are verified on-line. II. Preliminaries A physial path of a iruit is an alternating sequene of gates and lines leading from a primary input to a primary output of the iruit. In delay fault test generation we assoiate two logial paths with eah physial path. A logial path is a pair (T, p) with T = x x and x {0, }, being a transition at the input of p. In the ase of delay fault testing the test set onsists of pairs of s. The ardinality of the test set, that is, the number of pairs of s depends on the number of the paths that must be tested and the perentage of the paths that an be tested in parallel. Throughout the paper the term test session is used to denote the appliation of a test pair. An Omega MIN is onstruted from N=log 2 n stages of swithes, where eah of the stages has (n/2) 2x2 swithes. The swith stages are labeled from to N. We onsider that the soure and destination nodes onstitute the stages 0 and N+, respetively. The interonnetion pattern between adjaent stages is the perfet shuffle permutation [0]. This holds for all pairs of stages exept N and N+. Figure shows an 8x8 Omega MIN. A onflit of the MIN appears when any two soures are trying to set a swith of

2 the network in omplementary states. Soure S 0 S S 2 S 3 S 4 S 5 S 6 S 7 stage 0 Swith,,2,3,4 2, 3, 2,2 2,3 2,4 3,2 3,3 3,4 stage stage 2 stage 3 Figure. 8x8 Omega Network Destination D 0 D D 2 D 3 D 4 D 5 D 6 D 7 stage 4 simply lines). The analysis will be valid for all M lines of the bus. We note that to every virtual path or line orrespond two logial virtual paths. In an nxn Omega MIN we distinguish the paths in two sets: those not inluding subpaths souring from a ontrol input and those whih do. Sine the onnetions of soures to destinations hange dynamially during system operation, delays that stem from the ontrol signals are also signifiant. Let P be the set onsisting of all virtual paths starting from any soure and ending at any destination. Sine there are n soures and there is only one path from one of them to all the destinations, the number of all possible virtual paths is n 2. That is the ardinality of P, denoted P, is P = n 2. i i i i Control a) Swith S = 0 b) Diret state i i 6 = ) Cross state i Figure 2. Eah swith S, (Figure 2.a) has a pair of input data buses,, a pair of output data buses, and a ontrol signal. All four buses are unidiretional and idential in size. The two states of the swith S are determined by the ontrol line as follows: the diret state (Figure 2.b), where the values of, are propagated to, respetively, and a ross state (Figure 2.), where the values of, are propagated to, respetively. The upper input and output are labeled with 0 while the lower are labeled with. Eah swith is onstruted from 2M 2-> multiplexers, where M is the size of the buses. Eah pair of multiplexers, (Figure 2.d), aepts two lines of, buses, the ontrol signal and drives the orresponding lines of buses,. Without loss of generality we onsider that eah link is a single virtual line, that may atually represent either one physial line or a physial bus. For testing purposes any value of the virtual line is always applied to every line of the physial bus that it may represent. Paths along the MIN are formed by onatenation of subpaths along links and subpaths through swithes of the MIN as well as by subpaths souring from the ontrol signals. We will hereafter present the analysis based on virtual lines (or d) i i a) =0, i = b) =, i =0 Figure 3. Let L be the set onsisting of all paths starting from the ontrol input of a swith and ending at any destination. Figures 3.a and 3.b present the subpaths from the ontrol input of a swith through two of its 2M multiplexers for =0 and i = and for = and i =0. Sine the transition, during delay testing, propagates from the ontrol input through 2M multiplexers and along the lines of the bus, in this ase we refer also to virtual paths. For omputing the number of the virtual paths starting from a ontrol input we observe that at every stage the ontrol input of a swith an be seen as the root of two full binary trees having the destinations as leaves. Eah suh tree has a depth of N-i+, where i is the number of the stage and i {, 2,..., N}. The latter means that every suh tree has 2 N-i+ leaves whih is also the number of virtual paths. Sine eah stage has n/2 swithes and eah swith is the root of two trees, there are 2*(n/2)*2 N-i+ virtual paths starting from eah stage's ontrol inputs. Thus the ardinality of L is equal to the sum of the virtual paths starting from every ontrol input, whih is: N n N i+ n L = 2 2 = 2 2(2 N -) = 2n(n-) i= 2 2 Therefore the total number of virtual paths is equal to: P + L = 3n 2-2n and the number of all logial virtual paths is: LV = 2(3n 2-2n). The number of physial lines is equal to M(3n 2-2n), however the propagation delays along the M lines of the bus are measured in parallel. Note that every physial path is sensitizable. Although the number of the virtual paths of an nxn Omega network is O(n 2 ) we will show in the next setion

3 that due to the inherent parallelism of the network testing along various paths an be done in parallel. III. Parallel path delay fault testing It is well known that in an Omega network when the ontrol inputs get a set of values eah soure is onneted to a different destination. Throughout this setion we onsider that all ontrol inputs of stage i, for i=, 2,..., N, of the Omega network take the same value i. Changing the value of the ontrol inputs of a stage i the swithes of this stage alternate between the two states of Figures 2.b and 2., and all paths from soures to destinations hange. Then taking into aount that in the Omega network only one path exists from a speifi soure to a speifi destination we onlude that for the two sets of values 2... N and of ' 2 '... N ', with 2... N ' 2 '... N ', a ommon path from the soure to destination in both onfigurations of the network does not exist. Therefore, applying to 2... N all possible values, that is 2 N different values, we ensure that eah soure has been onneted to eah destination. A feature of the Omega network is that every soure an be onneted to every destination. Sine we have n destinations we onlude that at least n value ombinations of the ontrol signals are neessary so that eah soure gets onneted to eah destination. From the above disussion we onlude that 2 N is the least number of onfigurations that ensures that all possible paths from soures to destinations have been established. For eah onfiguration, that is a value of 2... N, the delays along n virtual paths an be measured, hene 2*2 N test sessions are required in order to measure the delays along all logial virtual paths from soures to destinations. Let T p denote the number of test sessions required to measure the delays along all paths from soures to destinations. Then : T p = 2*2 N = 2n () At every stage i a ontrol input an be seen as a root of two full binary trees having the destinations as leaves. Every suh tree has 2 N-i+ virtual paths from the root to the leaves, as disussed earlier. For any value of i+ i+2... N two paths starting from the ontrol input of eah swith of the stage i get established, whih means that 2*n/2 virtual paths starting from the ontrol inputs an be tested in parallel. Sine two trees eah one with 2 N-i+ virtual paths orrespond to eah swith of the stage i, we onlude that 2 * 2 * 2 N-i+ / 2 test sessions are required for testing the logial virtual paths starting from a ontrol input of stage i. Taking into aount that i=, 2,..., N we get that the total number of test sessions T L for measuring the propagation delays along the virtual paths starting from ontrol inputs N N i+ i= are: T L = 2 * 2 = 4(2 N -) = 4(n-) (2) From relations () and (2) we get: T p + T L = 2(3n-2). Therefore, while the number of virtual paths of a nxn Omega network is O(n 2 ) we have shown that the number of the required test sessions is O(n). In a iruit with n outputs the maximum number of paths that an be tested in parallel is equal to n. Then taking into aount that the number of all logial virtual paths of the nxn Omega network is equal to 2(3n 2-2n) and the fat that 2(3n-2) test sessions are required we onlude that this is the optimal number of test sessions required to test all possible paths. Table. Test s for the P paths of the 8x8 Omega network. T T T T T T T T* 0 T T T T T T T T P T T T T T T T T T T T T T T T T 0 T T T T T T T T 0 0 T T T T T T T T 0 T T T T T T T T 0 T T T T T T T T * T denotes a 0-> and a ->0 transition. Table 2. Test set for the L paths of the 8x8 Omega network T T 0 T 0 0 T 0 0 T 0 T L T T T 0 T 0 T 0 T 0 T T Table presents a test set suitable for parallel path delay fault testing of P paths for the MIN of Figure. As an been seen from this table, for testing the paths of P, we need to apply both 0-> and ->0 transitions at every soure for every value of the ontrol inputs. For the paths of set L, we need to apply omplementary s at the soures, for every transition required at the ontrol inputs. There exist many distint sets of test pairs that an be used for path delay testing of the paths belonging to L (suh a possible test set is presented in Table 2). From Table 2 we an easily see that the number of distint test s that must be applied to the soure inputs of the network is six. For large networks this number an be very large. Reduing the number of distint soure inputs, during the testing of L paths simplifies both the on-line testing of the network using resoures of the system as well as the appliation of the test set during prodution testing. To this end, we introdue a test set onsisting only of two omplementary s for the soure inputs no matter what the size of the MIN is. The derivation of one of the s of the proposed test set an be done aording to the following rules: Rule. For the 4x4 Omega MIN the test is 0 0. Rule 2. Reursively alulate the test v of the nxn Omega MIN from the test u of the (n/2) x (n/2) MIN by using the following : v i = u i and v i+(n/2) = u i, for i = 0,, 2,, (n/2). Table 3 presents the outome of the appliation of these rules to an 8x8 MIN. By applying the proposed test s at the inputs of the MIN we assure that eah stage of swithes reeives at

4 its inputs, ordered from top to bottom, either the applied test or its omplementary (the proof is omitted due to spae limitations). Table 3. Test set for the L paths of the 8x8 Omega network T 0 T 0 0 T T T 0 0 T L 0 0 T 0 0 T 0 0 T T T T T 0 0 T IV. Low-ost Tester. For prodution testing of the MIN we introdue a lowost tester. This will be omprised of : a) an up-down log 2 n bit Gray ounter, b) n*m T flip-flops, ) 2*n*M D flipflops, d) a 2*n*M input 2-rail er tree and e) some additional logi for ontrolling the omponents of the tester. The tester is fed with a lok frequeny f. The blok diagram of the tester is depited in Figure 4. The outputs of the Gray ounter drive the ontrol signals of the MIN. Eah MIN soure is driven by one of the T flip-flops. The T flip-flops are used in order to produe one of the two omplementary test s presented in Setion III. Eah output of the MIN drives two D flip-flops as shown in Figure 5. The flip-flop outputs are driven to a tree of 2-rail ers. When the MIN operates orretly at speed, the outputs of this er are at omplementary values. For testing the paths of set P, the Gray ounter and the D flip-flops are reset. The T flip-flops are driven by f, while the Gray ounter is driven by a lok with frequeny f/5. We assume that eah new yle begins with every rising edge of f. During the 5 yles that the Gray ounter is stable the following take plae (see Figure 6) : the first yle is used to set the MIN to a new onfiguration. At the next yle the first test is applied to the inputs of the MIN. The omplementary and the original test are applied at the start of the third and the fourth yles respetively and the s of the MIN are aptured by the D flip-flops. The fifth yle is utilized for apturing the of the MIN to the test applied during the fourth yle. The 2-rail er is enabled at the middle of the fourth and the fifth yles. The proedure is repeated until the Gray ounter passes from all its states ounting upwards. For testing the paths of set L, the first of the omplementary s is applied to the MIN inputs. The Gray ounter hanges values every two yles (suppose first and seond yle). The ounter is permitted to go through all of its states in both up and down diretion. Then the seond is applied and the ounting proedure is repeated. The s are aptured at the start of eah seond yle and verified at the middle of it by the 2-rail er as shown in Figure 7. The above desribed low-ost tester was designed and its orret funtion was verified by simulation. Blok of n*m T flip-flops tester lok f Up-down Gray ounter MIN Control signals Blok of 2*n*M D flip-flops 2-rail er Figure 4. The dediated tester ontrol signal ΜΙΝ's output ontrol signal 2 D Q FF D Q FF 2 To 2- rail er Figure 5. D flip-flops at MIN outputs set MIN Apply st Apply 2nd at FF Apply 3rd at FF 2 s set MIN at FF Error Indiator s Figure 6. Test sheme for testing the paths of set P tester lok f Configure Apply MIN on MIN soures at state C at FF Configure MIN at state C' at FF 2 s Figure 7. Test sheme for testing the paths of set L V. On line testing. We onsider that the MIN is used for interonneting proessors that are synhronized by a ommon lok. The ommuniation among the proessors is established after requests towards the entralized ontrol. One the entralized ontrol onfigures the MIN, the proessors an exhange data. If the entralized ontrol iruit an not establish a requested onfiguration (for example when two soures request ommuniation with the same destination) it will use some priority sheme for serving some of the requests and it will signal inability to the rest soures. During a data transfer all the ontrol signals are stable (i.e. the MIN remains at a fixed onfiguration). We further assume that the onfiguration is stable when there are no

5 new requests. The proessors have different input and output buffered ports. We assume that the ommuniation sheme is performed by: Step. The start of the ommuniation is indiated by a rising edge of the lok. At that moment eah proessor plaes its data on the output buffer and sends a request to the entralized ontrol. Step 2. At the next rising edge the entralized ontrol sets the MIN to the appropriate onfiguration and the proessors are notified if they should proeed with transmission or reeption of data. Step 3. At eah subsequent rising edge of the lok, eah proessor an send or reeive a word or both, by enabling its orresponding buffers. We assume that all buffers are of equal size and a ommuniation session terminates when all buffers are empty. Under these assumptions the appliation of the derived test set and the verifiation of the s an be done in system environment as follows : a) For the pairs of s that test the paths of set P eah soure's transmission buffer is filled with the test s that will ativate the two desired transitions. b) The proessors send requests that will not ause any onflit in the MIN. We will present a proedure that ensures onflit free onfigurations of the MIN below. ) The paths are onsidered fault free when the transition is identified one lok period after the data are plaed on the inputs of the MIN. This is performed by verifying the ontents of the input buffer of eah proessor after the end of a ommuniation session. d) In order to test the paths of set L we start a ommuniation session whih will transmit one of the test s mentioned above over the MIN. This ommuniation session will set the ontrol signals of the MIN to a known state whih will be stable until the next requests issued by the proessors. e) At the next ommuniation session the requests issued by the proessors ause the required transition of the ontrol signals of the onsidered stage. The transition is observed at the outputs of the MIN at the rising edge of the lok one lok period after the MIN is set. Again the path is delared fault free after the verifiation of the ontents of eah proessors' input buffer. For ahieving onflit free onfigurations of the MIN, all soures simulate an up-down Gray ounter. The outputs of the simulated ounters are used by eah soure for omputing the address of the desired destination in order to issue a request to the entralized ontrol unit. All the simulated ounters must be reset and advaned to a new value simultaneously. Every time the simulated ounter produes a new value, eah soure exeutes a proedure with inputs the new value of the ounter and the soure's label. Suh a proedure based on the perfet shuffle permutation is presented below. Let sr, dest denote the binary representations of the labels of the soure and the targeted destination proessors respetively. Let i be the i- th bit of the simulated Gray ounter The proposed proedure is omposed of the following steps : Step : Set dest = sr. Step 2 : Set i =. Step 3 : Perform the perfet shuffle permutation on dest (binary rotation). Step 4 : If i = 0 go to Step 6. Step 5 : If the LSB of dest is 0 then set dest = dest + else set dest = dest -. Step 6 : Set i = i +. Step 7 : If i log 2 n then go to Step 3 else end. VI. Conlusions In this work we studied path delay fault testing of Omega MINs. The ontributions of this work are : a) We have shown, by taking advantage of the MIN parallelism, that the O(n 2 ) physial paths of the MIN an be tested optimally by O(n) test pairs. b) We have derived an optimal test set for parallel path delay fault testing of the MIN. ) We have shown how the appliation of the test set as well as the verifiation of the MIN an be done either off-line by a dediated low ost tester or on-line using the system resoures. Referenes [] H. J. Siegel, "Interonnetion Networks for Large - Sale Parallel Proessing", 2nd ed., MGraw-Hill, 990. [2] T. Feng, "A Survey of Interonnetion Networks", Computer, Deember 98, pp [3] D. P. Agrawal, " Testing and Fault Tolerane of Multistage Interonnetion Networks", Computer, April 982, pp [4] V. P. Kumar and S. M. Reddy, "Augmented Shuffle- Exhange Multistage Interonnetion Networks". Computer, June 987, pp [5] G. L. Smith, "Model for Delay Faults Based upon Paths", Pro. of ITC-85, pp [6] P. Ashar, et. al., "Path-delay-fault testability properties of multiplexer - based networks", Integration, The VLSI Journal, vol.5, (no.), July 993. pp. -23 [7] S. Tani, et. al, "Effiient Path Seletion for Delay Testing Based on Partial Path Evaluation", Pro. of VTS '98, pp [8] T. W. Williams et. al., "The Interdependene between Delay-Optimization of Synthesized Networks and Testing", Pro. of 28 th DAC, pp. 9-25, ACM / IEEE 995. [9] M. A. Franklin, et. al, "Pin Limitations and Partitioning of VLSI Interonnetion Networks", IEEE Trans. on Comp., C-3, November 982, pp [0] H. S. Stone, "Parallel Proessing with the Perfet Shuffle", IEEE Trans. on Comp., C-20, pp. 53-6, 97.