Implementation of Pipelined Canny Edge Detection Algorithm

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1 Implementation of Pipelined Canny Edge Detection Algorithm 1 Suman S, 2 R. Sundaraguru 1,2 Dept. of ECE, Sir. MVIT, Bengaluru, Karnataka, India Abstract- Edge may be defined as discontinuities in image intensity from one pixel to other. Edge detection is the important tasks in most computer vision applications. The canny edge detection is verified to be able to significantly outperform existing edge detection techniques due to its higher performance. Unfortunately, the implementation of the systems in real-time is computationally complex and high hardware cost with increased latency and throughput with no loss in edge detection. The proposed canny edge detection algorithm makes use gradient approximation technique to replace the complex operations; we make use of pipelining to reduce the latency and resource utilization. The algorithm is implemented on Xilinx Virtex-5 FPGA. When compared with the previous hardware architecture, the proposed architecture requires fewer hardware costs to detect the edges of 512x512 images. Keywords: Edge detection, canny edge detection, FPGA, Throughput. I. INTRODUCTION Edge detection is basic operation in image processing and computer vision applications. The purpose of edge detection is to significantly reduce the amount of data in an image, while preserving the structural properties to be used for further image processing. It is used to identify changes in brightness of the image due to changes in scene structure. There are many edge detection operators available. These operators identify vertical, horizontal, step and corner edges. The quality of detected edges by these operators is highly dependent on lighting conditions, noise, objects of same density and the intensities of edges in the scene. A large variety of operators are existing that can extract the edges from noisy image. The Canny edge detector is used over a years for edge detection and has better performance.canny edge detector is also known as optimal edge detector. Intentions are to enhance the many edge detectors in the image. Edge detection is provided the stage for many image processing algorithm for example image segmentation, image enhancement and image video coding. Typically, canny edge detection algorithms are implemented using software, with advances in Very Large Scale Integration (VLSI) technology. Real time application used hardware implementation. The Canny edge detector is largely used in numerous real-world applications due to its ability to extract significant edges with good detection and good localization performance. This algorithm is very useful algorithm.the Canny edge detection algorithm performs hysteresis thresholding which computes high and low thresholds based on the entire image statistics. This spaces heavy requirements on memory and results in large latency hindering real-time implementation of the canny edge detection algorithm. II. LITERATURE SURVEY Various types of operators are available for finding edges. In first order derivative, input image is convolved with an adapted mask to generate a gradient image, where edges are identified by thresholding. Sobel, Robert and Prewitt, are the first order derivative operators [1]. These operators are also known as gradient operators. Gradient operators detect edges by looking for maximum and minimum intensity values.these operators examine the distribution of intensity values to the neighborhood of a given pixel and determine whether the pixel is to be classified as an edge.threshold values are inured to detect edges. The output of the edge detectors is sensitive to the threshold. These operators are more sensitive to noise and facing a problem of false edge detection and missing edges. To overcome these disadvantages an optimal edge detection canny algorithm [2] is present. Canny proposes a new approach for detecting edges that is optimal for step edges contaminated by noise. The optimality of the detector is associated to three criteria: Low error rate: no edges should be missed and should not get spurious responses. Localization: distance between points marked by the detector and the actual Centre of the edge should be less. Response: only single response for single edge. Chandrashekar N.S., Dr. K.R. Nataraj implemented Canny algorithm [3] on a Xilinx Virtex-4 FPGA platform and tested its working. The design development is done in VHDL and simulates the results in modelsim 6.3 using Xilinx

2 Tejaswini H.R. Implemented distributed canny edge detection algorithm [4] that gives decrease in latency, optimal use of memory and increase in throughput with no downfall in edge detection performance compared to original edge detection algorithm on FPGA.Chaithra.N.M, K.V. Ramana Reddy[5] present canny edge detection algorithm implemented on Spartan 3E FPGA and developed VGA interfacing for displaying images on the screen[5] Image is displayed on the monitor through FPGA. B.Muralikrishna, P.Sujitha, Habibulla Khan [6] created IP Core for application i.e. edge Detection and this core is added to the Xilinx Library and integrated into design and added VHDL code according to functionality. Finally able built embedded system and added design to that system and executed the complete system on FPGA. III. SYSTEM DESIGN Canny developed a methodology to derive an optimal edge detector based on three criteria related to the detection performance. The model was based on a step edge corrupted by additive while Gaussian noise. The Canny algorithm consists of the following steps; 1. smoothing the input image by Gaussian mask. 2. Calculating horizontal gradient Gx and vertical gradient Gy at each pixel location by convolving with gradient masks. 3. Computing the gradient magnitude and direction at each pixel location. 4. Applying non-maximum suppression (NMS) to thin edges. 5. Computing the hysteresis high and low threshold based on the histogram of the magnitude of the gradients of the entire image. 1. Smoothing: Smoothing is achieved by Gaussian convolutions. Blurring of the image to remove noise. 2. Finding the Gradients: Gradient calculation is performed using Finite-impulse-Response (FIR) gradient masks designed to approximate 2D sample version of partial derivative of Gaussian Function. The size of gradient mask used by canny edge detector is function of standard deviation. Fig. 1: Block diagram of the canny edge detection algorithm 3. Calculation of Gx and Gy: The actual images are always discrete; we define the direction as vertical, horizontal, left-diagonal and right-diagonal of the 3x3 adjacent window of current pixel. The first-derivative of each direction is then calculated by E = ({-1, 1}) 3 X 3 X H (i,j)3 X 3 (2.9) Using a {-1, +1} operator to the adjacent pixels along each direction, we get EV, EH, EDL and EDR, the results of equation in vertical, horizontal, left-diagonal and right-diagonal directions. The magnitude of gradient of current pixel is the maximum of EH, EV, EDR, EDL, and the direction of gradient is one of the four directions corresponding to the maximum of EH, EV, EDR, EDL. grads (H(I,j)) =max { EH, EV, EDR, EDL } Θ = Arg (max { EH, EV, EDR, EDL }) Since 3x3 convolutions are used to calculate the gradients, neighboring 8 pixels are required. FIFO buffers are employed to store the output pixels. 4. Non-Maximal Suppression: Once the direction of the gradient is known, the pixel that has no local maximum gradient magnitude is eliminated. If the pixel s gradient direction is one of 8 possible main directions (0º, 45º, 90º, 135º, 180º, 225º, 270º, 315º), the gradient magnitude of this pixel is compared with two of its immediate neighbors along the gradient direction and the gradient magnitude is set to zero if it does not correspond to a local maximum. For the gradient directions that do not coincide with one of the 8 possible main directions, an interpolation is done to compute the neighboring gradients. 5. Threshold Calculation: Computing high and low thresholds based on the histogram of the gradient magnitude for the entire image. The high threshold is computed such that a percentage p1 of total pixel in the image would be classified as Strong edge. The high threshold corresponds to the point at which value of gradient magnitude is Cumulative distributive function (CDF) equals to 1- p1. The low threshold is calculated as percentage p2 of high threshold. 21

3 6. Hysteresis Threshold: It is used to determine the edge map. If the gradient magnitude of pixel is greater than high threshold then this pixel is considered as strong edge. If the gradient magnitude of pixel is between high and low threshold then this pixel is considered as weak edge. IV. PROPOSED DESIGN STRATEGY In proposed design strategy the following are the key contributions: i) Approximate methods for the computation of gradient magnitude and orientation. ii) Cumulative histogram based median filter architecture for sliding window. i. Image smoothing. Smoothing of image is achieved by Gaussian convolution. The image is first passed through low pass filter (LPF) to reduce the noise, i.e. all high frequency components are eliminated. A 3x3 moving window Gaussian operator is used; two FIFO buffers with the depth of one row pixels of image are employed to access all the pixels in the 3x3 window at the same time [6]. Consider a two dimensional image of size 128x128 as input and it is represented as I(x,y) in spatial domain. The pixel values are obtained as array of values and these values are stored in a text file. This text file data is used as input during the smoothing process. Size of the filter has to be chosen very carefully because, as the size of the filter increases filter becomes less sensitive to noise. Filtering mask is obtained by using the two dimensional Gaussian function,and the function is as follows Where x and y represents horizontal and vertical values of a two dimensional image, sigma is the standard deviation of the Gaussian function and G(x, y) represents the smoothened image. Sigma plays a major role in the selection of the coefficients of the Gaussian filter. ii. Gradient Unit Next step is the gradient calculation unit which is performed using gradient filter. The inputs to the gradient block are the output values of the smoothing unit. This step creates an additional 1-pixel border of invalid data around the input image. The calculation steps used in the algorithm uses Gx =I(x +1,y) - I(x -1,y) and Gy=I(x, y +1)- I(x, y -1) to calculate the horizontal gradient and vertical gradient respectively. Two different masks are used for calculating horizontal and vertical gradient of an image shown in table 3.1a and b respectively. Table 3.1: Convolution Kernels Using the masks mentioned above the gradient calculation is done using the following equations. Gx= (P2+P5+P8)/2 Gy= (P4+P5+P6)/2 iii. Magnitude Unit: The horizontal and vertical gradient values obtained in the gradient unit are the inputs to the magnitude block; these gradient values are used for finding the magnitude of the input image. Magnitude of the gradient is calculated using the formula Gmag =. iv. Non-Maximum Suppression [NMS]: The architecture of NMS block is shown in fig. 3. It consists of window 3x3 unit, selector unit, and arithmetic and comparator unit. Window 3 3 unit holds the 8 pixel values at a time and feeds the input to the selector unit and the middle value is given to the comparator unit. In the selector block angle is calculated at each pixel location simultaneously after the calculation of gradient of an image. Edge direction is taken by considering the inverse tangent function of vertical gradient to horizontal gradient. Ө = arctan (Gy/Gx). The angle Өg(x, y) is calculated using the gradients i.e. arc tan (gy/gx). Fig. 2: Block diagram of Non Maximal Suppression Unit v. Hysteresis thresholding: The architecture of pipelined thresholding is shown in fig. 3. The output of the non-maximum suppression unit contains some spurious edges. Hence the hysteresis thresholding is performed to reduce those effects. The threshold is calculated based on the gradient histogram i.e. we need the histogram of the 22

4 image after the NMS operation. In non-maximal suppression block the operation is performed to thin the edges as well as to detect all possible edges. To identify the true edges from output NMS image two thresholds are considered in this algorithm i.e. the high threshold and the low threshold. Verilog coding, hence the imageis converted to edged image as shown in Fig 6.The result shows that it utilizesless cost compared to the existing architectures due toapproximation method and sliding window technique forhistogram based median filter architecture. Fig. 3: Block diagram of pipelined thresholding Pipelined Architecture The architecture consists of 6 major blocks as shown in Fig. 1. The edge detection algorithm adopts 3x3 masks. In order to speed up the operation of the VLSI hardware a 3 stage pipelined architecture has been proposed for 4 blocks: Gradient computation in x and y direction, Magnitude and orientation computation, Non- Maximum Suppression, Bin for threshold calculation as shown in Fig. 4(a). In this design, each function requires one clock cycle. As shown in Fig. 13(b) to process the pixel covered by 3x3 mask requires 15 clock cycles instead of 36 clock cycles that helps to reduce the output latency. Thus the pipelined architecture increases the speed of operation and are implemented using Xilinx. (a) (b) Fig. 4.Pipelining Stages (a) VLSI architecturefor detecting edges (b) Clockused for processing the pixels. V. RESULTS The canny edge algorithm is coded in Verilog. And the simulated wave form using modelsim simulator is Fig 5: Simulation result using ModelSim Simulator. Fig 6: Results of Canny Edge Algorithm in Verilog. VI. CONCLUSION The proposed canny edge detector uses the pipeliningtechnique and handles the multiple blocks at the same time. Ithelps to achieve fastest working speed. By using theapproximation methods, the hardware cost is reduced. Thehistogram based median filter architecture uses slidingwindow technique and results in low hardware utilization. Theproposed algorithm is scalable and has high accuracy. REFERENCES [1] L. G. Roberts. Machine perception of 3D solids, Optical and Electro- Optical Information Processing. MIT Press, [2] J. F. Canny, A computation approach to edgedetection, IEEE Trans. Pattern Analysis and Machine Intelligence, vol. 8, no. 6, pp ,November [3] Chandrashekar N.S, Dr. K.R. Nataraj, ADistributed Canny Edge Detector and ItsImplementation on FPGA International Journal of Computational Engineering Research Vol. 2 Issue.7. Issn (online) November [4] Tejaswini h.r, vidhya n, swathi r varma,santhosh b, an implementation of real time optimaledge detector and vlsi architecture. International conference on electronics and communication shown in Fig 5. The matlab is interconnected with the 23

5 engineering, 28th april-2013, bengaluru, isbn: [5] Chaithra.N.M., K.V. Ramana Reddy Implementation of Canny Edge Detection Algorithm on FPGA and displaying Image through VGA Interface International Journal of Engineering and Advanced Technology (IJEAT) ISSN: , Volume-2, Issue-6, August 2013 [6] B.Muralikrishna, P.Sujitha, Habibulla Khan Real Time Edge Detection Modelling With FPGA International Journal of VLSI and Embedded Systems-IJVES, Vol 04, Article 06103; June 2013 [7] Qian Xu, Chaitali Chakrabarti and Lina J. Karam A Distributed Canny Edge Detector and Its Implementation On FPGA School of Electrical, Computer and Energy Engineering, Arizona State University, IEEE, 2011, pp [8]. Parvinder Singh Sandhu, Mamata Juneja and Ekta Walia Comparative Analysis of Edge Detectin Techniques for extracting Refined Boundaries 2009 International Conference on Machine Learning and Computing,IPCSIT vol 3, [9]. Wenhao He and Kui Yuan An Improved Canny Edge Detector and its Realization on FPGA IEEE Proceedings of the 7th World Congress on Intelligent Control and Automation, Chongqing, China, June 25-27, 2008, pp [10] Alasdair Mc Andrew. Introduction to Digital Image Processing with MATLAB. [11] Gao Jie and Liu Ning An improved adaptive threshold canny edge detection algorithm, IEEE International Conference on Computer Science and Electronics Engineering, 2012, pp [12] Enoch Hwang, Build a VGA Monitor Controller, Circuit Cellar, Issue 172, November 2004,pp [13] Rafael C. Gonzalez, Richard E. Woods. Digital Image Processing, Prentice Hall, 2nd edition (January 15, 2002). 24