CIRPART A FPGA BASED PROCESSOR FOR CIRCUIT MULTI-WAY PARTITIONING USING HYBRID GENETIC ALGORITHM
|
|
- Roberta Snow
- 6 years ago
- Views:
Transcription
1 CIRPART A FPGA BASED PROCESSOR FOR CIRCUIT MULTI-WAY PARTITIONING USING HYBRID GENETIC ALGORITHM S. Rajaram, Dhinesh Joseph Sukumar, S.V. Karthick, V. Abhai Kumar Department of Electronics and Communication, Thiagarajar College of Engineering, Madurai sdhineshjoseph_conf@rediffmail.com ABSTRACT This paper proposes CIRPART architecture for implementing Hybrid Genetic Algorithm (GA) used for circuit Multiway Partitioning in VLSI physical design automation. CIRPART applies Hybrid Genetic Algorithm to considerably reduce the number of generations required. CIRPART provides flexibility and also achieves speedups over software based GA. CIRPART achieves more than 100x improvement in processing speed as compared to the software implementation. 1. INTRODUCTION GAs are applied to Circuit Partitioning problems since GA is more global (i.e.,) search is done from a population and not a single point and also large number of points are handled in parallel [1]. The circuit-partitioning problem [2] can be formally represented in graph theoretic notation as a weighted graph, G = (V, E) with the components represented as nodes, v i Є V where V is the vertex set and the wires connecting them as edges, e ij = (v i,v j ) Є E where E is the edge-set. Let a i be the weight (area) of a vertex i, and c ij be the weight or cost of an edge e ij. Also given is the number of partitions k, and the capacity of each subset or partition, A 1, A 2,,A k. The output consists of disjoint subsets V 1, V 2,,V k such that U k n=1 V n = V, Vn, Σ υ i ЄVn a i <A n, and e ij such that [υ i ] [υ j ], C = Σc ij is minimized. V n = [υ i ] represents the subset containing υ i, and C is the cost of the cut. The set of edges cut by the partition, e ij, [υ i ] = [υ j ] is called the cut set. Using Sterling s approximation [3], N k = O((n/p) (n-n/p) ). 2. PREVIOUS WORK Numerous optimization techniques have been applied to solve the graph and circuit partitioning problems [4,5,6,7,8,9]. GAs, which exhibit intrinsic parallelism provide even better solutions. Hybrid GAs [10] still speeds up the process. The use of reconfigurable hardware for the design of GA was seen in projects such as [11, 12, 13, 14, 15, 16, 17]. In the current work, all the research done in hardware implementation of GA is combined to create a system, which attempts to achieve significant speedup over software GA due to pipelining and parallelization. It also attempts to minimize the logic resources used within FPGA. It applies Hybrid Genetic Algorithm to perform local optimization in every generation. This results in faster convergence and hence the number of generations is considerably reduced. 3. NEED FOR HARDWARE REALIZATION OF GENETIC ALGORITHM Reconfigurability is essential in a generalpurpose GA engine because certain GA modules require changeability). Thus a hardware-based GA is both feasible and desirable. Work by Spears and De Jong [18] indicates that for NP-complete problems, m=100 and g=100 may be necessary to obtain a good result and avoid premature convergence to a local optimum. Because a general-purpose GA engine requires certain parts of its design to
2 be easily changed, a hardware-based Genetic Algorithm (HGA) was not feasible until Field Programmable Gate Arrays (FPGAs) [19] were developed. Reprogrammable FPGAs (those programmed via a bit patterns stored in a static RAM) are essential to the development of the HGA system. 4. SYSTEM ARCHITECTURE CIRPART is specifically optimized towards solving the circuit Multiway Partitioning. CIRPART uses a processing-pipeline for performing the computationally intensive parts of the partitioning algorithm. The block diagram of the GA processor is shown in Figure 1. The design is coded in VHDL and uses the generics shown in Table 1. The external RAM modules used by the design are listed in Table 2. The chromosome representation is depicted in Figure 2. The various registers used are listed in the table 3. The GA Processor consists of the following modules Fitness Evaluation Module (FEM) Once GOM generates a complete new population FEM generates fitness values for each of the generated chromosomes. Upon receiving the active high Start_Eval signal from CPM, FEM determines for each chromosome, the Partition-imbalance Cost and the Net-cut Cost simultaneously Parent Selection Module (PSM) PSM performs Tournament selection on the population by reading four random fitnesses from the Fitness memory upon receiving an active high START_SEL signal from the Main Controller. At the end of selection of two parents, PSM generates a signal, indicating end of selection Genetic Operation Module (GOM) GOM performs the crossover and mutation operations on the two parent chromosomes, the starting addresses of which are generated by PSM. The Population memory is divided into two address spaces, namely the low bank, and the high bank. At any time, the parent population is stored into one of the banks and the child population generated by GOM is stored into the other bank. Upon receiving an active high START_MAT signal from CPM, the chromosome for each of the parents is read from the Population memory based upon the addresses generated by PSM. The Crossover template is shown in Figure 3. Figure 4 describes the input status of both the multiplexer banks corresponding to different offsprings. Mutation is performed with a very small probability P m Central Processing Module (CPM) CPM generates control signals for rest of the blocks of the design. The state diagram of CPM is shown in figure 5. The various states of CPM are quoted below, S1 (000): CPM starts reading the various inputs using the input handshake signals. S2 (001): After loading the netlist into the Netlist memory, CPM generates random chromosomes and initializes the Population memory with random population. S3 (010): CPM evaluates the fitness of each individual in the population by enabling FEM. S4 (011): CPM selects the parents based on the fitness value by enabling PSM. S5 (100): CPM generates new population by enabling GOM. 5. EXPERIMENTAL RESULTS The GA was implemented in the C++ programming language on a Pentium III (800 MHz) machine with 128 MB memory. The proposed architecture CIRPART for Multiway Partitioning was implemented in Virtex V100CS144 chip through VHDL. The architecture was tested for structural and physical functionalities and proved to be satisfactory. The performance results for Hardware GA and Software GA are compared and tabulated in Tables 4 and 5 (default values for no. of generation, G N and population size, C N being 20).
3 6. CONCLUSION In this paper, CIRPART - a new architecture for implementing the Hybrid GA in hardware is proposed. Although the architecture is designed specifically to solve the Circuit Multi-way Partitioning problem, some of the modules in the design can be re-used for other problems as well. There are many ways to extend the proposed design by simple modifications to the VHDL code. This design was used to solve multi-way circuit partitioning problem with Tournament Selection and Uniform crossover. Other GA operators could be implemented as well. Alternate chromosome representations can be explored in order to reduce the memory requirements. 7. REFERENCES [1] D.E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Addison-Welsey Publishing Company, Reading,Massachusetts, [2] S. Areibi, "A Review of Circuit Partitioning", Technical report, School of Engineering, University of Guelph, June [3] G. A. Korn and T. M. Korn, Mathematical Handbook for Scientists and Engineers, New York: McGraw-Hill Book Company, Inc., [4] U. R. Kodres, Partitioning and Card Selection, in Design Automation of Digital Systems, M. A. Breuer, ed., pp , [5] B. W. Kernighan and S. Lin, An Efficient Heuristic Procedure for Partitioning Graphs, Bell Systems Technical Journal, vol. 49, pp , [6] C. M. Fiduccia and R. M. Mattheyses, A Linear-time heuristic for improving network partitions, Proc. Design Automation Conf., pp , [7] B. Krishnamurthy, An Improved min-cut algorithm for partitioning VLSI networks, IEEE Trans. Computers, vol. c-33, pp , [8] S. Dutta and W. Deng, A Probabilitybased approach to VLSI circuit partitioning, Proc. Design Automation Conf., pp , [9] S. Kirkpatrick, C. D. Gelatt, Jr., and M. P. Vecchi, Optimization by Simulated Annealing, Science, vol. 220, no.4598, pp , May [10] T.N. Bui, and B.R. Moon, A Fast and stable hybrid genetic algorithm for the ratio-cut partitioning problem on hypergraphs, Proc. ACM/IEEE Design Automation Conf., pp , June [11] Stephen Donald Scott, "A hardware based genetic algorithm", Master's thesis, University of Nebraska, August [12] Tommi Rintala, "Hardware implementation of GA", September [13] Loring Wirbel, "Compression chip is first to use genetic algorithms", page 17, December [14] PaulGraham and Brent Nelson, "A Hardware Genetic Algorithm for the Travelling Salesman Problem on Splash2", [15] PaulGraham and Brent Nelson, "Genetic Algorithms in Software and in Hardware- A performance Analysis of workstation and custom Computing Machine Implementation", in IEEE Symposium on FPGAs for custom Computing Machines, pp , Reconfigurable Logic Laboratory, Brigham Young University, Provo, UT, USA, [16] John R. Koza, Forrest h Bennett III, Stephen L Jeffrey L, Martin A and David Andre, "Evolving Computer Programs using Rapidly Reconfigurable Field Programmable Gate Arrays and Genetic Programming", [17] Chatchawit and Prabhas, "A Hardware Implementation of compace Genetic algorithm", in Proceedings of the 2001 IEEE Congress on Evolutionary Computation, pp , Seoul, Korea, May [18] K.A. De Jong and W.M. Spears, "Using genetic algorithms to solve NP-complete problems", in J.David Schaffer, editor, Proceedings of the Third International Conference on Genetic Algorithms, pp Morgan Kaufmann Publishers, [19] S.D. Brown, R.J. Francis, J. Rose and Z.G. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, USA, 1992.
4 BUS NAME AB1 DB1 AB2 DB2 AB3 DB3 AB4 DB4 DESCRIPTION Address Bus of Central Processing Module Data Bus of Central Processing Module Address Bus of Fitness Evaluation Module Data Bus of Fitness Evaluation Module Address Bus of Parent Selection Module Data Bus of Parent Selection Module Address Bus of Genetic Operation Module Data Bus of Genetic Operation Module Figure 1: Architecture for the Genetic Algorithm Processor Figure 2: Chromosome Representation of Circuit-multiway-Partitioning
5 RNG Random Number Generator *OA(i) i th bit content of First Offspring PA(i) i th bit content of First Parent OB(i) i th bit content of Second Offspring PB(i) i th bit content of Second Parent O(i) i th bit content of Offspring (in general) Figure 3: Crossover Template Figure 4: Multiplexer Inputs INPUT SIGNAL SIGNIFICANCE 000 StartGA Starts the GA Process. 001 StartInit Initializes the Population memory with random population. 010 StartEval Enables the Fitness Evaluation Module. 011 StartSel Enables the Parent Selection Module. 100 StartMat Enables the Genetic Operation Module. OUTPUT SIGNAL SIGNIFICANCE 000 Ready Indicates the successful reception of all inputs. 001 InitComp Indicates the completion of random initial population generation in the Population memory. 010 EvalComp Indicates the completion of the Fitness Evaluation Process. 011 SelComp Indicates the completion of the Parent Selection Process. 100 MatComp Indicates the completion of the Mating Process. 101 GAComp Indicates the completion of the GA Process. This happens at the end of the last generation. Figure 5: State machine of Central Processing module. S.No GENRIC NAME DESCRIPTION 1 FMAddrWidth Fitness memory address width. This gives two times maximum size supported. 2 FMDataWidth Fitness memory data width. 3 IMAddrWidth Input memory address width. This gives two times maximum size supported. 4 IMDataWidth Input memory data width. This represents word size of Input memory. 5 Chromosome_Length Number of bits used to represent the chromosome. Table 1: Generics used in the design
6 S.No MEMORY DESCRIPTION 1 Input Memory It stores the netlist in a modified form. For each net, the words corresponding to the modules that are connected via that particular newt, are made All 1 s and the rest of the words are made All 0 s. It stores the areas of the modules. It stores Population size, Number of Generations required, Number of Partitions required, Number of modules, Number of nets, Crossover rate and Mutation Rate. This is single address port synchronous RAM. 2 Population Memory It stores population elements for the parent as well as child population. The address space is divided into two halves. Each half stores either parent or child population. This is dual address port synchronous RAM. 3 Fitness Memory It stores fitness of parent and child population. This is also divided into two parts for storing parent and child population. This is single address port synchronous RAM. Table 2: Core Memories REGISTER SIZE (bits) DESCRIPTION Crossover_Rate 32 Crossover rate Mutation_Rate 32 Mutation rate Word_Count 16 Number of the word in a particular chromosome that is currently in process. Net_Count 16 Number of the net currently in process Chromosome_Count 8 Number of the chromosome currently in process Ref_Worst_Cost 32 Reference Worst Cost Table 3: Control Registers CIRCUIT #MODULES #NETS SOFTWARE HARDWARE G N=20 G N=60 G N=100 G N=20 G N=60 G N=100 Fract Struct Primary Ckt Ckt Ckt Ckt Ckt Ckt Ckt Ckt Table 4: Performance results for Hardware GA and Software GA for different Generation Count. CIRCUIT #MODULES #NETS SOFTWARE HARDWARE C N=20 C N=60 C N=100 C N=20 C N=60 C N=100 Fract Struct Primary Ckt Ckt Ckt Ckt Ckt Ckt Ckt Ckt Table 5: Performance results for Hardware GA and Software GA for different Chromosome Count.
Genetic Algorithm for Circuit Partitioning
Genetic Algorithm for Circuit Partitioning ZOLTAN BARUCH, OCTAVIAN CREŢ, KALMAN PUSZTAI Computer Science Department, Technical University of Cluj-Napoca, 26, Bariţiu St., 3400 Cluj-Napoca, Romania {Zoltan.Baruch,
More informationCAD Algorithms. Circuit Partitioning
CAD Algorithms Partitioning Mohammad Tehranipoor ECE Department 13 October 2008 1 Circuit Partitioning Partitioning: The process of decomposing a circuit/system into smaller subcircuits/subsystems, which
More informationGenetic Algorithm for FPGA Placement
Genetic Algorithm for FPGA Placement Zoltan Baruch, Octavian Creţ, and Horia Giurgiu Computer Science Department, Technical University of Cluj-Napoca, 26, Bariţiu St., 3400 Cluj-Napoca, Romania {Zoltan.Baruch,
More informationIMPROVEMENT OF THE QUALITY OF VLSI CIRCUIT PARTITIONING PROBLEM USING GENETIC ALGORITHM
Volume 3, No. 12, December 2012 Journal of Global Research in Computer Science RESEARCH PAPER Available Online at www.jgrcs.info IMPROVEMENT OF THE QUALITY OF VLSI CIRCUIT PARTITIONING PROBLEM USING GENETIC
More informationAdaptive Crossover in Genetic Algorithms Using Statistics Mechanism
in Artificial Life VIII, Standish, Abbass, Bedau (eds)(mit Press) 2002. pp 182 185 1 Adaptive Crossover in Genetic Algorithms Using Statistics Mechanism Shengxiang Yang Department of Mathematics and Computer
More informationA Simple Efficient Circuit Partitioning by Genetic Algorithm
272 A Simple Efficient Circuit Partitioning by Genetic Algorithm Akash deep 1, Baljit Singh 2, Arjan Singh 3, and Jatinder Singh 4 BBSB Engineering College, Fatehgarh Sahib-140407, Punjab, India Summary
More informationUnit 5A: Circuit Partitioning
Course contents: Unit 5A: Circuit Partitioning Kernighang-Lin partitioning heuristic Fiduccia-Mattheyses heuristic Simulated annealing based partitioning algorithm Readings Chapter 7.5 Unit 5A 1 Course
More informationImplementation of Genetic Algorithm Using FPGA with Applications
IJE, VOL.9, NO.1, 009 Abstract Dr. Hanan A. R. Akkar * & Omar Arif Abdul-Rahman * Received on: 1/1/008 Accepted on: 10/6/009 This paper presents a design of a general purpose GA. It is described using
More informationA Modified Genetic Algorithm for Process Scheduling in Distributed System
A Modified Genetic Algorithm for Process Scheduling in Distributed System Vinay Harsora B.V.M. Engineering College Charatar Vidya Mandal Vallabh Vidyanagar, India Dr.Apurva Shah G.H.Patel College of Engineering
More informationPlacement Algorithm for FPGA Circuits
Placement Algorithm for FPGA Circuits ZOLTAN BARUCH, OCTAVIAN CREŢ, KALMAN PUSZTAI Computer Science Department, Technical University of Cluj-Napoca, 26, Bariţiu St., 3400 Cluj-Napoca, Romania {Zoltan.Baruch,
More informationA COMPARATIVE STUDY OF FIVE PARALLEL GENETIC ALGORITHMS USING THE TRAVELING SALESMAN PROBLEM
A COMPARATIVE STUDY OF FIVE PARALLEL GENETIC ALGORITHMS USING THE TRAVELING SALESMAN PROBLEM Lee Wang, Anthony A. Maciejewski, Howard Jay Siegel, and Vwani P. Roychowdhury * Microsoft Corporation Parallel
More informationCOMPARATIVE STUDY OF CIRCUIT PARTITIONING ALGORITHMS
COMPARATIVE STUDY OF CIRCUIT PARTITIONING ALGORITHMS Zoltan Baruch 1, Octavian Creţ 2, Kalman Pusztai 3 1 PhD, Lecturer, Technical University of Cluj-Napoca, Romania 2 Assistant, Technical University of
More informationResearch Article Accounting for Recent Changes of Gain in Dealing with Ties in Iterative Methods for Circuit Partitioning
Discrete Dynamics in Nature and Society Volume 25, Article ID 625, 8 pages http://dxdoiorg/55/25/625 Research Article Accounting for Recent Changes of Gain in Dealing with Ties in Iterative Methods for
More informationA Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time
A Real Coded Genetic Algorithm for Data Partitioning and Scheduling in Networks with Arbitrary Processor Release Time S. Suresh 1, V. Mani 1, S. N. Omkar 1, and H. J. Kim 2 1 Department of Aerospace Engineering,
More informationHigh-speed FPGA-based Implementations of a Genetic Algorithm
High-speed FPGA-based Implementations of a Genetic Algorithm Michalis Vavouras Kyprianos Papadimitriou Ioannis Papaefstathiou Department of Electronic and Computer Engineering Technical University of Crete
More informationUsing Genetic Algorithm with Triple Crossover to Solve Travelling Salesman Problem
Proc. 1 st International Conference on Machine Learning and Data Engineering (icmlde2017) 20-22 Nov 2017, Sydney, Australia ISBN: 978-0-6480147-3-7 Using Genetic Algorithm with Triple Crossover to Solve
More informationPartitioning. Course contents: Readings. Kernighang-Lin partitioning heuristic Fiduccia-Mattheyses heuristic. Chapter 7.5.
Course contents: Partitioning Kernighang-Lin partitioning heuristic Fiduccia-Mattheyses heuristic Readings Chapter 7.5 Partitioning 1 Basic Definitions Cell: a logic block used to build larger circuits.
More informationCHAPTER 1 at a glance
CHAPTER 1 at a glance Introduction to Genetic Algorithms (GAs) GA terminology Genetic operators Crossover Mutation Inversion EDA problems solved by GAs 1 Chapter 1 INTRODUCTION The Genetic Algorithm (GA)
More informationEscaping Local Optima: Genetic Algorithm
Artificial Intelligence Escaping Local Optima: Genetic Algorithm Dae-Won Kim School of Computer Science & Engineering Chung-Ang University We re trying to escape local optima To achieve this, we have learned
More informationIntroduction. A very important step in physical design cycle. It is the process of arranging a set of modules on the layout surface.
Placement Introduction A very important step in physical design cycle. A poor placement requires larger area. Also results in performance degradation. It is the process of arranging a set of modules on
More informationJob Shop Scheduling Problem (JSSP) Genetic Algorithms Critical Block and DG distance Neighbourhood Search
A JOB-SHOP SCHEDULING PROBLEM (JSSP) USING GENETIC ALGORITHM (GA) Mahanim Omar, Adam Baharum, Yahya Abu Hasan School of Mathematical Sciences, Universiti Sains Malaysia 11800 Penang, Malaysia Tel: (+)
More informationSolving ISP Problem by Using Genetic Algorithm
International Journal of Basic & Applied Sciences IJBAS-IJNS Vol:09 No:10 55 Solving ISP Problem by Using Genetic Algorithm Fozia Hanif Khan 1, Nasiruddin Khan 2, Syed Inayatulla 3, And Shaikh Tajuddin
More informationGenetic Algorithm Performance with Different Selection Methods in Solving Multi-Objective Network Design Problem
etic Algorithm Performance with Different Selection Methods in Solving Multi-Objective Network Design Problem R. O. Oladele Department of Computer Science University of Ilorin P.M.B. 1515, Ilorin, NIGERIA
More informationProceedings of the First IEEE Conference on Evolutionary Computation - IEEE World Congress on Computational Intelligence, June
Proceedings of the First IEEE Conference on Evolutionary Computation - IEEE World Congress on Computational Intelligence, June 26-July 2, 1994, Orlando, Florida, pp. 829-833. Dynamic Scheduling of Computer
More informationThe Simple Genetic Algorithm Performance: A Comparative Study on the Operators Combination
INFOCOMP 20 : The First International Conference on Advanced Communications and Computation The Simple Genetic Algorithm Performance: A Comparative Study on the Operators Combination Delmar Broglio Carvalho,
More informationGenetic Algorithm for Dynamic Capacitated Minimum Spanning Tree
28 Genetic Algorithm for Dynamic Capacitated Minimum Spanning Tree 1 Tanu Gupta, 2 Anil Kumar 1 Research Scholar, IFTM, University, Moradabad, India. 2 Sr. Lecturer, KIMT, Moradabad, India. Abstract Many
More informationGenetic Algorithms For Vertex. Splitting in DAGs 1
Genetic Algorithms For Vertex Splitting in DAGs 1 Matthias Mayer 2 and Fikret Ercal 3 CSC-93-02 Fri Jan 29 1993 Department of Computer Science University of Missouri-Rolla Rolla, MO 65401, U.S.A. (314)
More informationGenetic Algorithm for Finding Shortest Path in a Network
Intern. J. Fuzzy Mathematical Archive Vol. 2, 2013, 43-48 ISSN: 2320 3242 (P), 2320 3250 (online) Published on 26 August 2013 www.researchmathsci.org International Journal of Genetic Algorithm for Finding
More informationImplementation of Multi-Way Partitioning Algorithm
Implementation of Multi-Way Partitioning Algorithm Kulpreet S. Sikand, Sandeep S. Gill, R. Chandel, and A. Chandel Abstract This paper presents a discussion of methods to solve partitioning problems and
More informationA Hybrid Genetic Algorithm for the Hexagonal Tortoise Problem
A Hybrid Genetic Algorithm for the Hexagonal Tortoise Problem Heemahn Choe, Sung-Soon Choi, and Byung-Ro Moon School of Computer Science and Engineering, Seoul National University, Seoul, 141-742 Korea
More informationInvestigation of the Fitness Landscapes and Multi-parent Crossover for Graph Bipartitioning
Investigation of the Fitness Landscapes and Multi-parent Crossover for Graph Bipartitioning Yong-Hyuk Kim and Byung-Ro Moon School of Computer Science & Engineering, Seoul National University Shillim-dong,
More informationThe study of comparisons of three crossover operators in genetic algorithm for solving single machine scheduling problem. Quan OuYang, Hongyun XU a*
International Conference on Manufacturing Science and Engineering (ICMSE 2015) The study of comparisons of three crossover operators in genetic algorithm for solving single machine scheduling problem Quan
More informationMulti-Attractor Gene Reordering for Graph Bisection
Multi-Attractor Gene Reordering for Graph Bisection Inwook Hwang School of Computer Science & Engineering Seoul National University Sillim-dong, Gwanak-gu, Seoul, 11-744 Korea hwang@soar.snu.ac.kr Yong-Hyuk
More informationEfficient FM Algorithm for VLSI Circuit Partitioning
Efficient FM Algorithm for VLSI Circuit Partitioning M.RAJESH #1, R.MANIKANDAN #2 #1 School Of Comuting, Sastra University, Thanjavur-613401. #2 Senior Assistant Professer, School Of Comuting, Sastra University,
More informationDETERMINING MAXIMUM/MINIMUM VALUES FOR TWO- DIMENTIONAL MATHMATICLE FUNCTIONS USING RANDOM CREOSSOVER TECHNIQUES
DETERMINING MAXIMUM/MINIMUM VALUES FOR TWO- DIMENTIONAL MATHMATICLE FUNCTIONS USING RANDOM CREOSSOVER TECHNIQUES SHIHADEH ALQRAINY. Department of Software Engineering, Albalqa Applied University. E-mail:
More informationAn Evolutionary Algorithm with Stochastic Hill-Climbing for the Edge-Biconnectivity Augmentation Problem
An Evolutionary Algorithm with Stochastic Hill-Climbing for the Edge-Biconnectivity Augmentation Problem Ivana Ljubić and Günther R. Raidl Institute for Computer Graphics and Algorithms, Vienna University
More informationUsing Genetic Algorithms to optimize ACS-TSP
Using Genetic Algorithms to optimize ACS-TSP Marcin L. Pilat and Tony White School of Computer Science, Carleton University, 1125 Colonel By Drive, Ottawa, ON, K1S 5B6, Canada {mpilat,arpwhite}@scs.carleton.ca
More informationFour Methods for Maintenance Scheduling
Four Methods for Maintenance Scheduling Edmund K. Burke, University of Nottingham, ekb@cs.nott.ac.uk John A. Clark, University of York, jac@minster.york.ac.uk Alistair J. Smith, University of Nottingham,
More informationCombinational Circuit Design Using Genetic Algorithms
Combinational Circuit Design Using Genetic Algorithms Nithyananthan K Bannari Amman institute of technology M.E.Embedded systems, Anna University E-mail:nithyananthan.babu@gmail.com Abstract - In the paper
More informationA Modified Genetic Algorithm for Task Scheduling in Multiprocessor Systems
A Modified Genetic Algorithm for Task Scheduling in Multiprocessor Systems Yi-Hsuan Lee and Cheng Chen Department of Computer Science and Information Engineering National Chiao Tung University, Hsinchu,
More informationResearch Incubator: Combinatorial Optimization. Dr. Lixin Tao December 9, 2003
Research Incubator: Combinatorial Optimization Dr. Lixin Tao December 9, 23 Content General Nature of Research on Combinatorial Optimization Problem Identification and Abstraction Problem Properties and
More informationVLSI Physical Design: From Graph Partitioning to Timing Closure
Chapter Netlist and System Partitioning Original Authors: Andrew B. Kahng, Jens, Igor L. Markov, Jin Hu Chapter Netlist and System Partitioning. Introduction. Terminology. Optimization Goals. Partitioning
More informationPATH PLANNING OF ROBOT IN STATIC ENVIRONMENT USING GENETIC ALGORITHM (GA) TECHNIQUE
PATH PLANNING OF ROBOT IN STATIC ENVIRONMENT USING GENETIC ALGORITHM (GA) TECHNIQUE Waghoo Parvez 1, Sonal Dhar 2 1 Department of Mechanical Engg, Mumbai University, MHSSCOE, Mumbai, India 2 Department
More informationInternational Journal of Digital Application & Contemporary research Website: (Volume 1, Issue 7, February 2013)
Performance Analysis of GA and PSO over Economic Load Dispatch Problem Sakshi Rajpoot sakshirajpoot1988@gmail.com Dr. Sandeep Bhongade sandeepbhongade@rediffmail.com Abstract Economic Load dispatch problem
More informationAcyclic Multi-Way Partitioning of Boolean Networks
Acyclic Multi-Way Partitioning of Boolean Networks Jason Cong, Zheng Li, and Rajive Bagrodia Department of Computer Science University of California, Los Angeles, CA 90024 Abstract Acyclic partitioning
More informationCIRCUIT PARTITIONING is a fundamental problem in
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 15, NO. 12, DECEMBER 1996 1533 Efficient Network Flow Based Min-Cut Balanced Partitioning Hannah Honghua Yang and D.
More informationSuppose you have a problem You don t know how to solve it What can you do? Can you use a computer to somehow find a solution for you?
Gurjit Randhawa Suppose you have a problem You don t know how to solve it What can you do? Can you use a computer to somehow find a solution for you? This would be nice! Can it be done? A blind generate
More informationCHAPTER 4 GENETIC ALGORITHM
69 CHAPTER 4 GENETIC ALGORITHM 4.1 INTRODUCTION Genetic Algorithms (GAs) were first proposed by John Holland (Holland 1975) whose ideas were applied and expanded on by Goldberg (Goldberg 1989). GAs is
More informationK partitioning of Signed or Weighted Bipartite Graphs
K partitioning of Signed or Weighted Bipartite Graphs Nurettin B. Omeroglu, Ismail H. Toroslu Middle East Technical University, Dep. of Computer Engineering, Ankara, Turkey {omeroglu, toroslu}@ceng.metu.edu.tr
More informationFuzzy Inspired Hybrid Genetic Approach to Optimize Travelling Salesman Problem
Fuzzy Inspired Hybrid Genetic Approach to Optimize Travelling Salesman Problem Bindu Student, JMIT Radaur binduaahuja@gmail.com Mrs. Pinki Tanwar Asstt. Prof, CSE, JMIT Radaur pinki.tanwar@gmail.com Abstract
More informationUsing Evolutionary Computation to explore geometry and topology without ground structures
Proceedings of the 6th International Conference on Computation of Shell and Spatial Structures IASS-IACM 2008: Spanning Nano to Mega 28-31 May 2008, Cornell University, Ithaca, NY, USA John F. ABEL and
More informationA HYBRID APPROACH IN GENETIC ALGORITHM: COEVOLUTION OF THREE VECTOR SOLUTION ENCODING. A CASE-STUDY
A HYBRID APPROACH IN GENETIC ALGORITHM: COEVOLUTION OF THREE VECTOR SOLUTION ENCODING. A CASE-STUDY Dmitriy BORODIN, Victor GORELIK, Wim DE BRUYN and Bert VAN VRECKEM University College Ghent, Ghent, Belgium
More informationSolving A Nonlinear Side Constrained Transportation Problem. by Using Spanning Tree-based Genetic Algorithm. with Fuzzy Logic Controller
Solving A Nonlinear Side Constrained Transportation Problem by Using Spanning Tree-based Genetic Algorithm with Fuzzy Logic Controller Yasuhiro Tsujimura *, Mitsuo Gen ** and Admi Syarif **,*** * Department
More informationOptimal Reactive Power Dispatch Using Hybrid Loop-Genetic Based Algorithm
Optimal Reactive Power Dispatch Using Hybrid Loop-Genetic Based Algorithm Md Sajjad Alam Student Department of Electrical Engineering National Institute of Technology, Patna Patna-800005, Bihar, India
More informationConstraint-Driven Floorplanning based on Genetic Algorithm
Proceedings of the 2007 WSEAS International Conference on Computer Engineering and Applications, Gold Coast, Australia, January 17-19, 2007 147 Constraint-Driven Floorplanning based on Genetic Algorithm
More informationABSTRACT I. INTRODUCTION. J Kanimozhi *, R Subramanian Department of Computer Science, Pondicherry University, Puducherry, Tamil Nadu, India
ABSTRACT 2018 IJSRSET Volume 4 Issue 4 Print ISSN: 2395-1990 Online ISSN : 2394-4099 Themed Section : Engineering and Technology Travelling Salesman Problem Solved using Genetic Algorithm Combined Data
More informationSolving the Travelling Salesman Problem in Parallel by Genetic Algorithm on Multicomputer Cluster
Solving the Travelling Salesman Problem in Parallel by Genetic Algorithm on Multicomputer Cluster Plamenka Borovska Abstract: The paper investigates the efficiency of the parallel computation of the travelling
More informationARTIFICIAL INTELLIGENCE (CSCU9YE ) LECTURE 5: EVOLUTIONARY ALGORITHMS
ARTIFICIAL INTELLIGENCE (CSCU9YE ) LECTURE 5: EVOLUTIONARY ALGORITHMS Gabriela Ochoa http://www.cs.stir.ac.uk/~goc/ OUTLINE Optimisation problems Optimisation & search Two Examples The knapsack problem
More informationAn Integrated Genetic Algorithm with Clone Operator
International Journal of Pure and Applied Mathematical Sciences. ISSN 0972-9828 Volume 9, Number 2 (2016), pp. 145-164 Research India Publications http://www.ripublication.com An Integrated Genetic Algorithm
More informationAn Adaptive Hardware Classifier in FPGA based-on a Cellular Compact Genetic Algorithm and Block-based Neural Network
An Adaptive Hardware Classifier in FPGA based-on a Cellular Compact Genetic Algorithm and Block-based Neural Network Yutana Jewajinda National Electronics and Computer Technology Center National Science
More informationPlace and Route for FPGAs
Place and Route for FPGAs 1 FPGA CAD Flow Circuit description (VHDL, schematic,...) Synthesize to logic blocks Place logic blocks in FPGA Physical design Route connections between logic blocks FPGA programming
More informationGenetic Algorithm for Dynamic Capacitated Minimum Spanning Tree
Genetic Algorithm for Dynamic Capacitated Minimum Spanning Tree Rahul Mathur M.Tech (Purs.) BU, AJMER IMRAN KHAN Assistant Professor AIT, Ajmer VIKAS CHOUDHARY Assistant Professor AIT, Ajmer ABSTRACT:-Many
More informationOptimizing the Sailing Route for Fixed Groundfish Survey Stations
International Council for the Exploration of the Sea CM 1996/D:17 Optimizing the Sailing Route for Fixed Groundfish Survey Stations Magnus Thor Jonsson Thomas Philip Runarsson Björn Ævar Steinarsson Presented
More informationTHE Multiconstrained 0 1 Knapsack Problem (MKP) is
An Improved Genetic Algorithm for the Multiconstrained 0 1 Knapsack Problem Günther R. Raidl Abstract This paper presents an improved hybrid Genetic Algorithm (GA) for solving the Multiconstrained 0 1
More informationEncoding Techniques in Genetic Algorithms
Encoding Techniques in Genetic Algorithms Debasis Samanta Indian Institute of Technology Kharagpur dsamanta@iitkgp.ac.in 01.03.2016 Debasis Samanta (IIT Kharagpur) Soft Computing Applications 01.03.2016
More informationEvolutionary Computation Algorithms for Cryptanalysis: A Study
Evolutionary Computation Algorithms for Cryptanalysis: A Study Poonam Garg Information Technology and Management Dept. Institute of Management Technology Ghaziabad, India pgarg@imt.edu Abstract The cryptanalysis
More informationPLACEMENT OF TSVS IN THREE DIMENSIONAL INTEGRATED CIRCUITS (3D IC) College of Engineering, Madurai, India.
Volume 117 No. 16 2017, 179-184 ISSN: 1311-8080 (printed version); ISSN: 1314-3395 (on-line version) url: http://www.ijpam.eu ijpam.eu PLACEMENT OF TSVS IN THREE DIMENSIONAL INTEGRATED CIRCUITS (3D IC)
More informationMeta- Heuristic based Optimization Algorithms: A Comparative Study of Genetic Algorithm and Particle Swarm Optimization
2017 2 nd International Electrical Engineering Conference (IEEC 2017) May. 19 th -20 th, 2017 at IEP Centre, Karachi, Pakistan Meta- Heuristic based Optimization Algorithms: A Comparative Study of Genetic
More informationAutomatic Creation of Digital Fast Adder Circuits by Means of Genetic Programming
1 Automatic Creation of Digital Fast Adder Circuits by Means of Genetic Programming Karim Nassar Lockheed Martin Missiles and Space 1111 Lockheed Martin Way Sunnyvale, CA 94089 Karim.Nassar@lmco.com 408-742-9915
More informationNetwork Routing Protocol using Genetic Algorithms
International Journal of Electrical & Computer Sciences IJECS-IJENS Vol:0 No:02 40 Network Routing Protocol using Genetic Algorithms Gihan Nagib and Wahied G. Ali Abstract This paper aims to develop a
More informationGENERATIONAL MODEL GENETIC ALGORITHM FOR REAL WORLD SET PARTITIONING PROBLEMS
International Journal of Electronic Commerce Studies Vol.4, No.1, pp. 33-46, 2013 doi: 10.7903/ijecs.1138 GENERATIONAL MODEL GENETIC ALGORITHM FOR REAL WORLD SET PARTITIONING PROBLEMS Chi-san Althon Lin
More informationGENETIC ALGORITHM BASED FPGA PLACEMENT ON GPU SUNDAR SRINIVASAN SENTHILKUMAR T. R.
GENETIC ALGORITHM BASED FPGA PLACEMENT ON GPU SUNDAR SRINIVASAN SENTHILKUMAR T R FPGA PLACEMENT PROBLEM Input A technology mapped netlist of Configurable Logic Blocks (CLB) realizing a given circuit Output
More informationSIMULATED ANNEALING TECHNIQUES AND OVERVIEW. Daniel Kitchener Young Scholars Program Florida State University Tallahassee, Florida, USA
SIMULATED ANNEALING TECHNIQUES AND OVERVIEW Daniel Kitchener Young Scholars Program Florida State University Tallahassee, Florida, USA 1. INTRODUCTION Simulated annealing is a global optimization algorithm
More informationGraph and Hypergraph Partitioning for Parallel Computing
Graph and Hypergraph Partitioning for Parallel Computing Edmond Chow School of Computational Science and Engineering Georgia Institute of Technology June 29, 2016 Graph and hypergraph partitioning References:
More informationISSN: [Keswani* et al., 7(1): January, 2018] Impact Factor: 4.116
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY AUTOMATIC TEST CASE GENERATION FOR PERFORMANCE ENHANCEMENT OF SOFTWARE THROUGH GENETIC ALGORITHM AND RANDOM TESTING Bright Keswani,
More informationA Genetic Algorithm for Graph Matching using Graph Node Characteristics 1 2
Chapter 5 A Genetic Algorithm for Graph Matching using Graph Node Characteristics 1 2 Graph Matching has attracted the exploration of applying new computing paradigms because of the large number of applications
More information저작권법에따른이용자의권리는위의내용에의하여영향을받지않습니다.
저작자표시 - 동일조건변경허락 2.0 대한민국 이용자는아래의조건을따르는경우에한하여자유롭게 이저작물을복제, 배포, 전송, 전시, 공연및방송할수있습니다. 이차적저작물을작성할수있습니다. 이저작물을영리목적으로이용할수있습니다. 다음과같은조건을따라야합니다 : 저작자표시. 귀하는원저작자를표시하여야합니다. 동일조건변경허락. 귀하가이저작물을개작, 변형또는가공했을경우에는, 이저작물과동일한이용허락조건하에서만배포할수있습니다.
More informationA Recursive Coalescing Method for Bisecting Graphs
A Recursive Coalescing Method for Bisecting Graphs The Harvard community has made this article openly available. Please share how this access benefits you. Your story matters. Citation Accessed Citable
More informationAN IMPROVED ITERATIVE METHOD FOR SOLVING GENERAL SYSTEM OF EQUATIONS VIA GENETIC ALGORITHMS
AN IMPROVED ITERATIVE METHOD FOR SOLVING GENERAL SYSTEM OF EQUATIONS VIA GENETIC ALGORITHMS Seyed Abolfazl Shahzadehfazeli 1, Zainab Haji Abootorabi,3 1 Parallel Processing Laboratory, Yazd University,
More informationMetaheuristic Optimization with Evolver, Genocop and OptQuest
Metaheuristic Optimization with Evolver, Genocop and OptQuest MANUEL LAGUNA Graduate School of Business Administration University of Colorado, Boulder, CO 80309-0419 Manuel.Laguna@Colorado.EDU Last revision:
More informationMINIMAL EDGE-ORDERED SPANNING TREES USING A SELF-ADAPTING GENETIC ALGORITHM WITH MULTIPLE GENOMIC REPRESENTATIONS
Proceedings of Student/Faculty Research Day, CSIS, Pace University, May 5 th, 2006 MINIMAL EDGE-ORDERED SPANNING TREES USING A SELF-ADAPTING GENETIC ALGORITHM WITH MULTIPLE GENOMIC REPRESENTATIONS Richard
More informationBACKEND DESIGN. Circuit Partitioning
BACKEND DESIGN Circuit Partitioning Partitioning System Design Decomposition of a complex system into smaller subsystems. Each subsystem can be designed independently. Decomposition scheme has to minimize
More informationDesign Space Exploration Using Parameterized Cores
RESEARCH CENTRE FOR INTEGRATED MICROSYSTEMS UNIVERSITY OF WINDSOR Design Space Exploration Using Parameterized Cores Ian D. L. Anderson M.A.Sc. Candidate March 31, 2006 Supervisor: Dr. M. Khalid 1 OUTLINE
More informationHybrid approach for solving TSP by using DPX Cross-over operator
Available online at www.pelagiaresearchlibrary.com Advances in Applied Science Research, 2011, 2 (1): 28-32 ISSN: 0976-8610 CODEN (USA): AASRFC Hybrid approach for solving TSP by using DPX Cross-over operator
More informationApplied Cloning Techniques for a Genetic Algorithm Used in Evolvable Hardware Design
Applied Cloning Techniques for a Genetic Algorithm Used in Evolvable Hardware Design Viet C. Trinh vtrinh@isl.ucf.edu Gregory A. Holifield greg.holifield@us.army.mil School of Electrical Engineering and
More informationHeuristic Optimisation
Heuristic Optimisation Part 10: Genetic Algorithm Basics Sándor Zoltán Németh http://web.mat.bham.ac.uk/s.z.nemeth s.nemeth@bham.ac.uk University of Birmingham S Z Németh (s.nemeth@bham.ac.uk) Heuristic
More informationGenetic Placement: Genie Algorithm Way Sern Shong ECE556 Final Project Fall 2004
Genetic Placement: Genie Algorithm Way Sern Shong ECE556 Final Project Fall 2004 Introduction Overview One of the principle problems in VLSI chip design is the layout problem. The layout problem is complex
More informationA New Selection Operator - CSM in Genetic Algorithms for Solving the TSP
A New Selection Operator - CSM in Genetic Algorithms for Solving the TSP Wael Raef Alkhayri Fahed Al duwairi High School Aljabereyah, Kuwait Suhail Sami Owais Applied Science Private University Amman,
More informationAn adaptive genetic algorithm for dynamically reconfigurable modules allocation
An adaptive genetic algorithm for dynamically reconfigurable modules allocation Vincenzo Rana, Chiara Sandionigi, Marco Santambrogio and Donatella Sciuto chiara.sandionigi@dresd.org, {rana, santambr, sciuto}@elet.polimi.it
More informationCrew Scheduling Problem: A Column Generation Approach Improved by a Genetic Algorithm. Santos and Mateus (2007)
In the name of God Crew Scheduling Problem: A Column Generation Approach Improved by a Genetic Algorithm Spring 2009 Instructor: Dr. Masoud Yaghini Outlines Problem Definition Modeling As A Set Partitioning
More informationGenetic Algorithms Variations and Implementation Issues
Genetic Algorithms Variations and Implementation Issues CS 431 Advanced Topics in AI Classic Genetic Algorithms GAs as proposed by Holland had the following properties: Randomly generated population Binary
More informationNOVEL HYBRID GENETIC ALGORITHM WITH HMM BASED IRIS RECOGNITION
NOVEL HYBRID GENETIC ALGORITHM WITH HMM BASED IRIS RECOGNITION * Prof. Dr. Ban Ahmed Mitras ** Ammar Saad Abdul-Jabbar * Dept. of Operation Research & Intelligent Techniques ** Dept. of Mathematics. College
More informationSynthesis of VHDL Code for FPGA Design Flow Using Xilinx PlanAhead Tool
Synthesis of VHDL Code for FPGA Design Flow Using Xilinx PlanAhead Tool Md. Abdul Latif Sarker, Moon Ho Lee Division of Electronics & Information Engineering Chonbuk National University 664-14 1GA Dekjin-Dong
More informationEfficient Self-Reconfigurable Implementations Using On-Chip Memory
10th International Conference on Field Programmable Logic and Applications, August 2000. Efficient Self-Reconfigurable Implementations Using On-Chip Memory Sameer Wadhwa and Andreas Dandalis University
More informationANTICIPATORY VERSUS TRADITIONAL GENETIC ALGORITHM
Anticipatory Versus Traditional Genetic Algorithm ANTICIPATORY VERSUS TRADITIONAL GENETIC ALGORITHM ABSTRACT Irina Mocanu 1 Eugenia Kalisz 2 This paper evaluates the performances of a new type of genetic
More informationPARALLEL GENETIC ALGORITHMS IMPLEMENTED ON TRANSPUTERS
PARALLEL GENETIC ALGORITHMS IMPLEMENTED ON TRANSPUTERS Viktor Nìmec, Josef Schwarz Technical University of Brno Faculty of Engineering and Computer Science Department of Computer Science and Engineering
More informationImplementation and Analysis of an Error Detection and Correction System on FPGA
Implementation and Analysis of an Error Detection and Correction System on FPGA Constantin Anton, Laurenţiu Mihai Ionescu, Ion Tutănescu, Alin Mazăre, Gheorghe Şerban University of Piteşti, Romania Abstract
More informationUsing Genetic Programming to Evolve a General Purpose Sorting Network for Comparable Data Sets
Using Genetic Programming to Evolve a General Purpose Sorting Network for Comparable Data Sets Peter B. Lubell-Doughtie Stanford Symbolic Systems Program Stanford University P.O. Box 16044 Stanford, California
More informationA Hybrid Genetic Algorithms and Tabu Search for Solving an Irregular Shape Strip Packing Problem
A Hybrid Genetic Algorithms and Tabu Search for Solving an Irregular Shape Strip Packing Problem Kittipong Ekkachai 1 and Pradondet Nilagupta 2 ABSTRACT This paper presents a packing algorithm to solve
More informationOptimization of Test Scheduling and Test Access for ITC-02 SOC Benchmark Circuits
Journal of Computer Science 5 (4): 290-296, 2009 ISSN 1549-3636 2009 Science Publications Optimization of Test Scheduling and Test Access for ITC-02 SOC Benchmark Circuits 1 P. Sakthivel, 2 R. Delhi Babu
More information