Transistor/Gate Sizing Optimization

Transcription

1 Trasstor/Gate Szg Optmzato Gve: Logc etwork wth or wthout cell lbrary Fd: Optmal sze for each trasstor/gate to mmze area or power, both uder delay costrat Statc szg: based o tmg aalyss ad cosder all paths at oce [Fshbur-Dulop, ICCAD 85][Sapatekar et al., TCAD 93] [Berkelaar-Jess, EDAC 90][Che-Oodera-Tamaru, ICCAD 95] Dyamc szg: based o tmg smulato ad cosder paths actvated by gve patters [Co et al., ICCAD 96] Trasstor szg versus gate szg The Trasstor Szg Problem Problem statemet mmze Areax Comb. Logc subject to Delayx T spec or mmze Powerx subject to Delayx T spec Prepared by CK 1

2 Mathematcal Backgroud - dmesoal space Ay ordered -tuple x = x 1, x 2,..., x ca be thought of as a pot a -dmesoal space fx 1,x 2,..., x s a fucto o the -dmesoal space Covex fuctos fx s a covex fucto f gve fx ay two pots x a ad x b, the le jog the two pots les o or above the fucto fx x x a x b Nocovex f: x a x b x Math Backgroud Cotd. Covex fuctos two dmesos fx 1,x 2 = x x 2 2 Formally, fx s covex f fα x a + [1 - α] x b α fx a + [1 - α] fx b 0 α 1 Prepared by CK 2

3 Math Backgroud Cotd. Covex sets A set S s a covex set f gve ay two pots x a ad x b the set, the le jog the two pots les etrely wth the set Examples Shape of yomg Shape of a pzza No-covex Sets Shape of CA Slhouette of the Taj Mahal Math Backgroud Cotd. Mathematcal characterzato of a covex set S If x 1, x 2 S, the α x α x 2 S, for 0 α 1 x 1 x 2 If fx s a covex fucto, fx c s a covex set A tersecto of covex sets s a covex set Prepared by CK 3

4 Math Backgroud Cotd. Covex programmg problem mmze covex fucto fx such that [f x c ] Global mmum value s uque! No-rgorous explaato from The Hadwaver s Gude to the Galaxy fx x a x b x Math Backgroud Cotd. Eglsh A posyomal s lke a polyomal except all coeffcets are postve expoets could be real umbers postve or egatve Are these posyomals? x x x x x x x x x x 3 + 5/x 1 + x x 4 + 3/x 3 YES NO YES Prepared by CK 4

5 Math Backgroud Cotd. I ay posyomal fucto fx 1, x 2,..., x, substtute x = expz to get Fz 1, z 2,..., z The Fz 1, z 2,..., z = covex fucto z 1,..., z! mmze posyomal objectve x s s.t. posyomal fucto x s K for 1 m [x = expz ] mmze covex objectve over a covex set Therefore, ay local mmum s a global mmum! Trasstor Szg uder the Elmore Model x s the set vector of trasstor szes mmze Areax subject to Delayx T spec Areax = Σ = 1 to x posyomal! Each path delay = Σ R C R x -1, C x posyomal path delay fucto Delayx T spec Pathdelayx T spec for all paths Therefore, problem has a uque global m. value Prepared by CK 5

6 TILOS TImed LOgc Sythess Phlosophy Sce m. value s uque, a smple method should fd t! Problem mmze Areax subject to Delayx T spec Strategy Set all trasstors the crcut to mmum sze Fd the crtcal path largest delay path Reduce delay of crtcal path, but wth a mmal crease the objectve fucto value TILOS s a regstered trademark of Lucet Techologes TILOS Cotd. mmze Areax subject to Delayx T spec Fd D/ A for all trasstors o crtcal path Bump up the sze of trasstor wth the largest D/ A x M x + a default: M = 1; a = 1 cotact head wdth IN Crtcal Path OUT Crcut Prepared by CK 6

7 Sestvty Computato Dw = K + R prev C u. w + R u. C / w R prev w C D/ w = R prev. C u - R u. C / w 2 1 Could mmze path delay by settg dervatve to zero Problem: may cause aother path delay to become very hgh! hy Is t Ths THE Perfect Soluto? Problems wth teractg paths A B C D 1 Better to sze A tha to sze all of B, C ad D 2 If X-E s ear-crtcal ad A-D s crtcal, sze A ot D X E False paths, layout cosderatos ot corporated AND YET.. TILOS the commercal tool gves good solutos It has hadled crcuts wth 250K trasstors It has lear tme performace wth creasg crcut sze Prepared by CK 7

8 CONTRAST Solves the covex optmzato problem exactly Uses a teror pot method that s guarateed to fd the optmal soluto Delay spec. satsfed Optmal soluto Ca hadle crcuts wth about a thousad trasstors Covex Polytopes Polytope = -dmesoal covex polygo Half-space: a T x b a T x = b s a hyperplae e.g. a 1 x 1 + a 2 x 2 b two dmesos Polytope = tersecto of half-spaces,.e., a 1 T x b 1 AND a 2 T x b 2 AND a m T x b m Represeted as A x b Prepared by CK 8

9 Covex Optmzato Algorthm Vadya 1 Eclose soluto wth a polytope varat Typcally, take a box represeted by w w MAX ad w w MIN as the startg polytope. 2 Fd ceter of polytope, w c 3 Does w c satsfy costrats tmg specs? Take trasstor wdths correspodg to w c ad perform a statc tmg aalyss 4 Add a hyperplae through the ceter so that the soluto les etrely oe half-space Hyperplae equato depeds o feasblty of w c Equato of the New Half-Space Half-space: f w c. w f w c. w c If w c s feasble the f = objectve fucto Fd gradet of area fucto w c If w c s feasble the f = volated costrat Fd gradet of crtcal path delay Prepared by CK 9

10 w 2 w 1 Illustratve Example S S soluto f w = c, f decreasg S S Calculatg the Polytope Ceter Fdg exact cetrod s computatoally expesve Estmate ceter by mmzg log-barrer fucto Fx = - Σ =1 to m log a T x - b Happy cocdece : Fx s a covex fucto! Physcal meag: maxmze product of perpedcular dstaces to each hyperplae that defes the polytope Prepared by CK 10

11 Lear Programmg Methods LP-based approaches Model gate delay as a pecewse lear fucto Delay Parameters: trasstor wdths w, w p faout trasstor wdths put trasto tme Formulate problem as a lear program LP Use a effcet smplex package to solve LP w Power-Delay Szg mmze Powerw subject to Delayw T spec Area A spec Each gate sze Msze Power = dyamc power + short-crcut power Prepared by CK 11

12 POST-IT Dyamc Power Dyamc Power Power requred to charge/dscharge capactaces P dyamc = C L V dd 2 f p T C L = load capactace, f = clock frequecy, p T = trasto probablty Posyomal fucto w s f p T costat Costtutes domat part of power a well-desged crcut Mmze dyamc power mmze C L mmze all trasstor szes! RIGHT? Ufortuately ot! Short-Crcut Power POST-IT Short-crcut Power Power dsspated whe a drect V dd -groud path exsts Approxmate formula by Veedrck may assumptos P short-ckt = β/12. V dd -2V T 2 τ f p T β = trascoductace, τ = trasto tme Posyomal fucto w s f p T cost Other more accurate models: table lookup, curve-fttg Less tha 10-20% of total power a well-desged crcut So what s the catch? Prepared by CK 12

13 The Catch X A B C D E F G H Delay of gate A s large Therefore, the value of τ for B, C,..., H s large Therefore short-crcut power for B, C,..., H s large Ca be reduced by reducg the delay of A I other words, sze A! Tradeoff dyamc ad short-crcut power! Mpower msze Soluto Techque beg Calculate p T 's for mszed gates error < ε? ed No Yes Solve gate szg problem for curret p T Calculate p T 's for ew szes error = old p T - ew p T Problem: accuraces short-ckt. power model Prepared by CK 13

14 Prepared by CK 14 Trasstor/Gate Szg [Borah-Owes-Irw, ISLPD 95, TCAD 96] γ σ α τ µ τ µ + + = = = = f f k f CL f c V P dd Optmal trasstor sze τ µ µ τ µ µ + = + = = = = = p I p p p I p C O C p O 1 1 * 1 1 * C I = t. cap Power Optmal Szes ad Correspodg Power Savgs

15 Power-Delay Optmzato Power, Delay ad Power-Delay Curves Prepared by CK 15

16 Power-Delay Optmal Trasstor Szg Algorthm Power-Optmal tal szg Tmg aalyss hle exsts path-delay > target-delay Power-delay optmal szg crtcal path f path-delay > target-delay upsze trasstor wth mmum power-delay slope f path-delay < target-delay dowsze trasstor wth mmum power-delay slope Icremetal tmg aalyss Effect of Trasstor Szg Prepared by CK 16