CSE Introduction to Parallel Processing. Chapter 7. Sorting and Selection Networks

Transcription

1 Dr Izadi CSE-4 Introduction to Parallel Processing Chapter 7 Sorting and Selection Networks Become familiar with the circuit-level models of parallel processing Introduce useful design tools and trade-off issues via a familiar problem

2 Introduction to Parallel Processing: Algorithms and Architectures Instructor s Manual, Vol (4/), Page 9 7 What Is a Sorting Network? Fig 7 n n-sorter n The outputs are a permutation of the inputs satisfing n (non-descending) An n-input sorting network or an n-sorter input min in out in out -sorter input ma in out in out Fig 7 Block Diagram Alternate Representations Block diagram and four different schematic representations for a -sorter k input k input Fig 7 a Compare b b<a? Mu Mu k min k ma input Inputs arrive MSB first input reset b<a? S Q R Q - S Q - R Q a<b? Mu Mu Parallel and bit-serial hardware realizations of a -sorter min ma B Parhami, UC Santa Barbara Plenum Press, 999

3 Introduction to Parallel Processing: Algorithms and Architectures Instructor s Manual, Vol (4/), Page 9 Fig 74 Block diagram and schematic representation of a 4-sorter How to verif that the circuit of Fig 74 is a valid 4-sorter? The answer is eas in this case After the first two circuit levels, the top line carries the smallest and the bottom line the largest of the four values The final -sorter orders the middle two values More generall, we need to verif the correctness of an n- sorter through formal proofs or b time-consuming ehaustive testing Neither approach is attractive The zero-one principle: A comparison-based sorter is valid iff it correctl sorts all / sequences Invalid 6-sorter 6* * 8 9 B Parhami, UC Santa Barbara Plenum Press, 999

4 Introduction to Parallel Processing: Algorithms and Architectures Instructor s Manual, Vol (4/), Page 94 7 Figures of Merit for Sorting Networks a Cost: number of -sorter blocks used in the design b Dela: number of -sorters on the critical path n = 9, modules, 9 levels n =, 9 modules, 9 levels n =, 9 modules, 9 levels n = 6, 6 modules, levels Fig 7 Some low-cost sorting networks B Parhami, UC Santa Barbara Plenum Press, 999

5 Introduction to Parallel Processing: Algorithms and Architectures Instructor s Manual, Vol (4/), Page 9 n = 6, modules, levels n = 9, modules, 8 levels n =, modules, 7 levels n =, 4 modules, 8 levels n = 6, 6 modules, 9 levels Fig 76 Some fast sorting networks B Parhami, UC Santa Barbara Plenum Press, 999

6 Introduction to Parallel Processing: Algorithms and Architectures Instructor s Manual, Vol (4/), Page 96 7 Design of Sorting Networks Rotate b 9 degrees Fig 77 Brick-wall 6-sorter based on odd even transposition C(n) = C(n ) + n = (n ) + (n ) = n(n )/ D(n ) = D(n ) + = = (n ) + = n Cost Dela = n(n )(n )/ = Θ(n ) n (n )-sorter n n (n )-sorter n n Insertion sort n n Selection sort n Parallel insertion sort = Parallel selection sort = Parallel bubble sort! Fig 78 Sorting network based on insertion sort or selection sort B Parhami, UC Santa Barbara Plenum Press, 999

7 P P P P P 4 P P 6 P 7 P 8 In odd steps,,,, etc, odd-numbered processors echange values with their right neighbors

8 74 Batcher Sorting Networks First sorted sequence Second sorted sequence 4 6 v w v w v w v w v4 w v (, 4)-merger (, )-merger Fig 79 Batcher s even odd merging network for inputs 4 m (k s) m' (k' s) Merge,, and,, to get v, v, k even = k/ + k'/ s Merge,, and,, to get w, w, k odd = k/ + k'/ s Compare-echange the pairs of elements w :v, w :v, w :v,

9 Introduction to Parallel Processing: Algorithms and Architectures Instructor s Manual, Vol (4/), Page 98 Batcher s (m, m) even-odd merger, when m is a power of, is characterized b the following recurrences: C(m) = C(m/) + m = (m ) + (m/ ) + 4(m/4 ) + = m log m + D(m) = D(m/) + = log m + Cost Dela = Θ(m log m) n/-sorter (n/, n/)- merger n/-sorter Fig 7 The recursive structure of Batcher s even odd merge sorting network 4-sorters Even (,)-merger Odd (,)-merger Fig 7 Batcher s even-odd merge sorting network for eight inputs B Parhami, UC Santa Barbara Plenum Press, 999

10 Introduction to Parallel Processing: Algorithms and Architectures Instructor s Manual, Vol (4/), Page 99 Batcher sorting networks based on the even-odd merge technique are characterized b the following recurrences: C(n) = C(n/) + (n/)(log (n/)) + n(log n ) / D(n) = D(n/) + log (n/) + = D(n/) + log n = log n (log n + )/ Cost Dela = Θ(n log 4 n) Bitonic sorters Bitonic sequence: rises then falls, falls then rises, or is obtained from the first two categories through cclic shifts or rotations Eamples include: Rises, then falls Falls, then rises The previous sequence, right-rotated b n/-sorter n/-input bitonicsequence sorter n/-sorter n/-input bitonicsequence sorter Bitonic sequence n-input bitonicsequence sorter Fig 7 The recursive structure of Batcher s bitonic sorting network B Parhami, UC Santa Barbara Plenum Press, 999

11 -input sorters 4-input bitonicsequence sorters 8-input bitonicsequence sorter