Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models

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1 INTERNATIONAL JOURNAL OF NUMERICAL MODELLING: ELECTRONIC NETWORKS, DEVICES AND FIELDS Int. J. Numer. Model. 2009; 22:43 55 Published online 1 September 2008 in Wiley InterScience ( Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models Ping Yang 1,2,,y and Wei Li 1 1 Laboratory of Materials and Micro-structural Integrity, School of Mechanical Engineering, Jiangsu University, Zhenjiang , People s Republic of China 2 Laboratory of Advanced Design and Manufacturing, School of Mechanical Engineering, Jiangsu University, Zhenjiang , People s Republic of China SUMMARY The objective of this paper is to investigate stress and strain of a special scale package-substrate on chip for reliability evaluation or manufacture strategy in deep-seated situation. A two-dimensional model with onehalf of cross-section (2D model) and a three-dimensional model with one-fourth of whole package (3D model) were built, respectively, to simulate the thermal stress and strain of CSP-SOC under the condition of the standard industry thermal cycling temperature 40 to1251c. The different locations can be processed by using the two models, respectively, based on different modeling simplified modes. By using 2D model, the numerical simulation shows that the maximum deformation of the prototype occurs in printed circuit board (PCB), the maximum stress and strain occurs in the outer solder balls. In the meantime, by the results of 3D model, the simulation shows that the maximum elastic strain occurs in the interface between the solder balls and PCB, the minimum strain occurs in the underfill tape, the maximum packaging stress occurs in the edge area of the chip. The result from 3D model maybe more impersonal to reflect the stress and strain characteristics because the third direction is considered in modeling. The analysis by integrating the 2D model and 3D model can get a more comprehensive profile for the thermal investigation of chip scale package (CSP) than by using any single model. The investigation built a basis for improving reliability in engineering design of CSP product. Copyright r 2008 John Wiley & Sons, Ltd. Received 5 December 2007; Revised 21 May 2008; Accepted 7 July 2008 KEY WORDS: chip scale package; temperature cycling; thermal stress; thermal strain; finite element; numerical simulation *Correspondence to: Ping Yang, Laboratory of Materials and Micro-structural Integrity, School of Mechanical Engineering, Jiangsu University, Zhenjiang , People s Republic of China. y yangpingdm@ujs.edu.cn,yangping1964@163.com Copyright r 2008 John Wiley & Sons, Ltd.

2 44 P. YANG AND W. LI 1. INTRODUCTION With the development of information on portable computer, mobile phone, numeral camera and so on, lighter, thinner, good electrical properties, high reliability and high-density package technology has been in constant search. Chip scale package (CSP) with mature techniques, low manufacture cost and good development potential is a high-density package. Although CSP has good performance, it is more sensitive than conventional package at work. Under the temperature cycling, for the coefficient of thermal expansion of the chip, solder joint and substrate mismatching, it may lead to thermal stress and strain on the package and solder joint, and it will be invalid when the intensity is lower than thermal stress [1 4]. Johnson et al. [1] discussed thermo-mechanical simulation of stacked CSPs with Moire interferometry validation. In this paper, Moire interferometry and finite element (FE) analysis are used to quantify the deformation of stacked CSPs under thermal and accelerated thermal cycling loads. Viscoplastic FE-based solder joint fatigue simulations indicate good reliability for several common design configurations of stacked packages. Pang et al. [2] discussed thermal cycling analysis of flip-chip solder joint reliability. The reliability concern in flip-chip-on-board technology is the high thermal mismatch deformation between the silicon die and the printed circuit board (PCB), which results in large solder joint stresses and strains causing fatigue failure. This study investigates different methods of implementing thermal cycling analysis, namely using the dwell creep and full creep methods based on a phenomenological approach to modeling timeindependent plastic and time-dependent creep deformations. There are significant differences between the dwell creep and full creep analysis results for the flip-chip solder joint strain responses and the predicted fatigue life. Comparison was made with a rate-dependent viscoplastic analysis approach. Investigations on thermal cycling analysis of the temperature range (DT) effects on the predicted fatigue lives of solder joints are reported. Amagai [3] discussed CSP solder joint reliability and modeling. A viscoplastic constitutive model was used to analyze the thermally induced plastic and creeping deformation and low cycle fatigue behavior of the solder joints in CSPs mounted on PCBs. The time-dependent and time-independent viscoplastic strain rate and plastic hardening work factors of solder material were used in 2D plane strain FE models. After satisfactory correlation between experiment and model was observed, the effect of material properties and package design variables on the fatigue life of solder joints in CSPs was investigated, and the primary factors affecting solder fatigue life were subsequently presented. Furthermore, a simplified model was proposed to predict the solder fatigue life in CSPs. Yang [5,6] discussed mechanical characterizations of different packaging materials interface and PBGA with nano-scale modeling method. In this paper, a two-dimensional with one-half of cross-section model (2D model) and a three-dimensional with one-fourth of whole package model (3D model) were built, respectively, to simulate the thermal stress and strain of CSP-SOC. The whole and global solder ball dynamics performance under the standard temperature cycling ( 40 to 1251C) of a special CSP was analyzed by integrating 2D/3D models. The different locations can be processed by using the two models, respectively, based on different modeling simplified modes. Based on the results on the thermal stress and strain curve along with time variation, the thermal analysis can be provided for the advanced package reliability analysis. The results show that the analysis by integrating the 2D model and 3D model can get a more comprehensive profile for thermal characteristics investigation of CSP than by using any single model. The investigation built a basis for improving reliability in the engineering design of CSP product (Figures 1 4).

3 NUMERICAL ANALYSIS ON THERMAL CHARACTERISTICS ANAND MODEL The mechanical behavior of the solder ball reflects the viscoplastic phenomenon under temperature cycling condition. Anand viscoplastic model was used in the ANSYS FE code, which was applied to viscoplastic materials by Anand in The viscoplastic material is timedependent stress and strain. The nonlinear strain is relative to temperature and time, while the stress is relative to the load variation rate. The important equations are as follows: h dp ¼ A exp Q=Ry sinh x s i 1=m ð1þ s _S ¼ h 0 ðjbjþ a B dp jbj ð2þ B ¼ 1 s s ð3þ s ¼ ^s dp n A expq=ry ð4þ All that are Anand model operation equations in ANSYS, and nine parameters are needed to be used in ANSYS. They are C 1 C 9, parameter a is greater than or equal to 1 and other parameters are bigger than zero. Figure 1. The cross-section of CSP-SOC: (a) structure scheme and (b) structure dimension scheme.

4 46 P. YANG AND W. LI Figure 2. The plot of temperature cycling. Figure 3. CSP-SOC 1/2 2D cross-section grid divided graph. 3. FE MODEL ANALYSIS 3.1. Model hypothesis In order to improve the efficiency, simplification and some hypothesis have been adopted: (1) all materials are elastic, except for solder balls that are nonlinear and time dependent. (2) The gold wire is tiny to the whole package; therefore, its effect to result can be ignored. (3) Ignore the original packaging stress and strain and flaws. (4) When the temperature fluctuates, the whole configuration temperature remains the same, namely T(x, t) 5 T(t), and considers no thermal convection and heat exchange Parameter choice of analysis and materials In the simulation, the material of the chip is Si, the material of solder balls is 37Sn/63Pb, the material of the substrate is bismaleimide triazine, the material of the PCB is FR-4 and the

5 NUMERICAL ANALYSIS ON THERMAL CHARACTERISTICS 47 Figure 4. CSP-SOC 3D grid divided graph. Table I. Material parameters. Kinds Elastic modulus (GPa) Poisson s ratio Coefficient of thermal expansion (ppm/k) Component Encapsulation molding compound a , a (EMC) T g C Substrate Tape Chip Solder ball Printed circuit board (PCB) Table II. The parameters of Anand model. Constant C 1 C 2 C 3 C 4 C 5 C 6 C 7 C 8 C 9 Variable S 0 (MPa) Q/R (K) A (s 1 ) x m h 0 (MPa) ^s (MPa) n A Value E material of the molding compound is epoxy adhesive. The parameters of all materials and solder balls are given in Tables I and II, respectively: 3.3. CSP-SOC model The CSP-SOC prototype is a 8 21 mm rectangular package, chip size is mm, encapsulation molding compound (EMC) size is 21 mm, the substrate on both sides is mm, the solder ball diameter is 0.45 mm, the ball pitch is 0.8 mm, the distance between the inner solder ball and the package center is 2 mm, the height of the final solder balllike drum is 0.27 mm, PCB dimension is mm and the cross-section is as follows: In

48 P. YANG AND W. LI Figure 5. The whole deformation graph of 2D and the approximate location of node 242. Figure 6. Equivalent stress distribution plot of 2D model.

Because there are many CSP-SOC products in the same PCB, the interaction to each other must be ignored. Plane82 element is used for 2D model except for the solder ball.

6 48 P. YANG AND W. LI Figure 5. The whole deformation graph of 2D and the approximate location of node 242. Figure 6. Equivalent stress distribution plot of 2D model. order to simulate the reliability of the chip on board, CSP-SOC solder balls must be adhered to the FR-4 PCB ( mm). Because there are many CSP-SOC products in the same PCB, the interaction to each other must be ignored. Plane82 element is used for 2D model except for the solder ball. The element size is equal to 0.05 mm. In order to get a precise result of the solder ball, the element size of the solder ball is set equal to 0.02 mm. The free mesh is used for the whole model including the solder ball. It includes 9143 elements, nodes; each element has 8 different nodes.

NUMERICAL ANALYSIS ON THERMAL CHARACTERISTICS 49 Figure 7. The E x variation of the outer solder ball in 2D model. Figure 8. Vonmises stress distribution plot of 3D 1/4 model.

7 NUMERICAL ANALYSIS ON THERMAL CHARACTERISTICS 49 Figure 7. The E x variation of the outer solder ball in 2D model. Figure 8. Vonmises stress distribution plot of 3D 1/4 model. Solid45 element is used for 3D model except for the solder ball. In order to get fewer elements for 3D model, two different types of mesh are used for 3D model. The chip and tape are plotted by using hexahedron element sweep. The solder ball and solder ball boundary are plotted by using tetrahedron element with free meshing mode. The model includes elements and nodes Temperature load application Initial temperature is set up to room temperature 251C, then the first thermal cycling and the process are divided into four steps: (1) Increasing the temperature from the room temperature 25 to 1251C within 5 min. (2) Keep the temperature at 1251C for 25 min. (3) Reducing the temperature from 125 to 401C within 5 min. (4) Keeping the temperature at 401C for 25 min.

8 50 P. YANG AND W. LI Figure 9. Solder ball shear force distribution plot of 3D 1/4 model. Figure 10. E y distribution of 3D 1/4 model. 4. ANALYSIS AND DISCUSSION OF STRESS AND STRAIN 4.1. Analysis of 2D stress and strain Figure 5 shows the whole deformation graph. It shows that the maximum deformation occurs in the PCB. Based on the equivalent stress distribution plot by using 2D model, the equivalent strain occurs in the joint between EMC and substrate (Figure 6). The maximum strain of 2D model occurs in the outer solder ball near the PCB. Based on the 2D FE strain analysis graph, the strain variation graph is shown as Figure 7. The maximum strain occurs in the joint with PCB (the left underside of the solder ball) and joint with substrate (the right top of the solder

9 NUMERICAL ANALYSIS ON THERMAL CHARACTERISTICS 51 Figure 11. Elastic strain along the Z direction of 3D 1/4 model. Figure 12. Displacement in node along the Y direction. ball); the least strain takes place in the joint between the right underside of the solder ball and the PCB Analysis of 3D stress and strain Figure 8 shows the Vonmises stress of 3D 1/4 model. It is easy to find that an obvious equivalent strain variation occurs between solder balls and the outer fringe of chip. The maximum strain of the solder ball is Pa and the minimum is Pa. Based on the equivalent strain on the solder ball, approximately, shear force in the outer solder ball is GPa and shear force in the inner solder ball is GPa. Therefore, we can conclude that the outer solder ball is the most dangerous solder ball to occur cracks in working. Figure 9 shows that the maximum stress occurs on the solder ball that located in the outer and underside of chip. Therefore, the solder balls should be put around the chip, but not under

10 52 P. YANG AND W. LI Figure 13. Node 242 stress along the Y direction in the right fringe PCB. Figure 14. The max stress (node 623) along the Z direction. the chip. Based on the 3D analysis graph, the maximum strain along the Y direction occurs in the outer solder ball. Figure 10 shows the strain variation graph. It shows that the maximum strain occurs on the outer fringe. Figure 11 shows the obvious elastic variation. The maximum and minimum elastic strains both occur on the tape, and the maximum elastic occurs in the underside of the chip center area Stress and strain along with time variation Figure 12 shows that the node is the maximum displacement variation joint between the PCB and the solder ball. The approximate location of the node can be shown in Figure 5.

11 NUMERICAL ANALYSIS ON THERMAL CHARACTERISTICS 53 Figure 15. (Node 4999) the max equivalent stress. Along the Y direction, when the temperature increases in the first 5 min, the displacement increases sharply. When the temperature decreases in the second time, the displacement increases sharply again; but after the temperature decreasing in the third time, the amplitude decreases obviously. Then, the variation tends to placidity. The maximum and the minimum are and , respectively. Figure 13 shows that the PCB occurs stress in a short time (less than 2000 s), and then the variation tends to placidity. The stress and strain distribution is reasonable under temperature cycling condition. If the stress on PCB is too excessive, it cannot support the solder ball and the substrate. Therefore, it cannot transfer signal. Figure 14 shows the variation course of stress relative to time in chip fringe along the Z direction (node 623 in Figure 8). Further more, it also can show that the variation is inerratic. This phenomenon cannot be shown by using 2D model. Figure 15 shows the maximum Vonmises stress relative to time on the outer solder ball (node 4999 in Figure 8). The variation range is less than the stress variation. 5. CONCLUSIONS (1) A 2D model and a 3D model were built, respectively, to simulate the thermal stress and strain of CSP. (2) The different locations can be processed by using the two models, respectively, based on different modeling simplified modes. By using 2D model, the numerical simulation shows that the maximum deformation of the prototype occurs in PCB, the maximum stress and strain occur in the outer solder balls. In the meantime, by the results of 3D model, the simulation shows that the maximum elastic strain occurs in the interface between the solder balls and the PCB, the minimum strain occurs in the underfill tape, the maximum packaging stress occurs in the edge area of the chip. The result from 3D model maybe more impersonal to reflect the stress and strain characteristics because the third direction is considered in

12 54 P. YANG AND W. LI modeling. The analysis by integrating the 2D model and 3D model can get a more comprehensive profile for the thermal investigation of CSP than by using any single model. The results built a basis for improving reliability in the engineering design of CSP product. NOMENCLATURE dp A s S * _S Q y x m h 0 n a PCB CSP SOC BT EMC CTE PRXY EX the inelastic strain rate pre-exponential factor the tensile stress, S is deformation resistance saturation value of deformation resistance time derivative of deformation resistance activation energy, R is universal gas constant absolute temperature the stress multiplier the strain rate sensitivity of stress hardening/softening constant strain rate sensitivity of saturation the hardening or softening strain rate sensitivity printed circuit board chip scale package small outline C-lead (package) bismaleimide triazine encapsulation molding compound coefficient of thermal expansion Poisson s ratio elastic modulus ACKNOWLEDGEMENTS The authors would like to acknowledge the support of National Natural Science Foundation of China( ), the support of Natural Science Foundation of Jiangsu province of China (BK ), Special Science Foundation for Middle-Young academic leader of Jiangsu high education in China(Qinglan Gongcheng Project), Innovative Science Foundation for Graduate Students of Jiangsu Province(CX07B_069z), the Natural Science Foundation for Qualified Personnel of Jiangsu University(04JDG027), the Special Natural Science Foundation for Innovative Group of Jiangsu University, Special Science Foundation for Middle-Young academic leader of Guangxi high education in China during the course of this work. REFERENCES 1. Johnson ZE, Schneck NR, Thoreson AR et al. Thermo-mechanical simulation of stacked chip scale packages with Moiré interferometry validation. Thermomechanical Phenomena in Electronic Systems Proceedings of the Intersociety Conference, v 2006, Tenth Intersociety Conference on Thermal and Thermomechanical Phenomena and Emerging Technologies in Electronic Systems, ITherm 2006, San Diego, CA, USA, 2006;

13 NUMERICAL ANALYSIS ON THERMAL CHARACTERISTICS Pang JHL, Chong DYR, Low TH. Thermal cycling analysis of flip-chip solder joint reliability. IEEE Transactions on Component and Package Technologies 2001; 24(4): Amagai M. Chip scale package (CSP) solder joint reliability and modeling. Microelectronics Reliability 1999; 39: Yang P, Liao N, Yang D, Ernst LJ. Sliding simulation for adhesion problems in micro gear trains based on an atomistic simplified model. Microsystem Technologies 2006; 12(12): Yang P, Zhang J. Research on parametric analysis for stress of PBGA solder joint under shock load. International Journal of Materials and Product Technology 2008; 31(2 4): Yang P, Liao N. Research on characteristics of interfacial heat transport between two kinds of materials using a mixed MD-FE model. Applied Physics A Materials Science & Processing DOI: /s AUTHORS BIOGRAPHIES Ping Yang is currently a professor in Jiangsu University in China. He is also currently a director of China Precision Machine Society and a senior member of Chinese Institute of Electronics. He received his PhD in mechanical engineering from Huazhong University of Science and Technology (HUST) in He engaged in sciences research in Concordia University. His research interests focus on the theoretical aspect and CAD of mechanical system for the purposes of design and control. He has authored over 30 professional and scholarly publications in famous international journals in the very specialized field of the theoretical aspect and CAD of mechanical systems for the purposes of design and control. Wei Li is a postgraduate in the School of Mechanical Engineering, Jiangsu University. His research interests are in electronic packaging and product reliability.

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