AIM Photonics Silicon Photonics PDK Overview. March 22, 2017 Brett Attaway
|
|
|
- Johnathan Quinn
- 6 years ago
- Views:
Transcription
1 AIM Photonics Silicon Photonics PDK Overview March 22, 2017 Brett Attaway
2 Silicon Photonics Process Design Kits (PDK) PDK 3 technologies, 2 major releases/year Full (active)- v1.0 available now Passive- v1.0 available now Interposer- v1.0 available now Next: v1.5 (Aug 17), v2.0 (Jan 18) Incremental releases add components & maturity leading to guaranteed specs based on full statistical corner validation Extensive Component Library Passive, Active and Interposer components Support for simulation, layout, schematics, DRC, documentation Developed by Analog Photonics LLC (Boston) EDA/PDA Design Software Supported Download the PDK from MOSIS AIM Membership or license required PDK Passive Components Qty Selected Performance Waveguides (Si & SiN), curves, etc. 16+ Si:<2.2dB/cm, SiN:<1dB/cm Edge Couplers (Si & SiN) 2 <2.5dB/facet loss Vertical Couplers (Si & SiN) 2 <3dB loss 3dB 4-Port Couplers (Si & SiN) 2 loss <0.5dB, deviation <1% Y- Junctions (Si & SiN) 2 loss <0.25dB, deviation <1% Directional Coupler (Si & SiN) 2 loss <0.5dB, deviation 1550nm Si-to-SiN Coupler (escalator) 1 loss <0.1dB Crossing (Si) 1 loss <0.25dB, crosstalk < -60dB PDK Active Devices Qty Selected Performance Digital Ge Photodetector 1 >30GHz, <20nA dark Analog Ge Photodetector 1 >25GHz, <80nA dark Digital Mach-Zehnder Modulator 1 Analog Mach-Zehnder Modulator 1 Thermo-Optic Phase Shifter (Si) 1 Thermo-Optic Switch (Si) 1 <1dB loss, 25mW Tunable Filter (Si) 4 Microdisk Switch (tunable) 4 Microdisk Modulator (tunable) 4 >15GHz, >25Gb/s, push-pull <2Vpp per arm, >5dB extinction, <5dB loss >15GHz, -10V< Vs <0V, 25dB lin., nm 0.25dB loss, <50mW, range 0π<Δθ<2π <0.5dB loss, 26nm FSR, >1nm/mW tuning efficiency <2ns switch time, >200GHz EO 1.2V 15GHz, 25Gb/s, 1.2Vpp, 1dB Loss, 8dB extinction 2
3 Silicon Photonics Multi Project Wafer (MPW) 2017 MPW Fab Runs SUNY Poly 300mm fab line 3 MPW offerings Full-Active- 2 runs in 2017 Passive Only- 2 runs in 2017 Interposer- 1 run in 2017 Reservations to be a rider can be started at Generates quote with terms 20% down to hold slot; balance invoiced at design submission MOSIS is the MPW Aggregator DRC clean designs (Mentor Calibre) are submitted to MOSIS MOSIS also distributes the PDK MPW Pricing FULL 50mm 2 chips $100K AIM members $120K non-members 8mm 2 chips $25K AIM members $30K non-members PASSIVE 50mm2 chips $30K AIM members $36K non-members INTERPOSER 156mm2 $93.6K AIM members $112.3K non-members 3
4 Silicon Photonics MPW Schedule PDK Releases Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec Jan Feb PDK 1.5 PDK 2.0 (100% measured, PDK 2.5 (80% measured) begin statistical) PDK 3.0 Active/Passive Combo Run #1 Run #2 On-Demand Due Apr 10 Full 17-01: MPW Fab Due Sep 5 Due Mar 5 Full 18-01: MPW Fab Full 17-02: MPW Fab Full 18-02: MPW Fab On-Demand; flexible start Full 17-03: MPW Fab Due Aug 6 On-Demand; flexible start Full 18-03: MPW Fab Interposer Run #1 On-Demand Int 17-01: MPW Fab Int 18-01: MPW Fab Due Jun 5 Due May 14 On-Demand; flex start Int 18-02: MPW Fab Notes/Assumptions: 1. DRC clean designs uploaded to MOSIS by the due date for each run 2. Must follow Design Guide in the applicable PDK version 3. MPW Reservations confirmed with 20% down payment; balance invoiced at submission 4. On-Demand runs will only start if economically feasible 4
5 Integrated Electronic/Photonic Design Enablement & more PDK Library System Level Design PIC / ASIC / SOC Schematic Entry and Design Physical Design / Layout Design Simulation, Verification, DRC Fabrication RTL / IP Partitioning and Design This PDK and library enables: Less complex design Hierarchical design Design re-use IP market Large design community Latest EPDA methodologies System-level E-O co-design Layout & schematic based flows Photonic schematic capture drag & drop components *auto waveguide routing Integrated photonic circuit simulation Integrated E-O IC floor-planning 2.5D/3D & monolithic integration *Parameter extraction DRC & *LVS (* coming soon) 5
6 EPDA Methodologies Contact these EPDA companies for more info multiple partnerships & integrated solutions
7 Interesting 2017 Design Enablement Projects Reference Design Project System level integrated transceiver with PIC and CMOS designs Open and sharable useful for EPDA methodology development Focus area on E-O co-simulation with verilog-a modeling methodologies Standardized Parameters for Photonic Modeling Project Collaborate with industry/academia/epda Ease PDK creation; define common functions & parameters
AIM Photonics: Manufacturing Challenges for Photonic Integrated Circuits
AIM Photonics: Manufacturing Challenges for Photonic Integrated Circuits November 16, 2017 Michael Liehr Industry Driving Force EXA FLOP SCALE SYSTEM Blades SiPh Interconnect Network Memory Stack HP HyperX
PIC design across platforms. Ronald Broeke Bright Photonics
PIC design across platforms Ronald Broeke Bright Photonics OUTLINE Introduction PIC applications & designs MPW Materials & platforms Design modules PICs in Phoxtrot Design House for Photonics ICs Custom
Virtuoso - Enabled EPDA framework AIM SUNY Process
Virtuoso - Enabled EPDA framework AIM SUNY Process CADENCE, LUMERICAL, PHOENIX SOFTWARE Driven by our customers Cadence is the leader with Virtuoso custom design platform for electronics custom and mixed
Photonics Integration in Si P Platform May 27 th Fiber to the Chip
Photonics Integration in Si P Platform May 27 th 2014 Fiber to the Chip Overview Introduction & Goal of Silicon Photonics Silicon Photonics Technology Wafer Level Optical Test Integration with Electronics
AIM Photonics Overview Roger Helkey Associate Director, West Coast Hub
AIM Photonics Overview Roger Helkey Associate Director, West Coast Hub 1 Explosive Growth In Datacenter Traffic Global data center traffic to triple and reach a total of 7.7 zettabytes annually by 2017-25%
Silicon Photonics PDK Development
Hewlett Packard Labs Silicon Photonics PDK Development M. Ashkan Seyedi Large-Scale Integrated Photonics Hewlett Packard Labs, Palo Alto, CA ashkan.seyedi@hpe.com Outline Motivation of Silicon Photonics
Silicon Photonics Scalable Design Framework:
Silicon Photonics Scalable Design Framework: From Design Concept to Physical Verification Hossam Sarhan Technical Marketing Engineer hossam_sarhan@mentor.com Objective: Scalable Photonics Design Infrastructure
UBCx Phot1x: Silicon Photonics Design, Fabrication and Data Analysis
UBCx Phot1x: Silicon Photonics Design, Fabrication and Data Analysis Course Syllabus Table of Contents Course Syllabus 1 Course Overview 1 Course Learning Objective 1 Course Philosophy 1 Course Details
Adding Curves to an Orthogonal World
Adding Curves to an Orthogonal World Extending the EDA Flow to Support Integrated Photonics Paul Double July 2018 Traditional IC Design BREXIT AHOY! Designers & tool developers have lived in a orthogonal
Putting Curves in an Orthogonal World
Putting Curves in an Orthogonal World Extending the EDA Flow to Support Integrated Photonics Masahiro Shiina October 2018 Traditional IC Design Designers & tool developers have lived in a orthogonal world
Xilinx SSI Technology Concept to Silicon Development Overview
Xilinx SSI Technology Concept to Silicon Development Overview Shankar Lakka Aug 27 th, 2012 Agenda Economic Drivers and Technical Challenges Xilinx SSI Technology, Power, Performance SSI Development Overview
take control of your photonics design flow Photonic-Electronic IC design and implementation Pieter Dumon 27/09/2016
take control of your photonics design flow Photonic-Electronic IC design and implementation Pieter Dumon 27/09/2016 Giving photonic IC designers the same power as electronic IC designers. Make it possible
Stacked Silicon Interconnect Technology (SSIT)
Stacked Silicon Interconnect Technology (SSIT) Suresh Ramalingam Xilinx Inc. MEPTEC, January 12, 2011 Agenda Background and Motivation Stacked Silicon Interconnect Technology Summary Background and Motivation
Seattle (NWMLS Areas: 140, 380, 385, 390, 700, 701, 705, 710) Summary
November, 2016 MTD MARKET UPDATE Data Current Through: November, 2016 (NWMLS Areas: 140, 380, 385, 390,, 701, 705, 710) Summary 4,000 3,500 3,000 2,500 2,000 1,500 1,000 500 0 Active, Pending, & Months
MARKET PERSPECTIVE: SEMICONDUCTOR TREND OF 2.5D/3D IC WITH OPTICAL INTERFACES PHILIPPE ABSIL, IMEC
MARKET PERSPECTIVE: SEMICONDUCTOR TREND OF 2.5D/3D IC WITH OPTICAL INTERFACES PHILIPPE ABSIL, IMEC OUTLINE Market Trends & Technology Needs Silicon Photonics Technology Remaining Key Challenges Conclusion
D5.2: Packaging and fiber-pigtailing of the 2 nd generation 2x2 optical interconnect router
ICT - Information and Communication Technologies Merging Plasmonics and Silicon Photonics Technology towards Tb/s routing in optical interconnects Collaborative Project Grant Agreement Number 249135 D5.2:
Asks for clarification of whether a GOP must communicate to a TOP that a generator is in manual mode (no AVR) during start up or shut down.
# Name Duration 1 Project 2011-INT-02 Interpretation of VAR-002 for Constellation Power Gen 185 days Jan Feb Mar Apr May Jun Jul Aug Sep O 2012 2 Start Date for this Plan 0 days 3 A - ASSEMBLE SDT 6 days
All King County Summary Report
September, 2016 MTD MARKET UPDATE Data Current Through: September, 2016 18,000 16,000 14,000 12,000 10,000 8,000 6,000 4,000 2,000 0 Active, Pending, & Months Supply of Inventory 15,438 14,537 6.6 6.7
ASIC Physical Design Top-Level Chip Layout
ASIC Physical Design Top-Level Chip Layout References: M. Smith, Application Specific Integrated Circuits, Chap. 16 Cadence Virtuoso User Manual Top-level IC design process Typically done before individual
FREQUENTLY ASKED QUESTIONS
DISTRICT 7030 WEBSITE FREQUENTLY ASKED QUESTIONS NB: THIS WILL BE REGULARLY UPDATED FOR YOUR INFORMATION. 1. This website works better with the following browsers: Internet Explorer (IE) and Google Chrome.
This report is based on sampled data. Jun 1 Jul 6 Aug 10 Sep 14 Oct 19 Nov 23 Dec 28 Feb 1 Mar 8 Apr 12 May 17 Ju
0 - Total Traffic Content View Query This report is based on sampled data. Jun 1, 2009 - Jun 25, 2010 Comparing to: Site 300 Unique Pageviews 300 150 150 0 0 Jun 1 Jul 6 Aug 10 Sep 14 Oct 19 Nov 23 Dec
Seattle (NWMLS Areas: 140, 380, 385, 390, 700, 701, 705, 710) Summary
September, 2016 MTD MARKET UPDATE Data Current Through: September, 2016 (NWMLS Areas: 140, 380, 385, 390,, 701, 705, 710) Summary Active, Pending, & Months Supply of Inventory 5,000 4,500 4,000 3,500 4,091
PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05
PDK-Based Analog/Mixed-Signal/RF Design Flow 11/17/05 Silvaco s What is a PDK? Which people build, use, and support PDKs? How do analog/mixed-signal/rf engineers use a PDK to design ICs? What is an analog/mixed-signal/rf
Seattle (NWMLS Areas: 140, 380, 385, 390, 700, 701, 705, 710) Summary
October, 2016 MTD MARKET UPDATE Data Current Through: October, 2016 (NWMLS Areas: 140, 380, 385, 390,, 701, 705, 710) Summary Active, Pending, & Months Supply of Inventory 4,500 4,000 3,500 4,197 4,128
Fluidity Trader Historical Data for Ensign Software Playback
Fluidity Trader Historical Data for Ensign Software Playback This support document will walk you through the steps of obtaining historical data for esignal into your Ensign Software program so that you
Broadband Rate Design for Public Benefit
Broadband Rate Design for Public Benefit The transition from service-based rates to loop rates on Chelan PUD s Broadband Network Dec.19, 2016 No action required today Today s Presentation Loop Rates Final
HPE Security Data Security. HPE SecureData. Product Lifecycle Status. End of Support Dates. Date: April 20, 2017 Version:
HPE Security Data Security HPE SecureData Product Lifecycle Status End of Support Dates Date: April 20, 2017 Version: 1704-1 Table of Contents Table of Contents... 2 Introduction... 3 HPE SecureData Appliance...
Design software and services for the integrated photonics market IPKISS Moves the edges in PIC PDK building
Design software and services for the integrated photonics market IPKISS 3.1.3 Moves the edges in PIC PDK building take controltake of your control photonics of your photonics design flow design flow 1
Markets Gateway Roadmap
Markets Gateway Roadmap As of April 17, 2018 www.pjm.com Background Markets Gateway allows users to submit information and obtain data needed to conduct business in the Day-Ahead, Regulation and Synchronized
AMS DESIGN METHODOLOGY
OVER VIEW CADENCE ANALOG/ MIXED-SIGNAL DESIGN METHODOLOGY The Cadence Analog/Mixed-Signal (AMS) Design Methodology employs advanced Cadence Virtuoso custom design technologies and leverages silicon-accurate
software.sci.utah.edu (Select Visitors)
software.sci.utah.edu (Select Visitors) Web Log Analysis Yearly Report 2002 Report Range: 02/01/2002 00:00:0-12/31/2002 23:59:59 www.webtrends.com Table of Contents Top Visitors...3 Top Visitors Over Time...5
Organics in Photonics: Opportunities & Challenges. Louay Eldada DuPont Photonics Technologies
Organics in Photonics: Opportunities & Challenges Louay Eldada DuPont Photonics Technologies Market Drivers for Organic Photonics Telecom Application Product Examples Requirements What Organics Offer Dynamic
ECE520 VLSI Design. Lecture 1: Introduction to VLSI Technology. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 1: Introduction to VLSI Technology Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Course Objectives
Open access to photonic integration technologies
Open access to photonic integration technologies Academic and Industrial examples of photonic integrated circuits Katarzyna Ławniczuk k.lawniczuk@tue.nl What is photonic integration technology? multiple
UBS Technology Conference 2011 Franki D Hoore - Director European Investor Relations London, March 10, 2011
UBS Technology Conference Franki D Hoore - Director European Investor Relations London, March 10, / Slide 1 Safe Harbor "Safe Harbor" Statement under the US Private Securities Litigation Reform Act of
COURSE LISTING. Courses Listed. with SAP Hybris Marketing Cloud. 24 January 2018 (23:53 GMT) HY760 - SAP Hybris Marketing Cloud
with SAP Hybris Marketing Cloud Courses Listed HY760 - SAP Hybris Marketing Cloud C_HYMC_1702 - SAP Certified Technology Associate - SAP Hybris Marketing Cloud (1702) Implementation Page 1 of 12 All available
Annex A to the DVD-R Disc and DVD-RW Disc Patent License Agreement Essential Sony Patents relevant to DVD-RW Disc
Annex A to the DVD-R Disc and DVD-RW Disc Patent License Agreement Essential Sony Patents relevant to DVD-RW Disc AT-EP S95P0391 1103087.1 09-Feb-01 1126619 8/16 Modulation AT-EP S95P0391 1120568.9 29-Aug-01
October Real Sector Statistics Division. Methodology
October 2013 Methodology The Consumer Survey has been conducted monthly since October 1999. Moreover, since January 2007 the Survey has involved 4,600 households as respondents (stratified random sampling)
An overview of standard cell based digital VLSI design
An overview of standard cell based digital VLSI design Implementation of the first generation AsAP processor Zhiyi Yu and Tinoosh Mohsenin VCL Laboratory UC Davis Outline Overview of standard cellbased
Packaging and Integration Technologies for Silicon Photonics. Dr. Peter O Brien, Tyndall National Institute, Ireland.
Packaging and Integration Technologies for Silicon Photonics Dr. Peter O Brien, Tyndall National Institute, Ireland. Opportunities for Silicon Photonics Stress Sensors Active Optical Cable 300 mm Silicon
Collaborate to Innovate FinFET Design Ecosystem Challenges and Solutions
2013 TSMC, Ltd Collaborate to Innovate FinFET Design Ecosystem Challenges and Solutions 2 Agenda Lifestyle Trends Drive Product Requirements Concurrent Technology and Design Development FinFET Design Challenges
Three DIMENSIONAL-CHIPS
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) ISSN: 2278-2834, ISBN: 2278-8735. Volume 3, Issue 4 (Sep-Oct. 2012), PP 22-27 Three DIMENSIONAL-CHIPS 1 Kumar.Keshamoni, 2 Mr. M. Harikrishna
Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni
Emerging Platforms, Emerging Technologies, and the Need for Crosscutting Tools Luca Carloni Department of Computer Science Columbia University in the City of New York NSF Workshop on Emerging Technologies
Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design
Silicon Virtual Prototyping: The New Cockpit for Nanometer Chip Design Wei-Jin Dai, Dennis Huang, Chin-Chih Chang, Michel Courtoy Cadence Design Systems, Inc. Abstract A design methodology for the implementation
BANGLADESH UNIVERSITY OF PROFESSIONALS ACADEMIC CALENDAR FOR MPhil AND PHD PROGRAM 2014 (4 TH BATCH) PART I (COURSE WORK)
BANGLADESH UNIVERSITY OF PROFESSIONALS ACADEMIC CALENDAR FOR MPhil AND PHD PROGRAM 2014 (4 TH BATCH) DAY Soci-Economic and Political History of Bangladesh PART I (COURSE WORK) 1 ST SEMESTER 2 ND SEMESTER
September Real Sector Statistics Division. Methodology
September 2014 Methodology The Consumer Survey has been conducted monthly since October 1999. Moreover, since January 2007 the Survey has involved 4,600 households as respondents (stratified random sampling)
Baseband IC Design Kits for Rapid System Realization
Baseband IC Design Kits for Rapid System Realization Lanbing Chen Cadence Design Systems Engineering Director John Rowland Spreadtrum Communications SVP of Hardware Engineering Agenda How to Speed Up IC
Kotura Analysis: WDM PICs improve cost over LR4
Kotura Analysis: WDM PICs improve cost over LR4 IEEE P802.3bm - 40 Gb/s & 100 Gb/s Fiber Optic Task Force Sept 2012 Contributors: Mehdi Asghari, Kotura Samir Desai, Kotura Arlon Martin, Kotura Recall the
Beyond Soft IP Quality to Predictable Soft IP Reuse TSMC 2013 Open Innovation Platform Presented at Ecosystem Forum, 2013
Beyond Soft IP Quality to Predictable Soft IP Reuse TSMC 2013 Open Innovation Platform Presented at Ecosystem Forum, 2013 Agenda Soft IP Quality Establishing a Baseline With TSMC Soft IP Quality What We
Overview of ITU capacity building activities
Europe Centers of Excellence Steering Committee Meeting Copenhagen, Denmark 12 December 2017 Overview of ITU capacity building activities Mike Nxele Senior Human Capacity Building Officer, Human Capacity
Imputation for missing observation through Artificial Intelligence. A Heuristic & Machine Learning approach
Imputation for missing observation through Artificial Intelligence A Heuristic & Machine Learning approach (Test case with macroeconomic time series from the BIS Data Bank) Byeungchun Kwon Bank for International
Undergraduate Admission File
Undergraduate Admission File June 13, 2007 Information Resources and Communications Office of the President University of California Overview Population The Undergraduate Admission File contains data on
OpenPDK Production Value and Benchmark Results
OpenPDK Production Value and Benchmark Results Philippe MAGARSHACK Executive Vice-President, Design Enablement and Services June 2 nd, 2014 ST s Strong technology portfolio : Several R&D Partnerships &
Integrated Optical Devices
Integrated Optical Devices January 2017 Month 2015 Integrated Optical Devices Is Silicon Photonics a Disruptive Technology? Source: Luxtera with text added by LightCounting 7 Table of Contents Table of
Large scale optical circuit switches for future data center applications
Large scale optical circuit switches for future data center applications ONDM2017 workshop Yojiro Moriand Ken-ichi Sato Outline 1. Introduction -Optical circuit switch for datacenter- 2. Sub-switch configuration
Lab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation
Course Goals Lab Understand key components in VLSI designs Become familiar with design tools (Cadence) Understand design flows Understand behavioral, structural, and physical specifications Be able to
Technology and Manufacturing
Technology and Manufacturing Executive Vice President Field Trip 2006 - London, May 23rd Field Trip 2006 - London, May 23rd Technology Technology Development Centers and Main Programs CMOS Logic Platform
Intel Silicon Photonics: from Research to Product
IEEE Components, Packaging and Manufacturing Technology Chapter, Santa Clara Valley 3/8/2017 Intel Silicon Photonics: from Research to Product MARCH 8, 2017 Ling Liao Principal Engineer Silicon Photonics
Using ASIC circuits. What is ASIC. ASIC examples ASIC types and selection ASIC costs ASIC purchasing Trends in IC technologies
Using ASIC circuits What is this machine? ASIC examples ASIC types and selection ASIC ASIC purchasing Trends in IC technologies 9.3.2004 Turo Piila 1 9.3.2004 Turo Piila 2 What is ASIC Floorplan and layout
D5.1: Packaging and fiber-pigtailing of the 2x2 optical interconnect router
ICT - Information and Communication Technologies Merging Plasmonics and Silicon Photonics Technology towards Tb/s routing in optical interconnects Collaborative Project Grant Agreement Number 249135 D5.1:
The Microprocessor as a Microcosm:
The Microprocessor as a Microcosm: A Hands-On Approach to VLSI Design Education David Harris David_Harris@hmc.edu November 2002 Harvey Mudd College Claremont, CA Outline Introduction Course Organization
Process Design Kit for for Flexible Hybrid Electronics (FHE-PDK)
Process Design Kit for for Flexible Hybrid Electronics (FHE-PDK) Tsung-Ching Jim Huang, PhD Sr. Research Scientist, Hewlett Packard Labs MEPTEC2018 Outline Introduction Modeling and design needs for flexible
2
March 2016 1 2 3 4 5 A. Consumer Confidence Index (CCI) - Consumer Confidence Index (CCI) - Current Economic Condition Index (CECI) - Consumer Expectation Index (CEI) Current Economic Condition Index -
SystemC Standardization Update Including UVM for SystemC Accellera Systems Initiative SystemC Standards Update. Andy Goodrich, Cadence Design Systems
SystemC Standardization Update Including UVM for SystemC Accellera Systems Initiative SystemC Standards Update Andy Goodrich, Cadence Design Systems Presentation Overview Accellera Overview Membership
All Programmable: from Silicon to System
All Programmable: from Silicon to System Ivo Bolsens, Senior Vice President & CTO Page 1 Moore s Law: The Technology Pipeline Page 2 Industry Debates Variability Page 3 Industry Debates on Cost Page 4
Concurrent, OA-based Mixed-signal Implementation
Concurrent, OA-based Mixed-signal Implementation Mladen Nizic Eng. Director, Mixed-signal Solution 2011, Cadence Design Systems, Inc. All rights reserved worldwide. Mixed-Signal Design Challenges Traditional
AirMax VSe High Speed Backplane Connector System
AirMax VSe High Speed Backplane Connector System July 2012 FCI Customer Presentation For External Use Where will AirMax VSe connectors be used & Why? More bandwidth density is being demanded from equipment
Will Silicon Proof Stay the Only Way to Verify Analog Circuits?
Will Silicon Proof Stay the Only Way to Verify Analog Circuits? Pierre Dautriche Jean-Paul Morin Advanced CMOS and analog. Embedded analog Embedded RF 0.5 um 0.18um 65nm 28nm FDSOI 0.25um 0.13um 45nm 1997
Annex A to the MPEG Audio Patent License Agreement Essential Philips, France Telecom and IRT Patents relevant to DVD-Video Disc - MPEG Audio - general
Essential Philips, France Telecom and IRT Patents relevant to DVD-Video Disc - MPEG Audio - general PUBLICATION AR N 013241-317015 04-Jun-90 11-Oct-96 250211 11-Oct-11 Universal subband coder format AT
Work to establish standard ENTSOE STAKEHOLDER COMMITTEE 1
Work to establish standard EN50549-1 EN50549-2 EN50549-10 2017-03-14 ENTSOE STAKEHOLDER COMMITTEE 1 SOMMAIRE Summary Key points TC8X / WG31 01 Schedule1 TC8X / approach1 02 03 Next steps 04 Others considerations1
An Overview of Standard Cell Based Digital VLSI Design
An Overview of Standard Cell Based Digital VLSI Design With examples taken from the implementation of the 36-core AsAP1 chip and the 1000-core KiloCore chip Zhiyi Yu, Tinoosh Mohsenin, Aaron Stillmaker,
Silicon Based Packaging for 400/800/1600 Gb/s Optical Interconnects
Silicon Based Packaging for 400/800/1600 Gb/s Optical Interconnects The Low Cost Solution for Parallel Optical Interconnects Into the Terabit per Second Age Executive Summary White Paper PhotonX Networks
Evolution of CAD Tools & Verilog HDL Definition
Evolution of CAD Tools & Verilog HDL Definition K.Sivasankaran Assistant Professor (Senior) VLSI Division School of Electronics Engineering VIT University Outline Evolution of CAD Different CAD Tools for
ICT PROFESSIONAL MICROSOFT OFFICE SCHEDULE MIDRAND
ICT PROFESSIONAL MICROSOFT OFFICE SCHEDULE MIDRAND BYTES PEOPLE SOLUTIONS Bytes Business Park 241 3rd Road Halfway Gardens Midrand Tel: +27 (11) 205-7000 Fax: +27 (11) 205-7110 Email: gauteng.sales@bytes.co.za
3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA
3D SYSTEM INTEGRATION TECHNOLOGY CHOICES AND CHALLENGE ERIC BEYNE, ANTONIO LA MANNA OUTLINE 3D Application Drivers and Roadmap 3D Stacked-IC Technology 3D System-on-Chip: Fine grain partitioning Conclusion
Improved Circuit Reliability/Robustness. Carey Robertson Product Marketing Director Mentor Graphics Corporation
Improved Circuit Reliability/Robustness Carey Robertson Product Marketing Director Mentor Graphics Corporation Reliability Requirements are Growing in all Market Segments Transportation Mobile / Wireless
Circuits Multi Projets
Circuits Multi Projets MPW Services Center for IC / MEMS Prototyping http://cmp.imag.fr Grenoble France CMP annual users meeting, 4 Feb. 2016, PARIS STMicroelectronics Standard Technology offers at CMP
Versatile Link and GBT Chipset Production
and GBT Chipset Production Status, Issues Encountered, and Lessons Learned Lauri Olanterä on behalf of the and GBT projects Radiation Hard Optical Link Architecture: VL and GBT GBT GBT Timing & Trigger
New Listings. Bullock Russell Market Area. 300 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec
New Listings Bullock Russell Market Area 1200 1100 1000 900 800 700 600 500 400 300 Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec 2014 2015 2016 2017 2018 Closed Sales Bullock Russell Market Area 1000
Quatius Corporation - FTP Site Statistics. Top 20 Directories Sorted by Disk Space
Property Value FTP Server ftp.quatius.com.au Description Quatius Corporation Country Australia Scan Date 03/Sep/2015 Total Dirs 133 Total Files 771 Total Data 9.61 GB Top 20 Directories Sorted by Disk
CIMA Asia. Interactive Timetable Live Online
CIMA Asia Interactive Timetable 2017 2018 Live Online Version 1 Information last updated 09 October 2017 Please note: Information and dates in this timetable are subject to change. CIMA Cert BA Course
Polycom Advantage Service Endpoint Utilization Report
Polycom Advantage Service Endpoint Utilization Report ABC Company 9/1/2018-9/30/2018 Polycom, Inc. All rights reserved. SAMPLE REPORT d This report is for demonstration purposes only. Any resemblance to
Polycom Advantage Service Endpoint Utilization Report
Polycom Advantage Service Endpoint Utilization Report ABC Company 3/1/2016-3/31/2016 Polycom, Inc. All rights reserved. SAMPLE REPORT d This report is for demonstration purposes only. Any resemblance to
Dialog Semiconductor. Capital Markets Day 16 September 2015, London. connected
Dialog Semiconductor Capital Markets Day 16 September 2015, London personal portable connected SmartBond Bluetooth Smart Sean McGrath SVP Connectivity, Automotive and Industrial personal portable connected
Return Path Analog CATV Detector Modules. EPM 705 Series
Return Path Analog CATV Detector Modules EPM 705 Series www.lumentum.com Data Sheet The EPM 705 series are high quality analog photodetectors designed for return path AM CATV applications. These coaxial
Integrated Optical Devices
Integrated Optical Devices May 2018 Integrated Optical Devices 2017 a good year for Silicon Photonics, a fantastic year for integrated InP and GaAs optics Source: Luxtera with text added by LightCounting
Integrated Photonics Grand Challenges and Key Needs for 2018
Integrated Photonics Grand Challenges and Key Needs for 2018 Lionel C. Kimerling MIT AIM Photonics Institute IPSR-International Webinar: December 21, 2017 Data Centers 3D/Augmented Reality/Automotive 5G/IoT
G450C Briefing and Supply Chain Collaboration on 450mm Transition. SEMI Northeast Forum Sept. 11,2013
G450C Briefing and Supply Chain Collaboration on 450mm Transition SEMI Northeast Forum Sept. 11,2013 G450C Background Building 450mm wafer / equipment development environment Consists of 5 member companies
NCC Cable System Order
Syscode 0081 Agency Beacon Media System Name Spectrum/Park Cities, TX Advertiser Ed Meier for Congress $2,421.00 Commission $363.15 Net $2,057.85 198 1 AEN VARIOUS 2/26/18 3/4/18 19:00 24:00 X X X X X
SRC 3D Summit. Bob Patti, CTO
SRC 3D Summit Bob Patti, CTO rpatti@tezzaron.com 1 Advantages Why We Scale? What can 3D do for us? Speed Power Cost Size >180nm 130nm 90nm 65nm 45nm 28nm 22nm 16nm 2 How Real is 3D??? 560μ Samsung 16Gb
Driving the Technology Frontier; Implications on this Cycle Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference
Driving the Technology Frontier; Implications on this Cycle Bank of America Merrill Lynch Taiwan, Technology and Beyond Conference Craig De Young VP Investor Relations and Corporate Communications March
THERMAL GRADIENT AND IR DROP AWARE DESIGN FLOW FOR ANALOG-INTENSIVE ASICS
THERMAL GRADIENT AND IR DROP AWARE DESIGN FLOW FOR ANALOG-INTENSIVE ASICS Pacific MicroCHIP Corp. AIMS-CAT November, 2009 OUTLINE Motivation Thermal Gradient Impact Simulation Methodology Results Accurate
Design Methodologies and Tools. Full-Custom Design
Design Methodologies and Tools Design styles Full-custom design Standard-cell design Programmable logic Gate arrays and field-programmable gate arrays (FPGAs) Sea of gates System-on-a-chip (embedded cores)
A VARIETY OF ICS ARE POSSIBLE DESIGNING FPGAS & ASICS. APPLICATIONS MAY USE STANDARD ICs or FPGAs/ASICs FAB FOUNDRIES COST BILLIONS
architecture behavior of control is if left_paddle then n_state
Design Methodologies. Full-Custom Design
Design Methodologies Design styles Full-custom design Standard-cell design Programmable logic Gate arrays and field-programmable gate arrays (FPGAs) Sea of gates System-on-a-chip (embedded cores) Design
Kaufman Brothers 13 th Annual Investor Conference
Kaufman Brothers 13 th Annual Investor Conference Craig DeYoung, VP Investor Relations New York, New York September 14, 21 / Slide 1 Safe Harbor "Safe Harbor" Statement under the US Private Securities
2
May 2016 1 2 3 4 5 A. Consumer Confidence Index (CCI) - Consumer Confidence Index (CCI) - Current Economic Condition Index (CECI) - Consumer Expectation Index (CEI) Current Economic Condition Index - Current
Section 1.2: What is a Function? y = 4x
Section 1.2: What is a Function? y = 4x y is the dependent variable because it depends on what x is. x is the independent variable because any value can be chosen to replace x. Domain: a set of values
CBERS-2. Attitude Control and its Effects on Image Geometric Correction. Follow up to TCM-06 INPE CBERS TEAM
CBERS-2 Attitude Control and its Effects on Image Geometric Correction Follow up to TCM-06 INPE CBERS TEAM Topics for discussion Known issues about CBERS-2 attitude data Transmitted attitude angles are
Agile Hardware Design: Building Chips with Small Teams
2017 SiFive. All Rights Reserved. Agile Hardware Design: Building Chips with Small Teams Yunsup Lee ASPIRE Graduate 2016 Co-Founder and CTO 2 2017 SiFive. All Rights Reserved. World s First Single-Chip