TUG Combo Board

Transcription

1 TUG Combo Board Overview These notes supplement the Combo Board Manual providing a functional overview of the description and operation of the board. (Note: This Version does not yet fully cover the 6116 option) The Combo board provides a storage facility for up to 16 (2716 or 2732) EPROMs or up to 16 (6116) RAM ICs which are plugged into the 24-Pin Dual-in-line sockets. Figure 1 shows a circuit overview. Figure 1 Combo Module Overview The Peripheral Interface Adaptor (PIA) provides the interface between the Tanbus and the EPROM/RAM address and data lines. The control circuitry detects when the Combo board is being addressed and uses tanbus control and address lines to control the PIA and select the appropriate EPROM/RAM socket. The default addressing range is BD00-BF07. Three alternative addressing ranges are available by wire link selection. Version June 2012

2 Peripheral Interface Adaptors (PIA) At the heart of the Combo board are two 6821 Peripheral Interface Adaptors (PIA). The 6821 PIA can be classed as two separate 8-bit ports with interrupt generating pins in one device. See figure 2 below. Figure Block Diagram Each channel has an 8-bit (byte wide) port and any of those 8 port pins can be configured as an input or output in any configuration. The ports are referred to as "port A" and "port Version June 2012

3 B". The interrupt control lines are CA1 and CA2 for port A and CB1, CB2 for port B. Each channel has three registers. The Data Direction Registers (DDRA and DDRB) determine the direction of the data for each of the 8 bit Peripheral Interfaces. The Output Registers (ORA and ORB) are used for writing data to the Peripheral Interface. The Control Registers (CRA and CRB) allow the device to control the operation of the four interrupt control lines. However Bit 2 in each of the Control Registers (CRA-2 and CRB-2) determines selection of either the Output Register or the corresponding Data Direction Register. A 1 in bit 2 allows access to the Output Register and a 0 causes the the Data Direction Register to be addressed. There are also two Register Select pins (RS0 and RS1) and these two bits determine which of the internal six registers are being read from or written to. RS1 RS0 Control Register Bit CRA-2 CRB-2 Location selected X ORA X DDRA 0 1 X X CRA 1 0 X 1 ORB 1 0 X 0 DDRB 1 1 X X CRB Table Internal Addressing Version June 2012

4 Combo PIA Control Lines The Chip Select and Read/Write controls for each of the two PIAs IC1 and IC2 are addressed from the Microtan Bus as shown in Figure 3 below. This assumes the Combo addressing links are L-K and F-H. Table 2 below shows the resultant decoding Figure 3 - PIA Controls Table 2 PIA Address Decoding Version June 2012

5 Alternative addressing ranges are provided by wire links. Linking H to G instead of F inverts Address line A7 (ie IC2 ORA is addressed by BD80). Linking K to J instead of L inverts Address line A3 (ie IC2 ORA is addressed by BF08). PIA to EPROM/ RAM Mapping Table 3 below shows the PIA mapping to the EPROM / 6116 RAM / PLG interfaces PIA Port PLG CA1 2 CA2 3 PA0 'Chip select' Enable 14 PA1 WE 1 PA2 8 PA3 9 PA4 10 PA5 11 IC1 PA6 12 PA7 13 PB0 O0 O0 I/O 0 PB1 O1 O1 I/O 1 PB2 O2 O2 I/O 2 PB3 O3 O3 I/O 3 PB4 O4 O4 I/O 4 PB5 O5 O5 I/O 5 PB6 O6 O6 I/O 6 PB7 O7 O7 I/O 7 PIA Port PA0 A0 A0 A0 PA1 A1 A1 A1 PA2 A2 A2 A2 PA3 A3 A3 A3 PA4 A4 A4 A4 PA5 A5 A5 A5 PA6 A6 A6 A6 PA7 A7 A7 A7 IC2 PB0 A8 A8 A8 PB1 A9 A9 A9 PB2 A10 A10 A10 PB3 A11 A A PB4 B A B PB5 C B C PB6 D C D PB7 D Chip Select EPROM/RAM Addressing Data Expansion Table 3 PIA to EPROM/RAM/PLG Mapping Version June 2012

6 PIA Initialisation and control Out of reset, the PIA will always configure itself to both ports being inputs and all interrupts disabled. To set up the 2 PIAs as above using 6502 assembly : ORA1 EQU $BD04 ;EPROM/RAM Chip select and Write Enable DDRA1 EQU $BD04 CRA1 EQU $BD05 ORB1 EQU $BD06 ;EPROM/RAM Data DDRB1 EQU $BD06 CRB1 EQU $BD07 ORA2 EQU $BD00 ;EPROM/RAM Address Lo DDRA2 EQU $BD00 CRA2 EQU $BD01 ORB2 EQU $BD02 ;EPROM/RAM Address Hi DDRB2 EQU $BD02 CRB2 EQU $BD03 ;Initialise the IC1 PIA ;Initialise the IC2 PIA LDA #$0 STA CRA1 ;Access Port A Direction Register (ie set bit 2 = 0) STA CRB1 ;Access Port B Direction Register (ie set bit 2 = 0) STA DDRB1 ;Set all DDRB1 bits to input (EPROM/RAM Data) LDA #$FF STA DDRA1 ;Set all DDRA1 bits to output (Chip Select / Write Enable) LDA #$04 STA CRA1 ;Access Port A Output Register (ie set bit 2 = 1) STA CRB1 ;Access Port B Output Register (ie set bit 2 = 1) LDA #$FE STA ORA1 ;Enable Chip Select. Disable Write Enable (bit 0 = 0) LDA #$0 STA CRA2 ;Access Port A Direction Register (ie set bit 2 = 0) STA CRB2 ;Access Port B Direction Register (ie set bit 2 = 0) LDA #$FF STA DDRA2 ;Set all DDRA2 bits to output (EPROM/RAM Address Lo) STA DDRB2 ;Set all DDRB2 bits to output (EPROM/RAM Address Hi) LDA #$04 STA CRA2 ;Access Port A Output Register (ie set bit 2 = 1) STA CRB2 ;Access Port B Output Register (ie set bit 2 = 1) ;Example: read data at Combo Board location $072F (ESC Option) LDA #$2F STA ORA2 ;Store address lo byte in ORA2 LDA #$07 STA ORB2 ;Store address hi byte in ORB2 LDA ORB1 ;Read data from ORB1 Version June 2012

7 ;Example: write byte $33 at Combo Board location $072F (6116 Option only) LDA #$0 STA CRB1 ;Access IC1 Port B Direction Register (ie set bit 2 = 0) LDA #$FF STA DDRB1 ;Set all DDRB1 bits to output (EPROM/RAM Data) LDA #$2F STA ORA2 ;Store address lo byte in ORA2 LDA #$07 STA ORB2 ;Store address hi byte in ORB2 LDA #$33 STA ORB1 ;Write data to ORB1 LDA #$00 STA ORA1 ;Enable Chip Select and Write Enable LDA #$FF STA ORA1 ;Disable Chip Select and Write Enable ;Example:. and then read the data back from Combo Board location $072F LDA #$0 STA CRB1 ;Access IC1 Port B Direction Register (ie set bit 2 = 0) STA DDRB1 ;Set all DDRB1 bits to input (EPROM/RAM Data) LDA #$00 STA ORA1 ;Enable Chip Select and Write Enable LDA #$2F STA ORA2 ;Store address lo byte in ORA2 LDA #$07 STA ORB2 ;Store address hi byte in ORB2 LDA ORB1 ;Read data from ORB1 LDA #$FF STA ORA1 ;Disable Chip Select and Write Enable Version June 2012

8 EPROM/RAM Chip Selection The PB3 PB7 Port to Chip Select mapping is provided by wire links and IC3 (4 to 16 line decoder) as shown in Figure 4 below. Sockets 1-16, Pin 21 +ve PB3 PB4 PB5 PB6 PB7 5v A A B B C C D D E R A B C D IC3 74LS154 74LS159 Socket 1 pins 18 &20 Socket 2 pins 18 &20 Socket 3 pins 18 &20 Socket 4 pins 18 &20 Socket 5 pins 18 &20 Socket 6 pins 18 &20 Socket 7 pins 18 &20 Socket 8 pins 18 &20 Socket 9 pins 18 &20 Socket 9 pins 18 &20 Socket 10 pins 18 &20 Socket 11 pins 18 &20 Socket 12 pins 18 &20 Socket 13 pins 18 &20 Socket 14 pins 18 &20 Socket 15 pins 18 &20 Socket 16 pins 18 &20 Figure 4 Chip Selection Table 4 below shows the links for the EPROM/RAM configurations EPROM 2732 EPROM 6116 RAM 5v A A A B B B C C C D D D E Table 4 Chip Select Link Configurations IC3 is enabled when its pin 18 is low. Normally pin 18 is held high via R21, but may taken low under software control by PIA1 Output Port PA0. Version June 2012

9 EPROM Storage Card (ESC) Configuration If the Combo board is fitted with 2716 or 2732 EPROMs, then IC3 is a 74LS154 and the following components may be omitted: Battery Circuit (ie Battery, D2 & R22) Pull-up resistors R5-20 Switch 1 / 2 (replaced with wire link) Diode D1 (replaced with wire link) The linking shown in Table 4 puts 5v on pin 21 on 2716 EPROMs and A11 addressing signal on 2732 EPROMs. RAM Storage Card (6116) Configuration If the Combo board is fitted with 6116 RAM chips, then IC3 must be a 74LS159 (4 to 16 line Decoder with open collector outputs). Pull-up resistors R5-20 must therefore be fitted. In this configuration Pin 21 of the 6116 RAM is held high by R4. When it is taken low by PIA1 Output Port PA1 (via Switch 1 / 2), the RAM is 'Write Enabled'. When SW 1 / 2 is open, the RAM is manually 'write protected'. The battery circuit provides power to all the RAM sockets, the 16 pull-up resistors and R4. Thus the stored data is retained when the Combo board is powered down. When 5v supply is available, the battery is charged via D1 and R22. Version June 2012

10 Appendix A EPROM / 6116 RAM Pin-outs Version June 2012