RECONFIGURABLE ARCHITECTURE OF 2D- ADAPTIVE MEDIAN FILTER BASED IMAGE DENOISING

Transcription

1 RECONFIGURABLE ARCHITECTURE OF 2D- ADAPTIVE MEDIAN FILTER BASED IMAGE DENOISING P.Karthikeyan Department of Electronics and Communication Engineering Velammal college of Engg & tech Madurai, India S.Vasuki Department of Electronics and Communication Engineering Velammal college of Engg &tech Madurai, India Ancila.D Department of Electronics and Communication Engineering Velammal college of Engg &tech Madurai, India Abstract This paper proposes an FPGA implementation for 2Dadaptive median filter. Adaptive median filters exhibit high efficient filtering properties than standard median filter. An Impulse noise removal with adaptive filtering approach is adopted to restore images corrupted by salt & pepper noise. This method uses an implementation of an adaptive median filter to illustrate the process of converting MATLAB algorithms for HDL code generation. The adaptive median filter is chosen for hardware implementation because it has been proved to be an efficient filter for salt & pepper noise. Hardware implementations of the filters are highly desirable due to the algorithm s computation complexity and high throughput requirements. By implementing adaptive median filter using Spartan 6 FPGA, high efficient, low power consumption, high speed device is obtained. Keywords adaptive median filter; salt and pepper; FPGA; I. INTRODUCTION Image denoising is the process of removing the noise that perturbs image quality. It is an important image processing technique, both as a process, and other processes component. The main properties of a good image denoising model is that it will remove noise while preserving the edges.denoising is important for post processing methods like segmentation, classification, object recognition, pattern analysis etc.in this context the denoising of the image is done by adaptive median filter. Normally when compare to median filter adaptive median filter is high efficient in its property [7] Due to the imperfections of image sensors, images are often corrupted by noise. The impulse noise is the most frequently referred type of noise. In most cases, impulse noise is caused by malfunctioning pixels in camera sensors, faulty memory locations in hardware, or errors in the data transmission. We distinguish two common types of impulse noise; the salt and pepper noise (commonly referred to as intensity spikes or speckle) and the random valued shot noise. For images corrupted by salt-and-pepper noise, the noisy pixels can take only the maximum or minimum values. In case of the random valued shot noise, the noisy pixels have an arbitrary value. It is very difficult to remove this type of noise using linear filters because they tend to smudge resulting images. [1] [3][5] The median filter is a nonlinear digital technique, often used to remove noise. Such noise reduction is a typical preprocessing step to improve the results of later processing.although median filter is a useful non-linear image smoothing and enhancement technique. It also has some disadvantages. The median filter removes both the noise and the fine detail since it can't differentiate between the two, anything relatively small in size compared to the size of the neighborhood will have minimal affect on the value of the median, and will be filtered out. In other words, the median filter can't distinguish fine detail from noise. Therefore the adaptive median filtering [2][3] has been applied widely as an advanced method compared with standard median filtering. The Adaptive Median Filter performs spatial processing to determine which pixels in an image have been affected by impulse noise. The Adaptive Median Filter classifies pixels as noise by comparing each pixel in the image to its surrounding neighbor pixels. The size of the neighborhood is adjustable, as well as the threshold for the comparison. A pixel that is different from a majority of its neighbors, as well as being not structurally aligned with those pixels to which it is similar, is labeled as impulse noise. These noise pixels are then replaced by the median pixel value of the pixels in the neighborhood that have passed the noise labeling test. In this paper matlab HDL coder is used. It integrates MATLAB algorithms into a Simulink model for C or HDL code generation. However, many MATLAB implementations of signal processing, communications, and image processing algorithms require some redesign to make them suitable for HDL code generation. For example, they often use data types such as doubles, strings, and structures, and contain control flow constructs, such as while loops and break statements, which do not map well to hardware [4]. Apart from these constructs, MATLAB algorithms that operate on large data sets are not always written to take account of hardware design characteristics like streaming and resource sharing. This [Page No. 4510]

2 article uses a typical software implementation of an adaptive median filter to illustrate the process of converting MATLAB algorithms for HDL code generation. The use of configurable hardware and system level programming languages allow direct implementation of image processing algorithms with improved performances and with a short time-to-market interval. There are many technologies available for hardware implementation. Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA s) are both reconfigurable devices able to support techniques such parallelism and pipelining [6]. The use of reconfigurable hardware to implement algorithms for image processing minimizes the time-to market cost while rapid prototyping with simplified debugging and verification stages is also possible. Therefore, the reconfigurable devices seem to be the ideal choice for implementation of image processing algorithms. Field Programmable Gate Arrays have traditionally been configured by hardware designers using specific so called Hardware Design Languages (HDLs)[6]. The main advantage of using HDLs to simulate digital processing of any logical inputs is related with the possibility of an immediate FPGA based hardware implementation. Since the HDL syntax is always related to a hardware structure, the timing information of the potential hardware implementation is also available allowing specific speed optimizations. Out of that, the use of HDLs means hardware portability and on the fly re-programmability. The main challenge is to transpose the validated algorithms into a non-programming language as hardware description languages are. Also, the input and output data files need to be reshaped to match the binary content permitted into the hardware simulators. Interesting results are obtained in video processing as is presented in the paper. [6] Xilinx System Generator provides a set of Simulink blocks (models) for several hardware operations that could be implemented on various Xilinx FPGAs. These blocks can be used to simulate the functionality of the hardware system using Simulink environment. The nature of most DSP applications requires floating point format for data representation. While this is easy to implement on several computer systems running high level modeling software such as Simulink, it is more challenging in the hardware world due to the complexity of the implementation of floating point arithmetic. These challenges increase with portable DSP systems where more restricting constraints are applied to the system design. For these reasons Xilinx System Generator uses fixed point format to represent all numerical values in the system. System generator provides some blocks to transform data provided from the software side of the simulation environment (in our case it is Simulink) and the hardware side (System Generator blocks). This is an important concept to understand during the design process using Xilinx System Generator. [8] II. ADAPTIVE MEDIAN FILTER Adaptive median filtering is a digital image processing technique commonly used to reduce speckle noise and salt-and-pepper noise. A generic median filter replaces the current pixel value with the median of its neighboring pixel values; it affects all the pixels, whether or not they are noisy, and hence, blurs images with high noise content. The adaptive median filter overcomes this limitation by selectively replacing the pixel values. It makes the decision by analyzing the median. If the median is skewed by the noise, it adapts itself by defining the median over larger regions. 1) For each pixel in the image calculate the median value in a surrounding neighborhood of the pixel. 2) Compare the median to a threshold and decide to either replace the pixel, keep the pixel, or increase the neighborhood size and recalculate. 3) Only affects image pixels determined to have noise content 4) Performs well for low or high noise densities III. EXISTING METHOD The current version of the algorithm is implemented in MATLAB for C code generation.the algorithm takes the whole input image, I, as input, operates on the data in double precision, and returns the denoised image, J, as output. The core of the algorithm is implemented in three levels of nested loops operating on the entire image. The two outer loops iterate over the rows and columns of the image. The innermost loop implements the adaptive nature of the filter by comparing the median to a threshold and deciding whether to replace the pixel or increase the neighborhood size and recalculate the median [4]. The algorithm uses four neighborhood sizes: 3x3, 5x5, 7x7, and 9x9. Even though the current implementation contains constructs and paradigms typical in software implementations and is efficient for soft-ware, in its current form it is not suitable for hardware synthesis, for the following reasons: The algorithm operates on the entire image: Typical hardware implementations stream the data into the chip in small chunks called windows or kernels to reduce the chip I/O count; the data is processed at a faster rate, and the chip finishes processing an entire frame of data before the next frame is available. The algorithm uses double data types: Double data types are not efficient for hardware realization. Hardware implementations must use silicon area efficiently and avoid usage of double-precision arithmetic, which consumes more area and power. The algorithm should use fixed-point data types as opposed to floating-point data types (double). The algorithm uses expensive math functions: The use of operators like sin, divide, and modulo on variables leads to inefficient hardware. The implementation of these functions in hardware results in low clock frequencies. For hardware design tradeoffs, we need to use low-cost repetitive add or subtract based algorithms, such as CORDIC. Software loops in the algorithm must be mapped [Page No. 4511]

3 efficiently to hardware: Since hardware execution needs to be deterministic, we cannot allow loops with dynamic bounds. Hardware is parallel, which means that we could unroll the loop execution in hardware to increase concurrency, but this uses up more silicon area. The algorithm contains large arrays and matrices: When mapped to hardware, large arrays and matrices consume area resources like registers and RAMs. IV. ADAPTIVE MEDIAN FILTER ALGORITHM FOR RECONFIGURABLE HARDWARE The process of converting the original adaptive median algorithm to hardware involves the following tasks: 1) Serializing the input image for processing 2) Separating the adaptive median filter computation for parallelization 3) Updating the original image using the denoised pixel values A. Serializing The Input Image Most hardware algorithms do not work on the whole image but on smaller windows at each time step. As a result, the original input image must be serialized and streamed into the chip and, depending on how much of the image needs to be available for the algorithm computation, buffered onto the onchip memory. This hardware modeling of the algorithm must take into account the amount of memory available to hold the image data, in addition to the number of I/O pins available on the chip to stream the data in. In this example, serialization involves restructuring the Simulink model so that adaptive filter design breaks the image into 9x1 columns of pixel data and feeds it as input to the filter. The data is buffered inside the chip for 9 cycles, creating a 9x9 window to compute a new center pixel. The filter processes the window of data and streams a modified center pixel value for the 9x9 window. At the output of the filter, the modified center pixel data is applied to the original image to reconstruct a denoised image. Now that the filter is working on smaller windows of data, it needs to run at a faster rate to finish processing the whole algorithm on the image before the next image is available at the input. The model of this algorithm behavior using rate transition blocks. This sort of image buffering would require additional control signals for the streaming of data to be processed by the algorithm implemented in the hardware. In this model the (Fig 1) subsystem capture column data helps to sweep through the image, and in 9x1 windows, feeds the data to the main Filter subsystem. Since the 2D adaptive median filter works on a maximum window size of 9x9, it takes 9 cycles to fill the filter pipeline at the beginning of each row of images and compute the first center pixel. This means we need additional control signals at the output of the filter to indicate the validity of the center pixel output. At the output of the filter, the subsystem update image takes the filtered data from the MedianFilter_2D_HW subsystem and reconstructs the full image based on the control signals. Fig 1: Simulink model of an adaptive median filter, set up for HDL code generation B. Paralleizing the algorithm The adaptive median filter is based on its selection of a window size for calculating the median on local statistics. The software oriented implementation computes these statistics for each window size sequentially in nested loops. The hardware implementation can perform these computations in parallel. The new filter implementation partitions the data buffer into 3x3, 5x5, 7x7, and 9x9 regions and implements separate median filters to compute the minimum, median, and maximum values for each subregion in parallel(fig 2). Parallelizing the window computations lets the filter perform faster in hardware. Fig 2: Implementation of the adaptive median filter C. Optimizing the Algorithm for Hardware To find the minimum, median, and maximum values of the neighboring pixels, the nested loops in the software implementation iterate over all the rows from left to right and top to bottom. In the hardware friendly implementation, min/max/median computation occurs only on the regions of interest, identified using a 1D median filter. (Fig 3) shows computation of min/max/median values for a 3x3 window; as can be seen, an nxn region of pixels re-quires {N 2 * floor (log 2 N 2 /2)} number of comparators. Fig 3:Algorithm for computing max/min/median for 3x3 window [Page No. 4512]

4 To implement the algorithm on 3x3, 5x5, 7x7, and 9x9 windows, we would require a total of 4752 (9*4 + 25* * *40) comparators shown in Table. I and its utilization is 51% in which the area is optimized in a high efficient manner. TABLE I:1D ADAPTIVE MEDIAN FILTER RESOURCE USAGE Region Stages Comparator Total 3x x x x It can explore other area tradeoffs for example, we can implement a 2D filtering algorithm that works on individual rows and columns of the nxn region rather than on all the pixels. This would consume fewer resources than the 1D filter d would require 800 comparators ( ) instead of However, because we know that the center pixel values are usually found in the 3x3 region, we could compromise on quality by applying the lossy 2D algorithm on other regions while applying the 1D algorithm on the 3x3 region. To experiment with these tradeoffs we simply swap the call to functions on the path 1d with 2d and simulate the model to compare the noise reduction differences between different choices. The output pixel of this algorithm is used to denoise the original image it is shown in (Fig 4). Fig 5: Optimized adaptive median filter Table II provides the results of design summary of the optimized filter and it determines the utilization of the slices, LUTs and flipflops. TABLE II: DESIGN UTILIZATION OF ADAPTIVE MEDIAN FILTER SLICE LOGIC UTILIZATION USED AVAILABLE UTILIZATION ` NO OF LUTs ,288 34% NO USED AS LOGIC ,288 33% NO OF OCUPIED SLICE ,822 51% NO OF UNUSED FLIPFLOP ,433 95% NO OF UNUSED LUT 74 9,433 1% Fig 4: Original Image with noise and Filtered Image D.Results and Discussion The optimization of adaptive median filters is described in VHDL by HDL code generation and synthesized using Xilinx ISE 14.7 tools to Spartan 6 X6SLX45 FPGA. The optimized adaptive median filter is shown in (Fig 5) which consists of different type of LUTs.The implementation costs are expressed in terms of slices. The FPGA contains 6,822 slices each containing four 6-input LUTs and eight flipflops. This implementation occupies 3,546 out of 6,822 slices Totally there are 27,288 LUTs present in the FPGA and only 9,359 LUTs used which is around 34%.Number of LUTs used as logic is 33% all these utilization provides high area efficiency. (Fig 6,7,8,9,10) shows the internal design of different types of LUTs mainly LUT3,LUT5 and LUT6 are used and they are named as follows E4,FDFDFDA8, , , DF5DDFDF , BFOFB303B000B000. About 9057 LUTs are used as logic, out of 27,288 availability the output 6 occupies 5,943 and both the output 5 and 6 occupies 3,114. The peak memory usage is upto 400 MB. [Page No. 4513]

5 Fig 6: Design of LUT Fig 10: Design of LUT6 DF5DDFDF Fig 7: Design of LUT5 FDFDFDA8 Fig 11: Design of LUT6 BFOFB303B000B000 Fig 8: Design of LUT5 The power analysis of this design is verified by the tool Xilinx Xpower Analyzer, consumption of the power can be determine with respect to the thermal properties such as effective TJA 22.6, Max Ambient 84.2C, junction temperature 25.6.The total power consumed are based on the utilization of logic and IOs is and the other details are shown in the (Fig 12). While analyzing the synthesis of the optimized design the consumption of power is low. Fig 9: Design of LUT Fig 12: Result of power analyzer [Page No. 4514]

6 V. CONCLUSION Using HDLs for image processing is a quite new approach, extending the field of digital design to image processing simulation. Reconfigurable hardware has been developed for an adaptive median filter to denoise the image using HDL coder, MATLAB and Simulink.The adaptive median filter is described in about 186 lines of MATLAB code. A comparable C-code implementation would require almost 1000 lines; an HDL implementation, more than 2000 lines. Understanding the modeling tradeoff between hardware and software is key for efficient implementation of complex signal and video processing algorithms. MATLAB and Simulink explore these tradeoffs at a high level of abstraction without encoding too much hardware detail, providing an effective way to use the MATLAB environment for hardware deployment. Xilinx ISE 14.7 tool plays a major role to obtain the optimization and synthesis of the adaptive median filter. The approach, proposed for implementing adaptive median filter in FPGA reduces the area and power. Experimental result confirms the performance of design implementation of adaptive median filter in an efficient way. REFERENCES [1] Zdenek Vasicek and Lukas Sekanina Novel Hardware Implementation of Adaptive Median Filters IEEE International Conference on Computer Vision, Bombay [2] Chin-Chen Chang, Ju-Yuan Hsiao and Chih-Ping Hsieh An Adaptive Median Filter for Image Denoising Second International Symposium on Intelligent Information Technology Application. [3] Sayed. A Hadei, and M lotfizad A Family of Adaptive Filter Algorithms in Noise Cancellation for Speech Enhancement International Journal of Computer and Electrical Engineering, Vol. 2, No. 2, April [4] Kiran Kintali Converting MATLAB Algorithms into Serialized Designs for HDL Code Generation. [5] Mamta Juneja and Rajni Mohana An Improved Adaptive Median Filtering Method for Impulse Noise Detection International Journal of Recent Trends in Engineering, Vol 1, No. 1, May 2009 [6] Iuliana Chiuchisan, Marius Cerlinca, Alin-dan Potorac, Adrian Graur Image Enhancement Methods Approach using Verilog Hardware Description Language 11th International Conference on DEVELOPMENT AND APPLICATION SYSTEMS, Suceava, Romania, May 17-19, 2012 [7] Fernanda Palhano Xavier de Fontes,Guillermo Andrade Barroso,Pierrick Coupe,Pierre Hellier Real time ultrasound image denoising Springer-Verlag 2010 [8] Ahmed Elhossini Using Xilinx System Generator 13.2 for Co- Simulation on Digilent NEXYS3 (Spartan-6) Board February 22, 2013 [Page No. 4515]