ECE Exam I February 19 th, :00 pm 4:25pm

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1 ECE 3056 Exam I February 19 th, :00 pm 4:25pm 1. The exam is closed, notes, closed text, and no calculators. 2. The Georgia Tech Honor Code governs this examination. 3. There are 4 questions and 16 pages including two blank worksheets, the opcode table, and the register name table. Make sure you have all of them. 4. Please write/draw legibly. Use the work sheets for generating the solutions before providing the final answer. I cannot give any credit if I cannot read your handwriting. You cannot be given credit for such omissions after the exam has been graded. 5. State any assumptions you feel you have to make or ask for clarification. Your answers will be graded in accordance with those assumptions if the question is unclear and your assumptions are reasonable. 6. Keep in mind it is difficult to give partial credit without written material. Please make sure you document any partial solutions. 7. The exam is 85minutes. 8. Points are shown next to each problem. Plan your work! Problem Max Total 100 Student Name: Student Number:

2 Problem Grades Problem Max Graded Total 100

3 1. (35 pts) Consider the following block of SPIM code. The text segment starts at 0x and the data segment starts at 0x data first:.word 1,0,1,0,1,0,1, 0.word 1,0,1,0,1,0,1, 0.word 1,0,1,0,1,0,1, 0.word 1,0,1,0,1,0,1, 0.word 1,0,1,0,1,0,1, 0.word 1,0,1,0,1,0,1, 0.word 1,0,1,0,1,0,1, 0.word 1,0,1,0,1,0,1, last:.word 0.text.globl main main: la $t0, first #load start address of array la $t1, last #load end address of the array addi $t1, $t1, 4 #point to first word after the array li $t2, 0 #initialize count using immediate add $t3, $zero, $zero #initialize sum using another approach loop: lw $t4, 0($t0) #fetch array element add $t3, $t3, $t4 #update sum addi $t0, $t0, 4 #point to next word addi $t2, $t2, 1 #increment count bne $t1, $t0, loop #if not done, start next iteration li $v0, 10 syscall a) (10 pts) Provide the hexadecimal encodings of the following lw $t4, 0($t0) bne $t1, $t0, loop

4 b. (5 pts) Is the above code relocatable? Explain. c. (10 pts) The following is the binary representation of a block of assembled SPIM code. Disassemble the program producing the original SPIM instructions. Use the opcode map at the end of this exam. Assembled Binary 0x x2129ffff 0x1520fffc MIPS Instruction d. (6 pts) Consider a jal instruction stored at address 0x Determine whether each of the following addresses can be a target of this instruction, i.e., the starting location of the procedure. You must justify your answer to receive credit. i. 0x ii. 0x e. (4 pts) What will be contained in the symbol table after assembly?

5 2. (10 pts) Consider the 32-bit ALU design discussed in class and shown below. Note that it supports the beq instruction. Now suppose that we wished to similarly add hardware support for ble $t0, $t1, loop the branch-on-lessthan-or-equal-to instruction. Clearly show i) the necessary changes to the ALU hardware, ii) list the corresponding values of the ALU control signals for this instruction, and iii) describe briefly (in a sentence or two) how the single cycle datapath would operate with these changes. Bnegate Operation Binvert Operation Carryin a0 b0 CarryIn ALU0 Less CarryOut Result0 a 0 1 Result a1 b1 0 CarryIn ALU1 Less CarryOut Result1 Zero b Less 3 a2 b2 0 CarryIn ALU2 Less CarryOut Result2 Carryout a31 b31 0 CarryIn ALU31 Less Result31 Set Overflow Instruction Binvert Operation ble

6 3. (25 pts) Consider the single cycle SPIM datapath shown overleaf. You wish to add a new instruction - dcb $t0, loop decrement-and-branch-on-zero. This instruction will first decrement the register $t0 by 1 and then branch to the label loop if the result is 0. Register $t0 is updated with the decremented value. a. (10 pts) Clearly show the hardware modifications on the datapath. [To receive any credit your modifications must be legible] b. (10 pts) Fill in the truth table below for the single cycle data path including any changes to accommodate the new instruction Instr. RegDst AluSrc MemToReg RegWrite MemRead MemWrite Branch AluOp R- format lw sw beq c. (5 pts) Assuming the opcode for the new instruction is , show the modifications required to the controller hardware below for the new instruction. Make and state any assumptions you need. Inputs Op5 Op4 Op3 Op2 Op1 Op0 R-format Iw sw beq Outputs RegDst ALUSrc MemtoReg RegWrite MemRead MemWrite Branch ALUOp1 ALUOpO

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8 4. (30 pts) Consider the execution of the following block of SPIM code on a multicycle datapath. Assume that the fetch cycle for the first instruction is cycle number 0. Assume that i) all immediate instructions require the same number of states as an add instruction, ii) all branch instructions require the same number of states as a beq instruction. Text starts at 0x and the data segment starts at 0x # a simple counting for loop and a conditional if-then-else statement.data L1:.word 0x44,22,33,55 main: loop:.text.globl main lui $t0, 0x1001 li $t1, 4 add $t2, $t2, $zero lw $t3, 0($t0) add $t2, $t2, $t3 addi $t0, $t0, 4 addi $t1, $t1, -1 bne $t1, $zero, loop bgt $t2, $0, then move $s0, $t2 j exit then: move $s1, $t2 exit: li $v0, 10 syscall a. (5 pts) What is the contents of ALUOut after cycle number 14 completes? Why? b. (15 pts) Fill in the following values during the requested cycle (remember the first cycle is cycle number 0!). Cycle ALUOp ALUSrcB IRWrite RegWrite MemToReg PCSource 10 18

9 c. (10 pts) Consider the multi-cycle data path and assume each state consumes the same amount of energy E joules, and that the bne instruction takes the same number of cycles as the beq instruction. Now consider that the data path executes at 1 GHZ. Compare the power dissipation of each loop. Your answer must include the computation of the power executed by each loop. Loop1: lw $t3, 0($t0) add $t2, $t2, $t3 addi $t0, $t0, 4 addi $t1, $t1, -1 bne $t1, $zero, Loop1 Loop2: lw $t3, 0($t0) add $t2, $t2, $t3 addi $t0, $t0, 4 bne $t0, $t4, Loop2

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11 Appendix: Opcode Table & Registers These tables list all of the available operations in MIPS. For each instruction, the 6-bit opcode or function is shown. The syntax column indicates which syntax is used to write the instruction in assembly text files. Note that which syntax is used for an instruction also determines which encoding is to be used. Finally the operation column describes what the operation does in pseudo-java plus some special notation as follows: "MEM [a]:n" means the n bytes of memory starting with address a. The address must always be aligned; that is, a must be divisible by n, which must be a power of 2. "LB (x)" means the least significant 8 bits of the 32-bit location x. "LH (x)" means the least significant 16 bits of the 32-bit location x. "HH (x)" means the most significant 16 bits of the 32-bit location x. "SE (x)" means the 32-bit quantity obtained by extending the value x on the left with its most significant bit. "ZE (x)" means the 32-bit quantity obtained by extending the value x on the left with 0 bits. Arithmetic and Logical Instructions Instruction Opcode/Function Syntax Operation add ArithLog $d = $s + $t addu ArithLog $d = $s + $t addi ArithLogI $t = $s + SE(i) addiu ArithLogI $t = $s + SE(i) and ArithLog $d = $s & $t andi ArithLogI $t = $s & ZE(i) div DivMult lo = $s / $t; hi = $s % $t divu DivMult lo = $s / $t; hi = $s % $t mult DivMult hi:lo = $s * $t multu DivMult hi:lo = $s * $t nor ArithLog $d = ~($s $t) or ArithLog $d = $s $t ori ArithLogI $t = $s ZE(i) sll Shift $d = $t << a sllv ShiftV $d = $t << $s sra Shift $d = $t >> a srav ShiftV $d = $t >> $s srl Shift $d = $t >>> a

12 srlv ShiftV $d = $t >>> $s sub ArithLog $d = $s - $t subu ArithLog $d = $s - $t xor ArithLog $d = $s ^ $t xori ArithLogI $d = $s ^ ZE(i) Constant-Manipulating Instructions Instruction Opcode/Function Syntax Operation lhi LoadI HH ($t) = i llo LoadI LH ($t) = i Comparison Instructions Instruction Opcode/Function Syntax Operation slt ArithLog $d = ($s < $t) sltu ArithLog $d = ($s < $t) slti ArithLogI $t = ($s < SE(i)) sltiu ArithLogI $t = ($s < SE(i)) Branch Instructions Instruction Opcode/Function Syntax Operation beq Branch if ($s == $t) pc += i << 2 bgtz BranchZ if ($s > 0) pc += i << 2 blez BranchZ if ($s <= 0) pc += i << 2 bne Branch if ($s!= $t) pc += i << 2 Jump Instructions Instruction Opcode/Function Syntax Operation j Jump pc += i << 2 jal Jump $31 = pc; pc += i << 2 jalr JumpR $31 = pc; pc = $s jr JumpR pc = $s Load Instructions Instruction Opcode/Function Syntax Operation lb LoadStore $t = SE (MEM [$s + i]:1) lbu LoadStore $t = ZE (MEM [$s + i]:1) lh LoadStore $t = SE (MEM [$s + i]:2) lhu LoadStore $t = ZE (MEM [$s + i]:2) lw LoadStore $t = MEM [$s + i]:4 Store Instructions

13 Instruction Opcode/Function Syntax Operation sb LoadStore MEM [$s + i]:1 = LB ($t) sh LoadStore MEM [$s + i]:2 = LH ($t) sw LoadStore MEM [$s + i]:4 = $t Data Movement Instructions Instruction Opcode/Function Syntax Operation mfhi MoveFrom $d = hi mflo MoveFrom $d = lo mthi MoveTo hi = $s mtlo MoveTo lo = $s Exception and Interrupt Instructions Instruction Opcode/Function Syntax Operation trap Trap Opcode Map: Bits 31:26 of the instruction Table of opcodes for all instructions: REG j jal beq bne blez bgtz 001 addi addiu slti sltiu andi ori xori llo lhi trap 100 lb lh lw lbu lhu 101 sb sh sw FUNC Code Field (Bits 5:0) of the Instruction Table of function codes for register-format instructions: sll srl sra sllv srlv srav 001 jr jalr 010 mfhi mthi mflo mtlo 011 mult multu div divu Dependent on operating system; different values for immed26 specify different operations. See the list of traps for information on what the different trap codes do.

14 100 add addu sub subu and or xor nor 101 slt sltu Name Register number Usage $zero 0 the constant value 0 $v0-$v1 2-3 values for results and expression evaluation $a0-$a3 4-7 arguments $t0-$t temporaries $s0-$s saved $t8-$t more temporaries $gp 28 global pointer $sp 29 stack pointer $fp 30 frame pointer $ra 31 return address

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