CISC 662 Graduate Computer Architecture. Lecture 4 - ISA MIPS ISA. In a CPU. (vonneumann) Processor Organization

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1 CISC 662 Graduate Computer Architecture Lecture 4 - ISA MIPS ISA Michela Taufer Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture, 4th edition ---- Additional teaching material from: Jelena Mirkovic (U Del) and John Kubiatowicz (UC Berkeley) PC 4 ALU Instruction cache IM NPC IR Reg In a CPU A B Sign extend Imm Zero? M U X M U X ALU opcode Cond ALU Output M U X Data cache DM Cond LMD M U X opcode (vonneumann) Processor Organization Control needs to: CPU Memory Devices 1. input instructions from Memory 2. issue signals to control the information flow between the Datapath components and to control what operations they Control Datapath Input Output perform Fetch 3. control instruction sequencing Datapath needs to have the: components the functional units and Exec Decode storage (e.g., register file) needed to execute instructions interconnects - components connected so that the instructions can be accomplished and so that can be loaded from and stored to Memory To main memory To main memory

2 MIPS R3000 Instruction Set Architecture (ISA) Instruction Categories Computational Load/Store Jump and Branch Floating Point - coprocessor Memory Management Special 3 Instruction Formats: all bits wide OP OP OP Registers: all bits wide R0 - R31 PC HI LO rs rt rd sa funct rs rt immediate jump target R format I format J format MIPS Register Convention Name Register Number Usage Preserve on call? $zero 0 constant 0 (hardware) n.a. $at 1 reserved for assembler n.a. $v0 - $v1 2-3 returned values no $a0 - $a3 4-7 arguments yes $t0 - $t7 8-1 temporaries no $s0 - $s saved values yes $t8 - $t temporaries no $gp 28 global pointer yes $sp 29 stack pointer yes $fp 30 frame pointer yes $ra 31 return addr (hardware) yes MIPS Register File Holds thirty-two -bit registers Two read ports and One write port src1 addr src2 addr dst addr Registers are write Faster than main memory - But register files with more locations are slower (e.g., a 64 word file could Register File bits locations write control be as much as 0% slower than a word file) - Read/write port increase impacts speed quadratically Easier for a compiler to use - e.g., (A*B) (C*D) (E*F) can do multiplies in any order vs. stack Can hold variables so that - code density improves (since register are named with fewer bits than a memory location) src1 src2 MIPS Arithmetic Instructions

3 MIPS Arithmetic Logic Unit (ALU) Must support the Arithmetic/Logic operations of the ISA add, addi, addiu, addu sub, subu, neg A mult, multu, div, divu B sqrt and, andi, nor, or, ori, xor, xori beq, bne, slt, slti, sltiu, sltu zero ovf 1 ALU 4 1 m (operation) With special handling for sign extend addi, addiu andi, ori, xori, slti, sltiu zero extend lbu, addiu, sltiu no overflow detected addu, addiu, subu, multu, divu, sltiu, sltu result MIPS Arithmetic Instructions MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 Each arithmetic instruction performs only one operation Each arithmetic instruction fits in bits and specifies exactly three operands destination source1 op source2 Those operands are all contained in the path s register file ($t0,$s1,$s2) indicated by $ Operand order is fixed (destination first) MIPS Arithmetic Instructions MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 Each arithmetic instruction performs only one operation Each arithmetic instruction fits in bits and specifies exactly three operands destination source1 op source2 Operand order is fixed (destination first) Those operands are all contained in the path s register file ($t0,$s1,$s2) indicated by $ Example a = a+b+c; MIPS code: a: $s0 b: $s1 c: $s2 add $t0, $s1, $s2 add $s0, $s0, $t0

4 Machine Language - Add Instruction Instructions, like registers and words of, are bits long Arithmetic Instruction Format (R format): add $t0, $s1, $s2 op rs rt rd shamt funct op 6-bits opcode that specifies the operation rs -bits register file of the first source operand rt -bits register file of the second source operand rd -bits register file of the result s destination shamt -bits shift amount (for shift instructions) funct 6-bits function code augmenting the opcode Example Consider the following AL instruction: add $t0, $s1, $s2 What is the equivalent ML instruction? Some help: add is an R-format instruction What is the structure of an R-format instructions: Op-code rs rt rd shamt funct Example con t Consider the following AL instruction: add $t0, $s1, $s2 On MIPS processors: $t0 is mapped into the number and is a source/destination $s1 is mapped into the number and is a source/destination $s2 is mapped into the number and is a source/destination Logical Operations MIPS code: sll $t2, $s0, 4 # $t2 = $s0 << 4 bits Q: What format does the sll instruction have? R-format OP OP rs rt rd sa funct rs rt immediate R format I format OP jump target J format Op-code rs rt rd shamt funct Op-code rs rt rd shamt funct

5 AND / OR Let s assume that: AL: $t2 = $t1 = and $t0, $t1, $t2 $t0 = AND mask since it conceals some bits Let s assume that: AL: $t2 = $t1 = or $t0, $t1, $t2 $t0 = MIPS Immediate Instructions Small constants are used often in typical code Possible approaches? put typical constants in memory and load them create hard-wired registers (like $zero) for constants like 1 have special instructions that contain constants! addi $sp, $sp, 4 #$sp = $sp + 4 slti $t0, $s2, 1 #$t0 = 1 if $s2<1 Machine format (I format): op rs rt 16 bit immediate I format The constant is kept inside the instruction itself! Immediate format limits values to the range to -2 1 Addi addi is an immediate instruction Q: Why are immediate instructions so important? A: The sum of a constant to a variable is a common operation. Immediate instructions make this common case faster. Load-Store

6 And if we need more How do we represent complex structures (i.e., array, structure) in assembly? We have a reduced number of registers!!!! How many? Memory can contain millions of elements register Memory We need instructions that transfer from and to the memory transfer instructions Memory Representation We think so It is so. Memory large, single-dimension array Memory es indexes to this array To access in memory or put in memory we have two instructions: load and store bits MIPS Memory Access Instructions MIPS has two basic transfer instructions for accessing memory lw $t0, 4($s3) #load word from memory sw $t0, 8($s3) #store word to memory The is loaded into (lw) or stored from (sw) a register in the register file a bit The memory a bit is formed by adding the contents of the base register to the offset value A 16-bit field meaning access is limited to memory locations within a region of ±2 13 or 8,192 words (±2 1 or,768 bytes) of the in the base register Note that the offset can be positive or negative Machine Language - Load Instruction Load/Store Instruction Format (I format): $s2 = lw $t0, 24($s2) op rs rt 16 bit offset = 0x120040ac $t0 Memory 0xf f f f f f f f 0x120040ac $s2 0x x c 0x x x word (hex)

7 Loading and Storing Bytes MIPS provides special instructions to move bytes lb $t0, 1($s3) #load byte from memory sb $t0, 6($s3) #store byte to memory op rs rt 16 bit offset What 8 bits get loaded and stored? load byte places the byte from memory in the rightmost 8 bits of the destination register - what happens to the other bits in the register? store byte takes the byte from the rightmost 8 bits of a register and writes it to a byte in memory - what happens to the other bits in the memory word? Example: Load int A [100]; int g; int h; g = h + A []; To write the equivalent MIPS code: base of A is in $s3 g is assigned to $s1 h is assigned to $s2 Write the MIPS code: lw $t0, 20($s3) # the temp register $t0 gets A [ ] add $s1, $s2, $t0 # g = h + $t0 Why 20? 20 words or bytes? Example: Store Example: Store int A [100]; int g; int h; A [12] = h + A [8]; Assign variables to registers: base of A is in $s3 h is assigned to $s2 int A [100]; int g; 100 is a constant Int h; A [12] = A [8]; Assign variables to registers: base of A is in $s3 lw $t0, ($s3) # the temp register $t0 gets A [ 8 ] add $t0, $s2, $t0 # $t0= h + $t0 sw $t0, 48($s3) # store the temp register $t0 in A [12] lw $t0, ($s3) # the temp register $t0 gets A [ 8 ] addi $t0, $t0, 100 # $t0= $t0 sw $t0, 48($s3) # store the temp register $t0 in A [12]

8 MIPS Control Flow Instructions MIPS conditional branch instructions: bne $s0, $s1, Lbl #go to Lbl if $s0 $s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1 Control Flow Instructions Ex: if (i==j) h = i + j; bne $s0, $s1, Lbl1 add $s3, $s0, $s1 Lbl1:... Instruction Format (I format): op rs rt 16 bit offset How is the branch destination specified? Specifying Branch Destinations Use a register (like in lw and sw) added to the 16-bit offset which register? Instruction Address Register (the PC) - its use is automatically implied by instruction - PC gets updated (PC+4) during the fetch cycle so that it holds the of the next instruction limits the branch distance to -2 1 to instructions from the (instruction after the) branch instruction, but most branches are local anyway from the low order 16 bits of the branch instruction sign-extend PC offset Add branch dst Add? More Branch Instructions We have beq, bne, but what about other kinds of brances (e.g., branch-if-less-than)? For this, we need yet another instruction, slt Set on less than instruction: slt $t0, $s0, $s1 # if $s0 < $s1 then # $t0 = 1 else # $t0 = 0 Instruction format (R format): op rs rt rd funct 2

9 More Branch Instructions, Con t Can use slt, beq, bne, and the fixed value of 0 in register $zero to create other conditions less than blt $s1, $s2, Label slt $at, $s1, $s2 #$at set to 1 if bne $at, $zero, Label # $s1 < $s2 less than or equal to greater than great than or equal to ble $s1, $s2, Label bgt $s1, $s2, Label bge $s1, $s2, Label Other Control Flow Instructions MIPS also has an unconditional branch instruction or jump instruction: j label #go to label Instruction Format (J Format): op 26-bit from the low order 26 bits of the jump instruction 26 Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler Its why the assembler needs a reserved register ($at) 4 PC 00 Aside: Branching Far Away What if the branch destination is further away than can be captured in 16 bits? The assembler comes to the rescue it inserts an unconditional jump to the branch target and inverts the condition becomes L2: beq $s0, $s1, L1 bne $s0, $s1, L2 j L1 Converting C Code into AL (I) if ( i == j) else f = g + h; f = g h; AL code: Assign variables to registers: i $s3 j $s4 f $s0 g $s1 h $s2 Do simple translations f. add $s0, $s1, $s2 # f = g + h g. sub $s0, $s1, $s2 # f = g - h Organize the translations bne $s3, $s4, ELSE f. j EXIT ELSE: g. EXIT:. Complete the code bne $s3, $s4, ELSE add $s0, $s1, $s2 # f = g + h j EXIT ELSE: sub $s0, $s1, $s2 # f = g - h EXIT:.

10 Converting C Code into AL (II) while (save[i] = = k) i += 1; Convert the code in MIPS AL 1. Assign variables to registers: save $s 6 i $s 3 k $s 2. Do simple translations: a. compute in memory for index i sll $t1, $s3, 2 # add = i * 4 = i << 2 b. load save[i] lw $t0, $t1($s6) c. increase i addi $s 3, $s 3, 1 # load save[i] # i+=1; 3. Organize the translations: LOOP: a. compute in memory for index I b. b. load save[i] lw $t0, $t1($s6) # save[i[ <> k bne $t0, $s, EXIT c. increase I j LOOP EXIT: 4. Complete the code: LOOP: sll $t1, $s3, 2 # add = i * 4 = i << 2 add $t1, $t1, $s6 lw $t0, 0($t1) # save[i[ <> k bne $t0, $s, EXIT addi $s 3, $s 3, 1 # i+=1; j LOOP EXIT: Converting AL into ML while (save[i] == k) i += 1; Assembly code Loop: sll $t 1, $s 3, 2 # temp reg $t 1 = 4 * i where i $s 3 add $t 1, $t 1, $s 6 # $t 1 = of save[i] lw $t 0, 0($t 1 ) # temp reg $t 0 = save[i] bne $t 0, $s 6, Exit # go to Exit if save[i] <> k addi $s 3, $s 3, 1 # increment I j Loop Exit: Write the equivalent ML instructions for the MIPS code above. The code is located in the text segment of the memory starting from 0x MIPS Review : bne statement jumps to = * 4 Note that PC points always to the next instruction 80020: j instruction uses the full x 4 = 80000

11 MIPS Organization So Far MIPS ISA So Far Processor Register File src1 addr src2 addr registers dst addr ($zero - $ra) write bits src1 src2 branch offset PC Add Add 4 Fetch PC = PC+4 Exec Decode ALU read/write addr read write Memory byte (big Endian) bits words word (binary) Category Instr Op Code Example Meaning Arithmetic (R & I format) Data Transfer (I format) Cond. Branch (I & R format) Uncond. Jump (J & R format) add 0 and add $s1, $s2, $s3 $s1 = $s2 + $s3 subtract 0 and 34 sub $s1, $s2, $s3 $s1 = $s2 - $s3 add immediate 8 addi $s1, $s2, 6 $s1 = $s2 + 6 or immediate 13 ori $s1, $s2, 6 $s1 = $s2 v 6 load word 3 lw $s1, 24($s2) $s1 = Memory($s2+24) store word 43 sw $s1, 24($s2) Memory($s2+24) = $s1 load byte lb $s1, 2($s2) $s1 = Memory($s2+2) store byte 40 sb $s1, 2($s2) Memory($s2+2) = $s1 load upper imm 1 lui $s1, 6 $s1 = 6 * 2 16 br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to L br on not equal bne $s1, $s2, L if ($s1!=$s2) go to L set on less than 0 and 42 slt $s1, $s2, $s3 if ($s2<$s3) $s1=1 else $s1=0 set on less than immediate 10 slti $s1, $s2, 6 if ($s2<6) $s1=1 else $s1=0 jump 2 j 200 go to jump register 0 and 8 jr $t1 go to $t1 jump and link 3 jal 200 go to 10000; $ra=pc+4 MIPS (RISC) Design Principles Simplicity favors regularity fixed size instructions -bits small number of instruction formats opcode always the first 6 bits Good design demands good compromises three instruction formats Smaller is faster limited instruction set limited number of registers in register file limited number of ing modes Make the common case fast arithmetic operands from the register file (load-store machine) allow instructions to contain immediate operands Review of MIPS Operand Addressing Modes Register ing operand is in a register op rs rt rd funct Register word operand Base (displacement) ing operand is at the memory location whose is the sum of a register and a 16-bit constant contained within the instruction op rs rt offset Memory word or byte operand base register Register relative (indirect) with 0($a0) Pseudo-direct with addr($zero) Immediate ing operand is a 16-bit constant contained within the instruction op rs rt operand

12 Review of MIPS Instruction Addressing Modes PC-relative ing instruction is the sum of the PC and a 16-bit constant contained within the instruction Next Deadlines op rs rt offset Program Counter (PC) Memory branch destination instruction Pseudo-direct ing instruction is the 26- bit constant contained within the instruction concatenated with the upper 4 bits of the PC op jump Program Counter (PC) Memory jump destination instruction Next Weeks Important Don't forget to register for the CS Research Day at: