CIRPART A FPGA BASED PROCESSOR FOR CIRCUIT MULTI-WAY PARTITIONING USING HYBRID GENETIC ALGORITHM

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1 CIRPART A FPGA BASED PROCESSOR FOR CIRCUIT MULTI-WAY PARTITIONING USING HYBRID GENETIC ALGORITHM S. Rajaram, Dhinesh Joseph Sukumar, S.V. Karthick, V. Abhai Kumar Department of Electronics and Communication, Thiagarajar College of Engineering, Madurai sdhineshjoseph_conf@rediffmail.com ABSTRACT This paper proposes CIRPART architecture for implementing Hybrid Genetic Algorithm (GA) used for circuit Multiway Partitioning in VLSI physical design automation. CIRPART applies Hybrid Genetic Algorithm to considerably reduce the number of generations required. CIRPART provides flexibility and also achieves speedups over software based GA. CIRPART achieves more than 100x improvement in processing speed as compared to the software implementation. 1. INTRODUCTION GAs are applied to Circuit Partitioning problems since GA is more global (i.e.,) search is done from a population and not a single point and also large number of points are handled in parallel [1]. The circuit-partitioning problem [2] can be formally represented in graph theoretic notation as a weighted graph, G = (V, E) with the components represented as nodes, v i Є V where V is the vertex set and the wires connecting them as edges, e ij = (v i,v j ) Є E where E is the edge-set. Let a i be the weight (area) of a vertex i, and c ij be the weight or cost of an edge e ij. Also given is the number of partitions k, and the capacity of each subset or partition, A 1, A 2,,A k. The output consists of disjoint subsets V 1, V 2,,V k such that U k n=1 V n = V, Vn, Σ υ i ЄVn a i <A n, and e ij such that [υ i ] [υ j ], C = Σc ij is minimized. V n = [υ i ] represents the subset containing υ i, and C is the cost of the cut. The set of edges cut by the partition, e ij, [υ i ] = [υ j ] is called the cut set. Using Sterling s approximation [3], N k = O((n/p) (n-n/p) ). 2. PREVIOUS WORK Numerous optimization techniques have been applied to solve the graph and circuit partitioning problems [4,5,6,7,8,9]. GAs, which exhibit intrinsic parallelism provide even better solutions. Hybrid GAs [10] still speeds up the process. The use of reconfigurable hardware for the design of GA was seen in projects such as [11, 12, 13, 14, 15, 16, 17]. In the current work, all the research done in hardware implementation of GA is combined to create a system, which attempts to achieve significant speedup over software GA due to pipelining and parallelization. It also attempts to minimize the logic resources used within FPGA. It applies Hybrid Genetic Algorithm to perform local optimization in every generation. This results in faster convergence and hence the number of generations is considerably reduced. 3. NEED FOR HARDWARE REALIZATION OF GENETIC ALGORITHM Reconfigurability is essential in a generalpurpose GA engine because certain GA modules require changeability). Thus a hardware-based GA is both feasible and desirable. Work by Spears and De Jong [18] indicates that for NP-complete problems, m=100 and g=100 may be necessary to obtain a good result and avoid premature convergence to a local optimum. Because a general-purpose GA engine requires certain parts of its design to

2 be easily changed, a hardware-based Genetic Algorithm (HGA) was not feasible until Field Programmable Gate Arrays (FPGAs) [19] were developed. Reprogrammable FPGAs (those programmed via a bit patterns stored in a static RAM) are essential to the development of the HGA system. 4. SYSTEM ARCHITECTURE CIRPART is specifically optimized towards solving the circuit Multiway Partitioning. CIRPART uses a processing-pipeline for performing the computationally intensive parts of the partitioning algorithm. The block diagram of the GA processor is shown in Figure 1. The design is coded in VHDL and uses the generics shown in Table 1. The external RAM modules used by the design are listed in Table 2. The chromosome representation is depicted in Figure 2. The various registers used are listed in the table 3. The GA Processor consists of the following modules Fitness Evaluation Module (FEM) Once GOM generates a complete new population FEM generates fitness values for each of the generated chromosomes. Upon receiving the active high Start_Eval signal from CPM, FEM determines for each chromosome, the Partition-imbalance Cost and the Net-cut Cost simultaneously Parent Selection Module (PSM) PSM performs Tournament selection on the population by reading four random fitnesses from the Fitness memory upon receiving an active high START_SEL signal from the Main Controller. At the end of selection of two parents, PSM generates a signal, indicating end of selection Genetic Operation Module (GOM) GOM performs the crossover and mutation operations on the two parent chromosomes, the starting addresses of which are generated by PSM. The Population memory is divided into two address spaces, namely the low bank, and the high bank. At any time, the parent population is stored into one of the banks and the child population generated by GOM is stored into the other bank. Upon receiving an active high START_MAT signal from CPM, the chromosome for each of the parents is read from the Population memory based upon the addresses generated by PSM. The Crossover template is shown in Figure 3. Figure 4 describes the input status of both the multiplexer banks corresponding to different offsprings. Mutation is performed with a very small probability P m Central Processing Module (CPM) CPM generates control signals for rest of the blocks of the design. The state diagram of CPM is shown in figure 5. The various states of CPM are quoted below, S1 (000): CPM starts reading the various inputs using the input handshake signals. S2 (001): After loading the netlist into the Netlist memory, CPM generates random chromosomes and initializes the Population memory with random population. S3 (010): CPM evaluates the fitness of each individual in the population by enabling FEM. S4 (011): CPM selects the parents based on the fitness value by enabling PSM. S5 (100): CPM generates new population by enabling GOM. 5. EXPERIMENTAL RESULTS The GA was implemented in the C++ programming language on a Pentium III (800 MHz) machine with 128 MB memory. The proposed architecture CIRPART for Multiway Partitioning was implemented in Virtex V100CS144 chip through VHDL. The architecture was tested for structural and physical functionalities and proved to be satisfactory. The performance results for Hardware GA and Software GA are compared and tabulated in Tables 4 and 5 (default values for no. of generation, G N and population size, C N being 20).

3 6. CONCLUSION In this paper, CIRPART - a new architecture for implementing the Hybrid GA in hardware is proposed. Although the architecture is designed specifically to solve the Circuit Multi-way Partitioning problem, some of the modules in the design can be re-used for other problems as well. There are many ways to extend the proposed design by simple modifications to the VHDL code. This design was used to solve multi-way circuit partitioning problem with Tournament Selection and Uniform crossover. Other GA operators could be implemented as well. Alternate chromosome representations can be explored in order to reduce the memory requirements. 7. REFERENCES [1] D.E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning, Addison-Welsey Publishing Company, Reading,Massachusetts, [2] S. Areibi, "A Review of Circuit Partitioning", Technical report, School of Engineering, University of Guelph, June [3] G. A. Korn and T. M. Korn, Mathematical Handbook for Scientists and Engineers, New York: McGraw-Hill Book Company, Inc., [4] U. R. Kodres, Partitioning and Card Selection, in Design Automation of Digital Systems, M. A. Breuer, ed., pp , [5] B. W. Kernighan and S. Lin, An Efficient Heuristic Procedure for Partitioning Graphs, Bell Systems Technical Journal, vol. 49, pp , [6] C. M. Fiduccia and R. M. Mattheyses, A Linear-time heuristic for improving network partitions, Proc. Design Automation Conf., pp , [7] B. Krishnamurthy, An Improved min-cut algorithm for partitioning VLSI networks, IEEE Trans. Computers, vol. c-33, pp , [8] S. Dutta and W. Deng, A Probabilitybased approach to VLSI circuit partitioning, Proc. Design Automation Conf., pp , [9] S. Kirkpatrick, C. D. Gelatt, Jr., and M. P. Vecchi, Optimization by Simulated Annealing, Science, vol. 220, no.4598, pp , May [10] T.N. Bui, and B.R. Moon, A Fast and stable hybrid genetic algorithm for the ratio-cut partitioning problem on hypergraphs, Proc. ACM/IEEE Design Automation Conf., pp , June [11] Stephen Donald Scott, "A hardware based genetic algorithm", Master's thesis, University of Nebraska, August [12] Tommi Rintala, "Hardware implementation of GA", September [13] Loring Wirbel, "Compression chip is first to use genetic algorithms", page 17, December [14] PaulGraham and Brent Nelson, "A Hardware Genetic Algorithm for the Travelling Salesman Problem on Splash2", [15] PaulGraham and Brent Nelson, "Genetic Algorithms in Software and in Hardware- A performance Analysis of workstation and custom Computing Machine Implementation", in IEEE Symposium on FPGAs for custom Computing Machines, pp , Reconfigurable Logic Laboratory, Brigham Young University, Provo, UT, USA, [16] John R. Koza, Forrest h Bennett III, Stephen L Jeffrey L, Martin A and David Andre, "Evolving Computer Programs using Rapidly Reconfigurable Field Programmable Gate Arrays and Genetic Programming", [17] Chatchawit and Prabhas, "A Hardware Implementation of compace Genetic algorithm", in Proceedings of the 2001 IEEE Congress on Evolutionary Computation, pp , Seoul, Korea, May [18] K.A. De Jong and W.M. Spears, "Using genetic algorithms to solve NP-complete problems", in J.David Schaffer, editor, Proceedings of the Third International Conference on Genetic Algorithms, pp Morgan Kaufmann Publishers, [19] S.D. Brown, R.J. Francis, J. Rose and Z.G. Vranesic, Field-Programmable Gate Arrays, Kluwer Academic Publishers, USA, 1992.

4 BUS NAME AB1 DB1 AB2 DB2 AB3 DB3 AB4 DB4 DESCRIPTION Address Bus of Central Processing Module Data Bus of Central Processing Module Address Bus of Fitness Evaluation Module Data Bus of Fitness Evaluation Module Address Bus of Parent Selection Module Data Bus of Parent Selection Module Address Bus of Genetic Operation Module Data Bus of Genetic Operation Module Figure 1: Architecture for the Genetic Algorithm Processor Figure 2: Chromosome Representation of Circuit-multiway-Partitioning

5 RNG Random Number Generator *OA(i) i th bit content of First Offspring PA(i) i th bit content of First Parent OB(i) i th bit content of Second Offspring PB(i) i th bit content of Second Parent O(i) i th bit content of Offspring (in general) Figure 3: Crossover Template Figure 4: Multiplexer Inputs INPUT SIGNAL SIGNIFICANCE 000 StartGA Starts the GA Process. 001 StartInit Initializes the Population memory with random population. 010 StartEval Enables the Fitness Evaluation Module. 011 StartSel Enables the Parent Selection Module. 100 StartMat Enables the Genetic Operation Module. OUTPUT SIGNAL SIGNIFICANCE 000 Ready Indicates the successful reception of all inputs. 001 InitComp Indicates the completion of random initial population generation in the Population memory. 010 EvalComp Indicates the completion of the Fitness Evaluation Process. 011 SelComp Indicates the completion of the Parent Selection Process. 100 MatComp Indicates the completion of the Mating Process. 101 GAComp Indicates the completion of the GA Process. This happens at the end of the last generation. Figure 5: State machine of Central Processing module. S.No GENRIC NAME DESCRIPTION 1 FMAddrWidth Fitness memory address width. This gives two times maximum size supported. 2 FMDataWidth Fitness memory data width. 3 IMAddrWidth Input memory address width. This gives two times maximum size supported. 4 IMDataWidth Input memory data width. This represents word size of Input memory. 5 Chromosome_Length Number of bits used to represent the chromosome. Table 1: Generics used in the design

6 S.No MEMORY DESCRIPTION 1 Input Memory It stores the netlist in a modified form. For each net, the words corresponding to the modules that are connected via that particular newt, are made All 1 s and the rest of the words are made All 0 s. It stores the areas of the modules. It stores Population size, Number of Generations required, Number of Partitions required, Number of modules, Number of nets, Crossover rate and Mutation Rate. This is single address port synchronous RAM. 2 Population Memory It stores population elements for the parent as well as child population. The address space is divided into two halves. Each half stores either parent or child population. This is dual address port synchronous RAM. 3 Fitness Memory It stores fitness of parent and child population. This is also divided into two parts for storing parent and child population. This is single address port synchronous RAM. Table 2: Core Memories REGISTER SIZE (bits) DESCRIPTION Crossover_Rate 32 Crossover rate Mutation_Rate 32 Mutation rate Word_Count 16 Number of the word in a particular chromosome that is currently in process. Net_Count 16 Number of the net currently in process Chromosome_Count 8 Number of the chromosome currently in process Ref_Worst_Cost 32 Reference Worst Cost Table 3: Control Registers CIRCUIT #MODULES #NETS SOFTWARE HARDWARE G N=20 G N=60 G N=100 G N=20 G N=60 G N=100 Fract Struct Primary Ckt Ckt Ckt Ckt Ckt Ckt Ckt Ckt Table 4: Performance results for Hardware GA and Software GA for different Generation Count. CIRCUIT #MODULES #NETS SOFTWARE HARDWARE C N=20 C N=60 C N=100 C N=20 C N=60 C N=100 Fract Struct Primary Ckt Ckt Ckt Ckt Ckt Ckt Ckt Ckt Table 5: Performance results for Hardware GA and Software GA for different Chromosome Count.