ICE Emulator for 68HC05 and 68HC08

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1 ICE Emulator for 68HC05 and 68HC08 TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... ICE In-Circuit Emulator... ICE Target Guides... ICE Emulator for 68HC05 and 68HC Warning... 4 Quick Start... 4 Troubleshooting... 5 Hang-Up 5 Dual-Port Errors 5 FAQ... 6 Basics... 9 Emulation Modes 9 SYStem.Clock Clock generation 11 SYStem.Access Dualport access 11 Code Sequencer 12 General SYStem Settings and Restrictions General Restrictions 13 SYStem.Option V33 Power option 13 SYStem.Option TraceAll Trace option 14 SYStem.Option PerReset Reset target 14 SYStem.Option FAST Speed 14 SYStem.Option TestClock Clock sense 14 SYStem.Option MapEEPROM Mapping 15 SYStem.Option MapGAP Mapping 15 SYStem.Option CANE CAN enable 15 SYStem.Option COMMON Size of common area. 15 SYStem.Option MAPEEPROM Enable EEPROM memory areas 16 SYStem.Option MAPGAP Enable GAP memory areas 16 SYStem.Option MOR Mask option register setting 16 SYStem.Option WDT Watchdog enable 16 Exception Control RESET 17 ICE Emulator for 68HC05 and 68HC08 1

2 Interrupt Control 18 Memory Classes State Analyzer Keywords for the Trigger Unit 20 General 68HC08 Keywords for the Trigger Unit 20 Keywords for the Display 21 Port Analyzer Keywords for the Port Analyzer 22 Additional Trace Channels 23 Compilers rd Party Tool Integrations 24 Emulation Frequency Emulation Modules Overview 27 Order Information 28 Physical Dimensions Adapter ICE Emulator for 68HC05 and 68HC08 2

3 ICE Emulator for 68HC05 and 68HC08 Version 06-Nov-2017 P:0069B0 \\IAR08\iar08\sieve+5... HLL AI E::w.d.l addr/line source register int i, primz, k; int anzahl; 515 anzahl = 0; 517 for ( i = 0 ; i <= SIZE ; flags[ i++ ] = TRUE ) ; ; i <= SIZE ; i++ ) E::w.v.f /l /c flags[ i ] ) E::w.r end of frame V V A 0 SP > main() primz = i + i + 3 HC _ X j = 15 I I D H:X 0203 { ::w.per N _ SP 0FF sieve(); IM4 Z _ PC sieve() SC 20 TOF no TOE C _ CCR 0E i = 3 DMA 00 TSK _ BNK primz = 3 CNT k = 3 MOD FFFF anzahl = 3 SC0 00 CHF no CHIE dis MSB norm MSA in E For general informations about the In-Circuit Debugger refer to the ICE User s Guide (ice_user.pdf). All general commands are described in IDE Reference Guide (ide_ref.pdf) and General Commands and Functions. ICE Emulator for 68HC05 and 68HC08 3

4 Warning NOTE: Do not connect or remove probe from target while target power is ON. Power up: Switch on emulator first, then target Power down: Switch off target first, then emulator Quick Start tbd. ICE Emulator for 68HC05 and 68HC08 4

5 Troubleshooting Hang-Up If you are not able to stop the emulation, there may be some typically reasons: Clock Error Wait / Stop instruction The clock lines between the target and the CPU on the probe are very short. Therefore normally no problems should occur when using an external crystal. Be sure that the capacitors on the target have a value of 20 pf minimum and are with short routes connected to the CPU socket. If you try to break the emulation while the processor is in stop or wait state, this could cause problems. Dual-Port Errors Dual-port errors may occur by the following conditions: 1. The bus frequency in GAP access mode is higher than 8 MHz. 2. The clock signal is switched off. 3. The CPU is hold in STOP state for a too long time. 4. The bus frequency in DENIED access mode is lower than 1.5 MHZ If you have problems with the dp access at higher frequencies, you must switch to DENIED mode. In this mode no access to memory is possible while running realtime emulation. The dual-port access has no effect on CPU performance in both modes. The 68HC05 CPUs do not use the DENIED mode, but only the GAP mode. ICE Emulator for 68HC05 and 68HC08 5

6 FAQ Debugging via VPN Ref: 0307 The debugger is accessed via Internet/VPN and the performance is very slow. What can be done to improve debug performance? The main cause for bad debug performance via Internet or VPN are low data throughput and high latency. The ways to improve performance by the debugger are limited: In PRACTICE scripts, use "SCREEN.OFF" at the beginning of the script and "SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates. Please note that if your program stops (e.g. on error) without executing "SCREEN.OFF", some windows will not be updated. "SYStem.POLLING SLOW" will set a lower frequency for target state checks (e.g. power, reset, jtag state). It will take longer for the debugger to recognize that the core stopped on a breakpoint. "SETUP.URATE 1.s" will set the default update frequency of Data.List/Data.dump/Variable windows to 1 second (the slowest possible setting). prevent unneeded memory accesses using "MAP.UPDATEONCE [address-range]" for RAM and "MAP.CONST [address--range]" for ROM/FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified address range only once after the core stopped at a breakpoint or manual break. "MAP.CONST" will read the specified address range only once per SYStem.Mode command (e.g. SYStem.Up). ICE Emulator for 68HC05 and 68HC08 6

7 Target Power Supply Switch Ref: 0103 Is there a simple way to control target power supply via the ICE to prevent problems after the ICE has been powered off? Follow the sequence below. If you own an output probe COUT8, connect it to the STROBE output connector. Type PULSE2. and press F1. You will get the pin out of the output probe COUT8. Pin 13 (OUT6) delivers +5 V after the emulator has finished its initialization and 0 V if the emulator is powered off. This can be used to drive a relay via a transistor to switch the target power on and off automatically if the Pulse Generator is not used for other purposes. The schematic of the switching unit can be found in the file TARGETC.CMM. Additionally Pin 13 (OUT6) can be controlled by ICE commands. Target power supply off. "PULSE2.P +" Target power supply on. "PULSE2.P -" The following Practice command file creates 3 buttons in the Toolbox for: Target power on Target power off Target power off and QUIT. Wrong Location after Break Ref: 0030 HC05JJ/JP Mask Option Register Ref: 0080 Adding that file to T32.cmm loads the buttons automatically after startup. Why is the location after break wrong? Most emulators use some bytes of user stack for the break system. Therefore it is necessary to have valid stack, if single step or breakpoints are used. The System Option MOR does not work There is no possibility to set the correct value of the MOR in the non user mode by hardware. The CPU always uses the value of the internal EPROM of the chip. To change this value use a *.cmm file with the following content: Data.Set D:1FF1 'value' Data.Set D:1C 02 WAIT 1.s Data.Set D:1C 00 The MOR value of a new chip is 0. The bits can be toggled only from 0 to 1. If a wrong value was programmed, it is necessary to exchange the chip! ICE Emulator for 68HC05 and 68HC08 7

8 HC08 Problems with EEPROM Ref: 0084 HC08AZ/AT TimerB and CAN Module Ref: 0077 After I switched off the power of the emulator and booted again, the values of the internal EEPROM can not be read correctly Be sure that the SYSTEM.OPTION MAPEEPROM is switched off. The Timer B is not available. The CAN controller is not available. The silicon of HC08AZ, HC08AS and HC08AT is the same. The Timer B and the CAN controller is only in the AZ and AT mode available. To switch the timer B and the CAN module on, use the CONFIG2 register of the CPU. ICE Emulator for 68HC05 and 68HC08 8

9 Basics The ICE-08 emulation head supports all 68HC08 and 68HC05 derivatives from Freescale Semiconductor. The adaption to different probes is done by changing the module. Modules support both DIL and QFP versions, where applicable. The maximum frequency of the base modul is 12 MHz Busclock, however the emulation is only possible to the max. speed of the MCU's available from the chip manufacturer. All emulation probes support single chip modes. The emulator supports up to 256 KByte RAM/ROM address space. An additional slot in the base modul offers upgrading with the port analyzer to get timing and state trace features for all MCU I/O ports. Emulation Modes E::w.sys system Mode Clock TimeReq Option Down RESet VCO 1.000ms V33 Up Analyzer Low TimeOut TraceAll Monitor Mid us PerReset RESet ResetDown High Fast ResetUp TestClocK cpu-type NoProbe Access M68HC08 AloneInt GAP AloneExt DENIED EmulInt EmulExt The emulation head can stay in 6 modes. The modes are selected by the SYStem.Up or the SYStem.Mode command. SYStem.Mode <mode> <mode>: ResetDown ResetUp AloneInt AloneExt EmulInt EmulExt ICE Emulator for 68HC05 and 68HC08 9

10 Reset Down Reset Up Alone Internal Alone External Emulation Internal Emulation External Target is down, all drivers are in tristate mode. Target has power, drivers are logically in inactive state, but not tristate. Probe is running with internal clock, driver inactive. This mode is used for 'standalone' operation. Probe is running with external clock, driver inactive. Probe is running with internal clock, strobes to target are generated. Probe is running with external clock, strobes to target are activated. As neither 68HC08 nor 68HC05 have an external bus, there is no difference between driver active and inactive. Different modes are only used to be compatible with other emulation probes. In active mode, the power of the target is sensed and by switching down the target the emulator changes to RESET mode. The probe is not supplied by the target. When running without target, the target voltage is simulated by an internal pull-up resistor. If your target has an 3.3 V supply, you must use the 5 V sys option. ICE Emulator for 68HC05 and 68HC08 10

11 SYStem.Clock Clock generation SYStem.Clock <option> <option>: VCO High Mid Low VCO Low, Mid, High Variable frequency 1 35 MHz. 2.5, 5.0 or 10.0 MHz. SYStem.Access Dualport access SYStem.Access <mode> <mode>: GAP Denied GAP Denied The dual-port access is done between two CPU cycles. As two memory cycles appear in one CPU cycle, this way of dual-port access is limited to bus frequencies up to 8 MHz. No dual-port access is allowed while the realtime emulation is running. This mode must be used if the CPU is hold in stop state for long time or if the bus frequency is too high. ICE Emulator for 68HC05 and 68HC08 11

12 Code Sequencer TRACE32-ICE08 uses a special code sequencer to classify CPU bus cycles on realtime emulation. This feature allows perfect trigger and trace functions as idle cycles are not traced. The sequencer offers many functions not available on competitive emulation systems. pshx pshx f P:00800A opfetch 9E f P:00800A opfetch 9E f D:0000FE wr-stk F f D:0000FF wr-stk F f P:00800b opfetch E f P:00800B opfetch E f P:00800c opfetch f P:00800C opfetch 02 lda 2,sp lda 2,sp f P:00800D opfetch f P:00800D opfetch 52 div div f D:0000FF rd-data F f D: rd-data f P:00800E opfetch B f P:00800E opfetch B f D:00800E dummy B f P:00800F opfetch f D:00800F dummy 50 sta f D:00800F dummy f D: wr-data f D:00800F dummy f P: opfetch f D:00800F dummy f P: opfetch EE f D:00800F dummy 50 bne f P:00800F opfetch f P: opfetch C7 sta f P: opfetch FF Without Sequencer With Sequencer Program breakpoints may be set in data area for protection Data breakpoints may be set in code area for protection Select trace on data transfers only Easy trigger on exception cycles Selective trace ICE Emulator for 68HC05 and 68HC08 12

13 General SYStem Settings and Restrictions General Restrictions Stack Usage On-Board Programming Pending Interrupts STOP Instruction The stack pointer must be placed on a location, where the CPU has internal RAM. Otherwise problems may occur when switching between monitor program and user program On-board programming with external programmers is not allowed with the emulation probe (may be damaged). If interrupts from internal sources are pending, single stepping will go into the interrupt routine. When starting program execution at an address, where a breakpoint is already set, the emulator will immediately execute the interrupt program. After returning from interrupt it will stop at the breakpoint without moving to the next instruction. If the STOP Instruction is used, you must use the option sys.option.testclk=off.the STOP Instruction disables the clockout of the CPU. This would cause a emulator CLKFail error. You can't break the emulator while the CPU is in the STOP mode. Stop mode has to be left before break. SYStem.Option V33 Power option V33 [ON OFF] Switches the power supply off the emulation probe between 5 V and 3.3 V. This Option is only available when the CPU supports 3.3 V supply. ICE Emulator for 68HC05 and 68HC08 13

14 SYStem.Option TraceAll Trace option SYStem.Option TraceAll [ON OFF] Normally dummy cycles and prefetches are not traced by the analyzer. All CPU cycles are traced if this option is set. SYStem.Option PerReset Reset target SYStem.Option PerReset [ON OFF] When activated, the reset output line is active while the system is down. This ensures that the target peripherals in reset state after the emulation is activated. SYStem.Option FAST Speed SYStem.Option FAST [ON OFF] Normally, without using the PLL, the bus frequency is 1/4 of the clk frequency. With the option FAST, you can double the bus frequency. This option will be sampled only during reset and is available only for the HC08. SYStem.Option TestClock Clock sense SYStem.Option TestClock [ON OFF] The emulator measures the system clock and switches down the emulator if a clock fail is detected. Some derivatives stop also the oscillator when the STOP command is executed. To prevent from switching down the emulation when the oscillator is stopped, set this option to OFF. ICE Emulator for 68HC05 and 68HC08 14

15 SYStem.Option MapEEPROM Mapping SYStem.Option MapEEPROM [ON OFF] The target CPU accesses the internal resources (EEPROM) when the map eeprom option is ON. When this option is OFF, it accesses a mapped ram instead. SYStem.Option MapGAP Mapping SYStem.Option MapGAP [ON OFF] The target CPU accesses the internal resources (GAP = no internal resources) when the mapgap option is ON. When this option is OFF, it accesses a mapped ram instead. SYStem.Option CANE CAN enable SYStem.Option CANE [ON OFF] ON OFF Enable CAN interface. Disable CAN interface. Enable CAN interface, 68HC05 only. SYStem.Option COMMON Size of common area. SYStem.Option COMMON [4K 15K 32K 48K] Define size of common area for banked applications, 68HC05 only. ICE Emulator for 68HC05 and 68HC08 15

16 SYStem.Option MAPEEPROM Enable EEPROM memory areas SYStem.Option MAPEEPROM [ON OFF] ON OFF Enable EEPROM memory areas. Replace EEPROM memory areas by emulation memory. Enable EEPROM memory areas. SYStem.Option MAPGAP Enable GAP memory areas SYStem.Option MAPGAP [ON OFF] ON OFF Enable GAP memory areas. Replace GAP memory areas by emulation memory. Enable GAP memory areas. SYStem.Option MOR Mask option register setting SYStem.Option MOR [ON OFF] 68HC05 only. SYStem.Option WDT Watchdog enable SYStem.Option WDT [ON OFF] 68HC05 only. ICE Emulator for 68HC05 and 68HC08 16

17 Exception Control E::w.x exception Activate Enable Trigger Puls Puls OFF OFF OFF OFF OFF Single ON CpuReset ON ON CpuReset Width RESet PerReset CpuReset RESet PerReset 1.000us IRQ1 PerReset STOP IRQ1 PERiod IRQ2 IRQ1 IRQ1 IRQ IRQ2 IRQ2 PULS This menu chart is from the 68HC08XL36. It may be different for other CPUs. RESET The reset line (input and output) is controlled by a bridge with analog switches and diodes. RESET input VCC 2*VCC R1 R2 RESET- S2 RESET- Target Emulation CPU S3 S1 S4 GND GND R1 = 22K R2 = 1K R3 = 220 S1 Reset Target X.Activate PerReset X.Puls PerReset * running S2 Reset Out running S3 Reset In X.Enable Reset * running S4 Internal Reset Emulator Control X.Activate CpuReset * running X.Puls CpuReset * running ICE Emulator for 68HC05 and 68HC08 17

18 exception.enable CpuReset [ON OFF] exception.enable PerReset [ON OFF] exception.activate PerReset [ON OFF] exception.activate CpuReset [ON OFF] Interrupt Control Interrupts may be enabled separately for every interrupt input. The names of the different interrupts are like they are called in the CPU. Exception.Enable IRQ1 [ON OFF] Exception.Enable IRQ2 [ON OFF] ICE Emulator for 68HC05 and 68HC08 18

19 Memory Classes Memory Class Description C: Specify the same address-area (CPU-access) D: P: E: Emulation memory access (dual-ported) ED: EP: C:, P: and D: This storage classes operate on the same physically memory. They are only used to be compatible with other emulation probes. CPU internal registers and memory may not be accessed dual-ported, data written to the internal memory is also present in the emulation memory. ICE Emulator for 68HC05 and 68HC08 19

20 State Analyzer Keywords for the Trigger Unit General 68HC08 Keywords for the Trigger Unit Input Event Meaning Analyzer Hardware ECC8 HAC HA120 SA120 DATA Data access X X X X DMA DMA cycle X X X X DMAREAD DMA read cycle X X X X DMAWRITE DMA write cycle X X X X DUMMY DUMMY cycle X X X X FETCH any fetch cycle X X X X FFETCH First fetch cycle X X X X IRQ Interrupt request X X IRQ1 Interrupt 1 request X X IRQ2 Interrupt 2 request X X MEM Memory cycle X X X X MEMREAD Memory read cycle X X X X MEMWRITE Memory write cycle X X X X OFETCH Opfetch cycle X X X X PD0..PD6 Port D line access X X PORT Input line from port analyzer X X Read Read access X X X X SFETCH Sequential fetch cycle X X X X STACK Stack access X X X X STACKREAD Stack read cycle X X X X STACKWRITE Stack write cycle X X X X WAIT Wait state X X Write Write access X X X X XREAD X X X X For not CPU-specific keywords, see non-declarable input variables in ICE/FIRE Analyzer Trigger Unit Programming Guide (analyzer_prog.pdf). ICE Emulator for 68HC05 and 68HC08 20

21 Keywords for the Display WAIT PA0..PA7 PD0..PD5 Wait for interrupt, normally not sampled Port A Port D PIRQ1 Port Interrupt 1 PIRQ2 Port Interrupt 2 PIRQ PNWOI Port Interrupt Port Wired Or Interrupt ICE Emulator for 68HC05 and 68HC08 21

22 Port Analyzer Keywords for the Port Analyzer Port.A0..Port.A7 Port.B0..Port.B7 Port.C0..Port.C7 Port.D0..Port.D7 Port.E0..Port.E7 Port.F0..Port.F5 Port.G0..Port.G3 Port.H0..Port.H3 Port.IRQ1 Port.IRQ2 Port.IRQ Port.NWOI ICE Emulator for 68HC05 and 68HC08 22

23 Additional Trace Channels Not used trace channels on Port-Analyzer are connected to pins placed on the emulation module. Modul M68HC08-XL Port.I0 2 Port.I1 3 Port.I2 4 Port.I3 5 Port.I4 6 Port.I5 7 Port.I6 8 Port.I7 9 GND 10 GND Modul M68HC05-X32 M68HC05-B Port.I0 2 Port.I1 3 Port.I2 4 Port.I3 5 Port.I4 6 Port.I5 7 Port.I6 8 Port.I7 9 GND 10 GND ICE Emulator for 68HC05 and 68HC08 23

24 Compilers Language Compiler Company Option Comment C CX68HC05 Cosmic Software COSMIC C HT-6805 Microchip Technology HITECH Inc. C HICROSS NXP Semiconductors HICROSS Language Compiler Company Option Comment C CX68HC08 Cosmic Software COSMIC C HICROSS-68HC08 NXP Semiconductors HICROSS 3rd Party Tool Integrations CPU Tool Company Host WINDOWS CE PLATF. - Windows BUILDER CODE::BLOCKS - - C++TEST - Windows ADENEO - X-TOOLS / X32 blue river software GmbH Windows CODEWRIGHT Borland Software Windows Corporation CODE CONFIDENCE Code Confidence Ltd Windows TOOLS CODE CONFIDENCE Code Confidence Ltd Linux TOOLS EASYCODE EASYCODE GmbH Windows ECLIPSE Eclipse Foundation, Inc Windows CHRONVIEW Inchron GmbH Windows LDRA TOOL SUITE LDRA Technology, Inc. Windows UML DEBUGGER LieberLieber Software Windows GmbH SIMULINK The MathWorks Inc. Windows ATTOL TOOLS MicroMax Inc. Windows VISUAL BASIC INTERFACE Microsoft Corporation Windows ICE Emulator for 68HC05 and 68HC08 24

25 CPU Tool Company Host LABVIEW NATIONAL Windows INSTRUMENTS Corporation RAPITIME Rapita Systems Ltd. Windows RHAPSODY IN MICROC IBM Corp. Windows RHAPSODY IN C++ IBM Corp. Windows DA-C RistanCASE Windows TRACEANALYZER Symtavision GmbH Windows TA INSPECTOR Timing Architects GmbH Windows UNDODB Undo Software Linux VECTORCAST UNIT Vector Software Windows TESTING VECTORCAST CODE COVERAGE Vector Software Windows ICE Emulator for 68HC05 and 68HC08 25

26 Emulation Frequency Module CPU F-W0-15 F-W0-35 S-W0-15 S-W0-35 S-W1-15 S-W1-35 LA-7126 MC68HC05B LA-7121 MC68HC05B LA-7123 MC68HC05C LA-7122 MC68HC05D LA-7120 MC68HC05X LA-7111 MC68HC08AB LA-7112 MC68HC08AS LA-7112 MC68HC08AT LA-7112 MC68HC08AZ LA-7111 MC68HC08AZ LA-7113 MC68HC08GP LA-7110 MC68HC08XL LA-7120 MC68HC705-X DRAM ICE Emulator for 68HC05 and 68HC08 26

27 Emulation Modules Overview LA-7100 LA-7110 MC68HC08XL36 MC68HC08XL36 DIL56 ET64-QF29 MC68HC08AB ET100-QF49 LA-7111 MC68HC08AB ET64-QF29 MC68HC08AZ0 ET100-QF49 MC68HC08AS ET64-QF29 MC68HC08AS PLCC52 LA-7112 MC68HC08AT ET64-QF29 MC68HC08AT PLCC52 MC68HC08AZ ET64-QF29 LA-7113 MC68HC08GP MC68HC08GP DIL40 ET44-QF16 LA-7120 MC68HC05X MC68HC705-X32 ET64-QF29 ET64-QF29 LA-7121 MC68HC05B32 ET64-QF29 LA-7122 MC68HC05D ET64-QF29 LA-7123 LA-7124 LA-7125 MC68HC05C MC68HC05C MC68HC05C MC68HC05C ET44-QF16 SDIP42 DIP40 PLCC44 LA-7126 MC68HC05B16 PLCC52 LA-7127 MC68HC05B32 PLCC52 ICE Emulator for 68HC05 and 68HC08 27

28 Order Information Order No. Code Text LA-7100 ICE-08 ICE-08 Base Module LA-7110 M-MC68HC08-XL36 Module MC68HC08-XL36 LA-7111 M-MC68HC08-AZ0/AB0 Module MC68HC08-AZ0/AB0 LA-7115 M-MC68HC08-AZ60A Module MC68HC08-AZ60A LA-7112 M-MC68HC08-AT Module MC68HC08-AT/AS/AZ16-AZ60 LA-7113 M-MC68HC08-GP Module MC68HC08-GP LA-7116 M-MC68HC08-GT Module MC68HC08-GT LA-7117 M-MC68HC08-AB32 Module MC68HC08-AB32 LA-7120 M-MC68HC05-X32 Module MC68HC05-X32 LA-7121 M-MC68HC05-B32-ET64 Module MC68HC05-B32/ET64 LA-7122 M-MC68HC05-D32 Module MC68HC05-D32 LA-7123 M-MC68HC05-C9 Module MC68HC05-C9 LA-7124 A-MC68HC05-C9-E/S Adapter MC68HC05-C9 ET/SDIP LA-7125 A-MC68HC05-C9-P/D Adapter MC68HC05-C9 PLCC/DIP LA-7128 M-MC68HC05-JJ/JP Module MC68HC05-JJ/JP LA-7126 M-MC68HC05-B16 Module MC68HC05-B16 LA-7127 M-MC68HC05-B32-PLCC Module MC68HC05-B32/PLCC52 Additional Options TO-1340 ET44-ETO-QF16 Emul. Adapter for T0 socket ET44-QF16 TO-1341 ET44-STO-QF16 Emul. Adapter TO-surface mount. ET44-QF16 LA-6450 PA64 Port Analyzer LA-1925 PLCC-TEST-ADAPTER-44 PLCC Test Adapter 44 Pins YA-1160 YA-SOCKET-QF29 YAMAICHI Socket ET64-QF29 ICE Emulator for 68HC05 and 68HC08 28

29 Physical Dimensions Dimension LA-7110 M-MC68HC08-XL36 64 cable (400) SIDE VIEW PIN 1 PIN TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 29

30 Dimension LA-7111 LA-7112 M-MC68HC08-AZ0/AB0 M-MC68HC08-AT 64 cable (400) SIDE VIEW Pin TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 30

31 Dimension LA-7120 M-MC68HC05-X32 64 cable (400) SIDE VIEW PIN TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 31

32 Dimension LA-7121 LA-7126 LA-7127 M-MC68HC05-B32-ET64 M-MC68HC05-B16 M-MC68HC05-B32-PLCC 64 cable (400) SIDE VIEW 8 PIN 1 PIN TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 32

33 Dimension LA-7122 M-MC68HC05-D32 64 cable (400) SIDE VIEW PIN TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 33

34 Dimension LA-7123 M-MC68HC05-C9 64 cable (400) SIDE VIEW PIN TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 34

35 Dimension LA-7124 A-MC68HC05-C9-E/S SIDE VIEW PIN TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 35

36 Dimension LA-7125 A-MC68HC05-C9-P/D SIDE VIEW 3 11 PIN TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 36

37 Adapter Socket CPU ET100-QF49 MC68HC08AB MC68HC08AZ0 Adapter YA-1091 ET100-EYA-QF49 Emul. Adapter for YAMAICHI socket ET100-QF SIDE VIEW TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 37

38 Socket CPU ET64-QF29 MC68HC05B32 MC68HC05D MC68HC05X MC68HC08AB MC68HC08AS MC68HC08AT MC68HC08AZ MC68HC08XL36 MC68HC705-X32 Adapter YA-1121 ET64-EYA-QF29 Emul. Adapter for YAMAICHI socket ET064-QF SIDE VIEW TOP VIEW (all dimensions in mm) ICE Emulator for 68HC05 and 68HC08 38

Simulator for HC08/MSC08

Simulator for HC08/MSC08 TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... TRACE32 Instruction Set Simulators... Simulator for HC08/MSC08... 1 TRACE32 Simulator License... 3 Quick