A 3D Physical Design Flow Based on OpenAccess

Transcription

1 A 3D Physcal Desgn Flow Based on OpenAccess Jason Cong 1,2, Fellow, IEEE, and Guoje Luo 1, Student Member, IEEE 1 Computer Scence Department, Unversty of Calforna, Los Angeles, CA 90095, USA 2 Calforna NanoSystems Insttute, Los Angeles, CA 90095, USA {cong, gluo}@cs.ucla.edu Abstract 3D IC technologes have recently attracted great attenton due to the potental performance mprovement, power consumpton reducton and heterogeneous ntegraton. In ths paper we present a 3D physcal desgn flow based on OpenAccess (named 3D-Craft) to facltate the rapd adopton of 3D IC technologes. The OpenAccess extenson for 3D-Craft s dscussed, and the key components ncludng the 3D placer mpl-3d and the 3D router TMARS are presented. We also demonstrate the applcaton of 3D-Craft for the 3D physcal desgn of an open-source processor, and show that the 3D mplementaton can reduce both the half-permeter wrelength and the routed wrelength by about 30% compared to the 2D mplementaton. T I. INTRODUCTION he 3D IC technologes promse to further ncrease ntegraton densty, beyond Moore's Law, and offer the potental to sgnfcantly reduce nterconnect delays and mprove system performance. Furthermore, the shortened wrelength, especally that of the clock net, also lessens the power consumpton of the crcut. 3D IC technologes also provde a flexble way to carry out the heterogeneous system-on-chp (SoC) desgn by ntegratng dsparate technologes, such as memory and logc crcuts, rado frequency (RF) and mxed sgnal components, optoelectronc devces, etc., onto dfferent layers of a 3D IC. Devce layers n a 3D IC are connected usng through-slcon vas (TS va). However, TS vas are usually etched or drlled through devce layers by specal technques and are costly to fabrcate. A large number of the TS vas wll degrade the yeld of the fnal chp. Also, under current technologes, TS va ptches, usually around 5-10μm, are very large compared to the szes of regular metal wres. In 3D IC structures, TS vas are usually placed at the whtespace between the macro blocks or cells, so the TS vas affect both the routng resources and the overall chp areas. Therefore, the number and dstrbuton of TS vas n a 3D IC needs to be consdered, not only at the routng stage, but also at the floorplannng and placement stages. Another crtcal challenge of 3D IC desgn s heat dsspaton, whch already posed a serous problem even for 2D IC desgns. The thermal problem s exacerbated n the 3D cases manly for two reasons: (1) The vertcally stacked multple layers of actve devces cause a rapd ncrease n power densty; (2) The thermal conductvty of the delectrc Manuscrpt receved May 19, Ths research was partally supported by IBM under a DARPA subcontract, and supported by Natonal Scence Foundaton under grants CCF and CCF layers between the devce layers s very low compared to slcon and metal. For nstance, the thermal conductvty of SO 2 at room temperature (300K) s 1.4 W/mK [12], whch s very much smaller than the thermal conductvty of slcon (150 W/mK) and copper (401 W/mK). Therefore, the thermal ssue needs to be consdered durng every stage of 3D physcal desgn. In recent years, 3D IC physcal desgn has attracted an ncreasng amount of attenton. There s a sgnfcant amount of work on the floorplannng [1][2][14][15][19][21], placement [8][10][11][5][7][18] and routng [3][4][20] for 3D ICs. However, all these tools developed by dfferent groups, usng dfferent formats to represent the desgn data, create barrers for researchers who need to make use of the exstng desgn automaton tools to conduct further studes on 3D IC. Ths problem motvates us to develop an nfrastructure for the 3D desgn data representaton and assst n the nteroperaton of physcal desgn tools. In ths paper we present an OpenAccess [22] extenson for 3D physcal desgn automaton. The man dffculty n developng the OpenAccess extenson s to make t applcable, not only to a specfc 3D IC technology avalable today, but also applcable to other possble 3D IC technologes n the future. The ssues n detal nclude how to represent the multple-ter structure for a 3D IC technology, and how to represent through-slcon vas (TS va) n a 3D desgn. To solve these ssues, we have made the followng contrbutons n ths paper: We defne a database archtecture for 3D physcal desgn based on OpenAccess. Ths archtecture s capable of representng the mult-ter structure n a general way, and t s also capable of representng the structure of TS vas and ther occurrence n a 3D desgn. We mplement 3D-Craft based on the OpenAccess extenson. Ths s a 3D physcal desgn flow ncludng 3D placement, 3D routng and thermal TS va nserton, and the nterface wth commercal detaled routers. The ablty of 3D-Craft s demonstrated through the 3D physcal desgn of an open-source mcroprocessor LEON3 [23]. The physcal desgn results show that the 3-ter 3D mplementaton can reduce both the half-permeter wrelength and routed wrelength by about 30% compared to the 2D mplementaton. The remander of ths paper s organzed as follows. Secton II llustrates an overvew of 3D-Craft, ntroduces OpenAccess and dscusses the ssues and solutons n the extenson for 3D ICs. Secton III presents the key components n 3D-Craft. The

2 applcaton of 3D-Craft on an open-source core s demonstrated n Secton IV. Fnally, Secton V concludes the work and proposes future work. II. OVERVIEW OF 3D-CRAFT AND OPENACCESS EXTENSION FOR 3D PHYSICAL DESIGN The 3D-Craft s physcal desgn flow s llustrated n Fg. 1. Several physcal desgn tools are ntegrated based on the 3D OpenAccess, ncludng a 3D placer, a 3D global router wth thermal TS va planner, and a commercal 2D detaled router. A thermal resstve network model s also ntegrated for thermal evaluatons. The detaled nformaton for ths collecton of physcal desgn tools wll be presented n Secton III. Before we present the components n 3D-Craft, we shall frst ntroduce OpenAccess and dscuss the ssues and solutons n the extenson for 3D physcal desgn. where the attrbutes name, cell name, and orgn are natve attrbutes of the oainst objects. And we use oaintappdef to add an nteger attrbute to these objects for the extended nformaton n 3D desgns. So every nstantaton of oainst ncludes the natve attrbutes of name, cell name, and orgn, as well as the extended attrbute of ter. The detaled use of oaappdef for OpenAccess extenson wll be dscussed n Secton II.C. Fg. 2. An example of the herarchcal desgn database [22] Fg. 3. An example of the oaappdef mechansm Fg. 1. Overvew of 3D-Craft A. Prelmnares on OpenAccess OpenAccess s an nfrastructure desgned and mantaned by S2 [22] to acheve the nteroperablty of EDA applcatons and desgn data. The desgn data management s through a C++ API that defnes classes and member functons to create, access and manpulate the databases. The OpenAccess API conssts of a set of packages, where the technology database package and the desgn database package are the most mportant packages related to place and route (P&R) tools. The technology lbrary holds data that s generally appled across all the desgns developed from a specfc technology. For example, the mnmum wre wdth of a metal layer s specfed n the technology lbrary as a layer constrant. The desgn database refers to desgn-specfc data, whch ncludes cell/macro lbrares and the top desgn that conssts of nstances of cells and macros. The data n the desgn lbrary s represented n a herarchcal way, an example of whch s llustrated n Fg. 2. In ths example, the desgn lbrary contans the cells XOR/AND/OR, the macro HalfAdder, and the top desgn FullAdder. The top desgn conssts of nstances of desgns n the cell lbrary and the macro lbrary. The oaappdef mechansm s a way to add extenson values to exstng database objects, through whch we attach addtonal nformaton to OpenAccess objects to realze the 3D desgn representaton. An example s shown n Fg. 3, B. Issues n Extendng OpenAccess for 3D Physcal Desgn Although OpenAccess s general enough for data representaton of tradtonal 2D desgns, t lacks some necessary features for 3D IC technologes; therefore, there are two very mportant ssues to be consdered n the extenson. The frst ssue s the multple-ter structure n a 3D desgn. Physcally, a 3D desgn can be vewed as a stack of multple 2D desgns, where a sngle 2D desgn s called a ter n terms of 3D IC technologes. There are face-to-back, face-to-face and back-to-back bondng of ters to form a 3D IC. Therefore, the OpenAccess extenson should be able to represent the multple-ter structure and also the bondng method. The other ssue s representaton of through-slcon vas (TS va). TS vas are used for the nterconnecton between dfferent ters. In current 3D IC technologes, the sze of a TS va s comparable to the sze of an nverter, and t also has electrcal and mechancal characterstcs that are dfferent from tradtonal vas; thus, TS vas should be represented explctly and acknowledged by physcal desgn tools. C. Solutons for Extendng OpenAccess for 3D Desgns The database archtecture for 3D desgns conssts of a technology lbrary, a reference lbrary and a desgn lbrary. The technology lbrary stores the technology nformaton of each ter, where each ter has a structure smlar to a sngle 2D desgn. The desgn rules for the metal layers and the tradtonal va layers are descrbed n the technology lbrary, as well as the RC characterstcs of these layers. To represent all ths nformaton, the metal layers and normal va layers are lsted n order from bottom to top. A strng called structure s added to the oatech object by the oaappdef mechansm to

3 descrbe the bondng order of ters and the order of the metal layers and normal va layers. For example, the strng f5b5b5 tells us that there are three ters, f5, b5, and b5, n a 3D chp. The frst ter n a face-on-top ( f ) drecton starts wth a slcon layer, followed by fve ( 5 ) nterconnect layers from metal 1, va 12, metal 2, va 23 to metal 3. The second and thrd ters n a back-on-top ( b ) drecton start wth fve ( 5 ) nterconnect layers frst, from metal 3, va 23, metal 2, va 12 to metal 1, followed by the slcon layer. In such a way, the mult-ter structure s represented n the OpenAccess database, whch s the soluton of the frst ssue referred to Secton II.B. The reference lbrary contans a TS va lbrary and a cell/macro lbrary. Under the assumpton that the sze of a TS va s no larger than the standard cell heght, we capsulate the TS va as a pseudo cell n the TS va lbrary. The metal layer consumptons, as well as the slcon layer consumpton whch a TS va drlls through, are captured by the pseudo cell. Dfferent TS vas connectng dfferent pars of ters may have dfferent structures; thus there are multple pseudo cells n the TS va lbrary. Ths solves the second ssue referred to n Secton II.B. The cell/macro lbrary contans the abstract (boundng box and I/O pns) of standard cells and ntellectual property (IP) blocks that are avalable for a desgn nstance. The desgn lbrary stores the netlst and ts P&R nformaton. The orgnal netlst representaton before placement and routng s the same as the netlst representaton for 2D desgns. After placement, an nteger called ter s added to every oainst, as shown n Fg. 3, to represent whch ter a cell nstance s placed on. After global routng, the TS va locatons are determned, and nstances of the pseudo cells n the TS va lbrary are created to represent these TS vas. When the TS va locatons are determned, t s straghtforward to partton the 3D desgn to multple 2D desgns physcally and run commercal detaled routers. III. COMPONENTS IN 3D-CRAFT A. Resstve Thermal Model In ths work we use the thermal resstve model proposed n [17]. Compared wth an accurate smulaton tool, the error of ths resstve network model s smaller than 2% [17]. A tle structure s mposed on the crcut stack, as shown n Fg. 4(a). Each tle stack contans an array of tles, one from each devce layer, as shown n Fg. 4(b). A tle stack s modeled as a resstve chan as shown n Fg. 4(c). RLateral (a) Tles Stack Array (b) Sngle Tle Fg. 4. Resstve Thermal Model P5 P4 P3 P2 P1 5 R5 4 R4 3 R3 2 R2 1 R1 Rb (c) Tle Stack Analyss The tle stacks are connected by lateral resstances. A voltage source s used for the sothermal base of heat snk temperature, and current sources are present n every tle to represent heat sources. B. Multlevel Placement for 3D ICs (mpl-3d) Gven a crcut represented as a hypergraph H ( V, E), the placement regon R, and the number devce layers K, the task of 3D placement problem s to assgn every cell v V a trple ( x, y, z ), whch ndcates that ths cell s placed on the devce layer z {1, 2, K, K} wth ts center at ( x, y ) R. The objectve s to mnmze the weghted sum of total wrelength and TS va number, under the non-overlap constrants and the TSV densty constrants n each ter. mnmze OBJ ( x, y, z ) l ( e ) v ( e ) subject to ee non-overlap constrants (TSV densty constrants) The objectve functon s a weghted sum of wrelength and TS va number. We estmate the wrelength le () by the half-permeter model, and estmate the TS va number ve () by assumng the cross-ter net s routed as a vertcal-trunk tree. The weghtng factor s used to acheve the tradeoffs between the wrelength le () and the TS va number ve (). The multlevel analytcal placement engne [7] s used for 3D global placement, where t solves the followng problem n a multlevel framework: mnmze OBJ ( x, y, z) Penalty( x, y, z) (2) ncrease untl converge To apply an analytcal solver, the range of the dscrete varable z s relaxed from the set {1, 2,..., K 1} to a contnuous nterval [1, K ]. Then the max operaton n the functon OBJ ( x, y, z ) s smoothed by the log-sum-exp functon [13], and the non-overlap constrants are replaced by the projected smoothed densty constrants on ters and pseudo ters [7] and added to the objectve as a penalty functon. The ntermedate soluton obtaned from global placement roughly satsfes the densty constrants, thus the ter assgnment can be done by smply snappng the cells or the macros to the nearest ter. After ter assgnment, the remanng 2D legalzaton and detaled placement are done ter-by-ter as tradtonal 2D detaled placement. A two-step approach [6] s used for the mxed-sze legalzaton, where the macros are legalzed frst, followed by standard-cell legalzaton. The expermental results n [7] ndcate that a 3D standard cell placement wth four ters can reduce the wrelength by about 50% compared to a 2D placement, f the szes of TS vas are gnored. The results also show that the analytcal placement engne s able to acheve good-qualty tradeoffs between wrelength and TS va number, so t s adaptve for dfferent 3D IC technologes. (1)

4 C. 3D Multlevel Routng wth Thermal TS Va Plannng (TMARS) The thermal-drven 3D routng wth a TS va plannng problem can be descrbed as follows, gven these three nputs: 1) The target 3D IC technology, ncludng desgn rule, heght and thermal conductvty of each materal layer. 2) A 3D crcut placement or floorplan result wth whtespace reserved between blocks for nterlayer nterconnects. 3) A gven maxmum temperature T 0, e.g., 80 o C. Gven these three nputs, the crcut must be routed accordng to the connectng rules and desgn rules, so that the weghted cost of wrelength and the total TS va number s mnmzed. The sze and thermal conductvty dsparty between TS vas and the regular sgnal wres and vas make t dffcult to handle them together. An ndvdual step of TS va plannng also gves us more control over the temperature of the crcut, snce the TS vas are planned drectly nstead of planned through shortest-path searchng. Therefore, our TMARS [3][4] s mplemented as a multlevel 3D routng system wth a novel thermal TS va plannng algorthm. Wth a more global vew and the plannng power of a multlevel plannng scheme, the TS va plannng step can effectvely optmze temperature and wrelength through drect plannng of the TS vas. The expermental results [3][4] show that ths method of smultaneous global routng and thermal TS va plannng can reduce the number of TS vas by 67% wth the same temperature constrant, compared to the method of thermal TS va nserton by post-processng. D. 3D Detaled Routng After the 3D global routng wth sgnal and thermal TS va plannng, the 3D desgn can be decomposed nto several 2D desgns, and there s no dfference between 3D detaled routng and 2D detaled routng. Therefore, t s best to make use of a well-developed commercal detaled router. The decomposed 2D desgns can be routed by any router, ncludng the commercal routers n the Cadence Encounter [24] or the Magma Talus [25]. The routers read n the decomposed crcut and complete the global and detaled routng. Magma Talus supports readng n exstng global routng usng Magma-TCL scrpt. So, we mplemented a tool to exchange the routng data wth Magma Talus. The global routng paths are represented as boxes n the Magma data model. Thus the result of 3D global routng s mported to Talus by creatng boxes usng Magma-TCL scrpt. The tool we mplemented n the flow converts the global routng nto a Magma-TCL scrpt to create those boxes. After loadng the scrpt and runnng the detaled router on these 2D desgns, the tool agan parses the detaled routng nformaton and wrtes back to the 3D desgn lbrary. The routed 3D desgn s obtaned after ths step. IV. 3D PHYSICAL DESIGN EVALUATION We evaluate the beneft on wrelength reducton usng 3D IC technology and the capablty of our 3D-Craft tool wth the open-source processor LEON3 [23]. It s a syntheszable and confgurable 32-bt processor complant wth the SPARC V8 archtecture. We synthesze a sngle-core LEON3 processor based on the NCSU standard cell kt [9] for the MITLL 0.18μm FD-SOI technology. The sze of a TS va s 3 3 μm 2 wth an extra 1.5 μm spacng on each sde, thus a TS va consumes a area of 36 μm 2. We perform physcal desgn and evaluate the wrelengths for the 2D and the 3-ter 3D mplementatons. The syntheszed netlst conssts of standard cells, nets, and 150 I/O ports. The total cell area s mm 2, We defne the 2D and 3D placement regons such that there are 20% whte spaces n total, excludng the area consumed by TS vas. In detal, we defne a mm 2 placement regon for the 2D mplementaton, and a mm 2 placement regon for the 3-ter 3D mplementaton. Snce 2D physcal desgn can be treated as a specal case of 3D physcal desgn, we use 3D-Craft to generate a placement and global routng for both mplementatons. The placement s generated by mpl-3d, and the global routng s generated by Cadence Encounter. We lst the statstcs of the physcal desgn results n TABLE I. The half-permeter wrelength (HPWL) and the wrelength estmated after global routng (routed WL) are computed by Cadence Encounter. The TS vas are nserted by mpl-3d assumng there s only one TS va for every nter-ter net, and for each ter we only count the TS vas (#TSV) that consumes slcon area. The area utlzaton s also reported n the last column. In ths example, the HPWL of the 3-ter 3D mplementaton s 29% shorter than the 2D mplementaton, and the routed wrelength s 37% shorter, whch demonstrates the beneft of the 3D mplementaton. TABLE I Statstcs of the 2D and 3D mplementatons HPWL routed WL #TSV utlzaton (mm) (mm) 2D N/A 0.80 Bottom ter Mddle ter D Top ter Total The placement, TS dstrbuton and routng congeston analyss are shown n Fg. 5. The placements and the TS va dstrbuton are shown n the frst two pctures of each ter, respectvely. The routng congestons on the rght are analyzed by the Cadence Encounter, where the shadng spots represent congested regons. Although there are congested regon n the mddle ter, we observe smlar congestons n the 2D mplementaton, thus the comparson s far. Snce the MITLL 3D IC technology provdes only 3 metal layers for each ter, the routng congestons can be probably solved by adoptng 3D IC technologes that provde more routng resources, or by ntegratng a routablty-drven 3D placer n 3D-Craft.

5 (a) Bottom ter (b) Mddle ter (c) Top ter Fg. 5. The 3D placement by mpl-3d, the TS va dstrbuton, and the routng congeston analyss by Cadence Encounter V. CONCLUSIONS AND FUTURE WORK In ths paper we propose our extenson of OpenAccess for 3D desgns and present 3D-Craft as a referenced 3D physcal desgn flow. The database archtecture for 3D desgns s descrbed, and the mplementaton detals based on an OpenAccess extenson through the oaappdef mechansm s ntroduced. Several physcal desgn tools wth 3D awareness are ntegrated n the 3D-Craft, ncludng the 3D placer mpl-3d and the 3D global router TMARS wth thermal TS va nserton. The applcaton of 3D-Craft on the open-source processor LEON3 shows that the 3-ter 3D mplementaton can reduce both half-permeter wrelength and routed wrelength by about 30% compared to the 2D mplementaton. Future work ncludes the ntegraton of the followng physcal desgn tools: 3D cube packng tools whch support plannng real 3D modules, the 3D power/ground network optmzaton tools, and the 3D clock tree routng tools. ACKNOWLEDGMENT Ths research was partally supported by IBM under a DARPA subcontract, and supported by Natonal Scence Foundaton under grants CCF and CCF The authors would lke to thank Dr. Phlp Chong for hs help on the extenson mechansms of OpenAccess, and wsh to thank Dr. Marek Turowsk and Mr. Patrck Wlkerson from CFD Research Corporaton (CFDRC) for the compact resstve network thermal model. REFERENCES [1] L. Cheng, L. Deng, and M. D. Wong, Floorplannng for 3D VLSI desgn, Proceedngs of IEEE/ACM ASP-DAC 2005, pp , [2] J. Cong, J. We, and Y. Zhang, A Thermal-Drven Floorplannng Algorthm for 3D ICs, Proceedngs of ICCAD 2004, pp , [3] J. Cong and Y. Zhang, Thermal-Drven Multlevel Routng for 3-D ICs, Proceedngs of the 2005 Conference on Asa South Pacfc Desgn Automaton, pp , [4] J. Cong and Y. Zhang, Thermal Va Plannng for 3-D ICs, Proceedngs of the 2005 IEEE/ACM Internatonal Conference on Computer-Aded Desgn, pp , [5] J. Cong, G. Luo, J. We, and Y. Zhang, Thermal-Aware 3D IC Placement Va Transformaton, Proceedngs of the 2007 Conference on Asa South Pacfc Desgn Automaton, pp , [6] J. Cong and M. Xe, A Robust Mxed-Sze Legalzaton and Detaled Placement Algorthm, IEEE Transactons on Computer-Aded Desgn of Integrated Crcuts and Systems, vol. 27, no. 8, pp , August [7] J. Cong and G. Luo, A Multlevel Analytcal Placement for 3D ICs, Proceedngs of the 2009 Conference on Asa and South Pacfc Desgn Automaton, pp , [8] S. Das, Desgn Automaton and Analyss of Three-Dmensonal Integrated Crcuts, PhD Dssertaton, Massachusetts Insttute of Technology, Cambrdge, MA, [9] W.R. Davs, J. Wlson, S. Mck, J. Xu, H. Hua, C. Mneo, A.M. Sule, M. Steer, and P.D. Franzon, Demystfyng 3D ICs: The Pros and Cons of Gong Vertcal, IEEE Desgn & Test of Computers, vol. 22, no. 6, pp , [10] B. Goplen and S. Sapatnekar, Effcent Thermal Placement of Standard Cells n 3D ICs usng a Force Drected Approach, Proceedngs of the 2003 IEEE/ACM Internatonal Conference on Computer-Aded Desgn, pp , [11] B. Goplen and S. Sapatnekar, Placement of 3D ICs wth Thermal and Interlayer Va Consderatons, Proceedngs of the 44th Annual Conference on Desgn Automaton, pp , [12] A.S. Grove, Physcs and Technology of Semconductor Devces, John Wley & Sons, Inc., Hoboken, NJ, [13] D. Hll, Method and System for Hgh Speed Detaled Placement of Cells wthn an Integrated Crcut Desgn, US Patent , Aprl 9, [14] Z. L, X. Hong, Q. Zhou, Y. Ca, J. Ban, H. H. Yang, V. Ptchuman, and C.-K. Cheng, Herarchcal 3-D Floorplannng Algorthm for Wrelength Optmzaton, IEEE Trans. Crcuts and Systems I, Vol.53, ssue 12, pp , [15] Y. Ma, X. Hong, S. Dong and C.K.Cheng, 3D CBL: an Effcent Algorthm for General 3-Dmensonal Packng Problems, Proceedngs of the 48th MWS-CAS 2005, Vol. 2, pp , [16] J.-M. Ln and Y.-W. Chang, TCG: A Transtve Closure Graph Based Representaton for Non-Slcng Floorplans, Proceedngs of ACM/IEEE Desgn Automaton Conference (DAC-2001), pp , Las Vegas, NV, June [17] P. Wlkerson, A. Raman, and M. Turowsk, Fast, Automated Thermal Smulaton of Three-Dmensonal Integrated Crcuts, ITherm 2004, Las Vegas, Nevada, 1-4 June [18] H. Yan, Q. Zhou, and X. Hong, Thermal Aware Placement n 3D ICs Usng Quadratc Unformty Modelng Approach, Integraton, the VLSI Journal, vol. 42, no. 2, pp , [19] T. Yan, Q. Dong, Y. Takashma, and Y. Kajtan, How Does Parttonng Matter for 3D Floorplannng?, Proceedngs of the 16th ACM GLS-VLSI, pp.73-78, [20] T. Zhang, Y. Zhan, and S.S. Sapatnekar, Temperature-Aware Routng n 3D ICs, Proceedngs of the 2006 Conference on Asa South Pacfc Desgn Automaton, pp , [21] P. Zhou, Y. Ma, Z. L, R.P. Dck, L. Shang, H. Zhou, X. Hong, and Q. Zhou, 3D-STAF: scalable temperature and leakage aware floorplannng for three-dmensonal ntegrated crcuts, Proceedngs of ICCAD 2007, pp , [22] [23] [24] [25]