Compiler Optimizations. Lecture 7 Overview of Superscalar Techniques. Memory Allocation by Compilers. Compiler Structure. Register allocation

Transcription

1 Lecture 7 Overview of Superscalar Techniques CprE 581 Computer Systems Architecture, Fall 2013 Reading: Textbook, Ch. 3 Complexity-Effective Superscalar Processors, PhD Thesis by Subbarao Palacharla, Ch.1 1 Compiler Optimizations for (I=1; I < 5; I++) {X = 5; Y = Y + 5*I;} X=5; for (I=1; I < 5; I++) {Y = Y + 5*I;} strength reduction: High-level: in PL/I: L = LENGTH (S1 S2) can be replaced by L = LENGTH (S1) + LENGTH (S2); machine level: replace multiply and divide by a power of 2 by shift. Compiler Structure Front end Memory Allocation by Compilers Stack local scalars High Level Optimizations Heap Data Global Static Data dynamic data, lists in LISP arrays, constants Global Optimizations User Program Code generator Low Addr:0 OS Some Optimizations common sub-exp elimination: A[I+1] := B[I+1]; common subexp: J := I+1; A[J] := =B[J]; Y := 500 * Z/X;.; YY := Z/X; common subexp:tmp := Z/X; Y := 500 * TMP; ; YY := TMP; constant propagation: A := 5; ; B := A * X; B := 5 * X; copy propagation: A := X;.; Y := A / 2; Y := X / 2; code motion: any loop-invariant code can be moved out or move loop code so that loop length decreases. Register allocation most effective for stack scalars. Any aliased variables whether stack or global are hard to allocate: p = &A; *p=50; p=p+x; *p=30; A[32]=10; Call by reference or var also creates aliasing. Actual parameter is an alias for the formal parameter. 1

2 Register Allocation CompilerTechniques How many registers suffice? Spec benchmark profiling suggests registers. The RTL level code assumes infinitely many virtual registers. Register allocation maps virtual registers to physical registers. Technique Loop unrolling Pipeline scheduling Dynamic scoreboard scheduling Dynamic renaming Dynamic branch prediction Compiler dependence analysis Multiple instruction issue Software pipelining/trace scheduling Dynamic memory alias resolution and value prediction Affects Control stalls RAW stalls RAW stalls RAW, WAW, WAR stalls Control stalls Ideal CPI & data stalls Ideal CPI Control stalls, ideal CPI, data stalls Memory stalls (RAW?) Register Allocation ILP within a Basic Block Live Range X X=5; Z=2*Y Z=X+Z; X=3*X; Live Range Y X Y Z Basic block: straight line code single entry, single exit. Gcc branch: 17% typical basic block 6-7 instructions. How much ILP? Beyond single block to get more instruction level parallelism Loop level parallelism one opportunity, SW and HW Live Range: from a definition of a var. to the last use. Register Allocation Loop Level Parallelism Interference Graph X1 X2 X3 X4 X5 X6 Register Assignment: R1: X1, X5, X6 R2: X2, X3, X4 Def X1 Last use X1 Def X5 For (i=1; i<=1000; i++) X[i] = X[i] + Y[i]; No dependence between the data values produced in iteration i and the values needed in iteration i+j. ILP of 1000 loop bodies available! How about the intervening branch instruction between loop iterations! Last use X5 2

3 FP Loop: Where are the Hazards? Loop: LD F0,0(R1) ;F0=vector element ADDD F4,F0,F2 ;add scalar from F2 SD 0(R1),F4 ;store result SUBI R1,R1,8 ;decrement pointer 8B (DW) BNEZ R1,Loop ;branch R1!=zero NOP ;delayed branch slot Instruction Instruction Latency in producing result using result clock cycles FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 Load double Store double 0 Integer op Integer op 0 Where are the stalls? Revised FP Loop Minimizing Stalls 2 stall 3 ADDD F4,F0,F2 4 SUBI R1,R1,8 5 BNEZ R1,Loop ;delayed branch 6 SD 8(R1),F4 ;altered when move past SUBI Swap BNEZ and SD by changing address of SD Instruction Instruction Latency in producing result using result clock cycles FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 6 clock cycles: Unroll loop 4 times to make code faster? FP Loop Hazards Loop:LD F0,0(R1) ;F0=vector element ADDD F4,F0,F2 ;add scalar in F2 SD 0(R1),F4 ;store result SUBI R1,R1,8 ;decrement pointer 8B (DW) BNEZ R1,Loop ;branch R1!=zero NOP ;delayed branch slot Instruction Instruction Latency in producing result using result clock cycles FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 Load double Store double 0 Integer op Integer op 0 Unroll Loop Four Times (straightforward way) Rewrite loop to minimize 2 ADDD F4,F0,F2 3 SD 0(R1),F4 ;drop SUBI & BNEZstalls? 4 LD F6,-8(R1) 5 ADDD F8,F6,F2 6 SD -8(R1),F8 ;drop SUBI & BNEZ 7 LD F10,-16(R1) 8 ADDD F12,F10,F2 9 SD -16(R1),F12 ;drop SUBI & BNEZ 10 LD F14,-24(R1) 11 ADDD F16,F14,F2 12 SD -24(R1),F16 13 SUBI R1,R1,#32 ;alter to 4*8 14 BNEZ R1,LOOP 15 NOP x (1+2) = 27 clock cycles, or 6.8 per iteration Assumes R1 is multiple of 4 FP Loop Showing Stalls ;F0=vector element 2 stall 3 ADDD F4,F0,F2 ;add scalar in F2 4 stall 5 stall 6 SD 0(R1),F4 ;store result 7 SUBI R1,R1,8 ;decrement pointer 8B (DW) 8 BNEZ R1,Loop ;branch R1!=zero 9 stall ;delayed branch slot Instruction Instruction Latency in producing result using result clock cycles FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 9 clock cycles: Rewrite code to minimize stalls? Unrolled Loop That Minimizes Stalls 2 LD F6,-8(R1) 3 LD F10,-16(R1) 4 LD F14,-24(R1) 5 ADDD F4,F0,F2 6 ADDD F8,F6,F2 7 ADDD F12,F10,F2 8 ADDD F16,F14,F2 9 SD 0(R1),F4 10 SD -8(R1),F8 11 SD -16(R1),F12 12 SUBI R1,R1,#32 13 BNEZ R1,LOOP What assumptions made when moved code? OK to move store past SUBI even though changes register OK to move loads before stores: get right data? 14 SD 8(R1),F16 ; 8-32 = -24 When is it safe for 14 clock cycles, or 3.5 per iteration compiler to do such When safe to move instructions? changes? 3

4 Compiler Perspectives on Code Movement Definitions: compiler concerned about dependences in program, whether or not a HW hazard depends on a given pipeline. Try to schedule to avoid hazards. (True) Data dependences (RAW if a hazard for HW) Instruction i produces a result used by instruction j, or Instruction j is data dependent on instruction k, and instruction k is data dependent on instruction i. If dependent, can t execute in parallel. Easy to determine for registers (fixed names). Hard for memory: Does 100(R4) = 20(R6)? From different loop iterations, does 20(R6) = 20(R6)? Where are the name dependences? 2 ADDD F4,F0,F2 3 SD 0(R1),F4 ;drop SUBI & BNEZ 4 LD F0,-8(R1) 5 ADDD F4,F0,F2 6 SD -8(R1),F4 ;drop SUBI & BNEZ 7 LD F0,-16(R1) 8 ADDD F4,F0,F2 9 SD -16(R1),F4 ;drop SUBI & BNEZ 10 LD F0,-24(R1) 11 ADDD F4,F0,F2 12 SD -24(R1),F4 13 SUBI R1,R1,#32 ;alter to 4*8 14 BNEZ R1,LOOP 15 NOP How can we remove them? Where are the data dependences? 2 ADDD F4,F0,F2 3 SUBI R1,R1,8 4 BNEZ R1,Loop ;delayed branch 5 SD 8(R1),F4;altered when move past SUBI Where are the name dependences? 2 ADDD F4,F0,F2 3 SD 0(R1),F4 ;drop SUBI & BNEZ 4 LD F6,-8(R1) 5 ADDD F8,F6,F2 6 SD -8(R1),F8 ;drop SUBI & BNEZ 7 LD F10,-16(R1) 8 ADDD F12,F10,F2 9 SD -16(R1),F12 ;drop SUBI & BNEZ 10 LD F14,-24(R1) 11 ADDD F16,F14,F2 12 SD -24(R1),F16 13 SUBI R1,R1,#32 ;alter to 4*8 14 BNEZ R1,LOOP 15 NOP Called register renaming Compiler Perspectives on Code Movement Another kind of dependence called name dependence: two instructions use same name (register or memory location) but don t exchange data Antidependence (WAR if a hazard for HW) Instruction j writes a register or memory location that instruction i reads from and instruction i is executed first Output dependence (WAW if a hazard for HW) Instruction i and instruction j write the same register or memory location; ordering between instructions must be preserved. Compiler Perspectives on Code Movement Again Name Dependences are Hard for Memory Accesses Does 100(R4) = 20(R6)? From different loop iterations, does 20(R6) = 20(R6)? Our example required compiler to know that if R1 doesn t change then: 0(R1) -8(R1) -16(R1) -24(R1) There were no dependences between some loads and stores so they could be moved. 4

5 Compiler Perspectives on Code Movement Final kind of dependence called control dependence Example if p1 {S1;}; if p2 {S2;}; S1 is control dependent on p1 and S2 is control dependent on p2 but not on p1. When Safe to Unroll Loop? Example: Where are data dependencies? (A,B,C distinct & nonoverlapping) for (i=1; i<=100; i=i+1) { A[i+1] = A[i] + C[i]; /* S1 */ B[i+1] = B[i] + A[i+1];} /* S2 */ 1. S2 uses the value, A[i+1], computed by S1 in the same iteration. 2. S1 uses a value computed by S1 in an earlier iteration, since iteration i computes A[i+1] which is read in iteration i+1. The same is true of S2 for B[i] and B[i+1]. This is a loop-carried dependence : between iterations Implies that iterations are dependent, and can t be executed in parallel In our prior example; each iteration was distinct/independent. Compiler Perspectives on Code Movement Two (obvious) constraints on control dependences: An instruction that is control dependent on a branch cannot be moved before the branch so that its execution is no longer controlled by the branch. An instruction that is not control dependent on a branch cannot be moved to after the branch so that its execution is controlled by the branch. Control dependences relaxed to get parallelism; preserve order of exceptions and data flow. Sequential Execution Model Any program execution is correct if the final architectural states (registers and memory contents) match the final state of sequential execution Single-cycle implementation is intuitively correct If instructions are not executed sequentially, what is correct execution? 29 Where are the control dependences? 2 ADDD F4,F0,F2 3 SD 0(R1),F4 4 SUBI R1,R1,8 5 BEQZ R1,exit 6 LD F0,0(R1) 7 ADDD F4,F0,F2 8 SD 0(R1),F4 9 SUBI R1,R1,8 10 BEQZ R1,exit 11 LD F0,0(R1) 12 ADDD F4,F0,F2 13 SD 0(R1),F4 14 SUBI R1,R1,8 15 BEQZ R1,exit... Out-of-order Execution Compared with a sequential execution, an out-of-order execution may 1. Fetch and execute instructions that should not be executed 2. Execute instructions in a different order 30 5

6 Sequential Execution Model A program execution is correct if 1. The same set of instructions write to user-visible register and memory; 2. Each instruction receives the same operands as in the sequential execution; and 3. Any register or memory word receives the value of the last write as in the sequential execution Data Dependences Instruction J is dependent on I if I s output is used by J, or J is dependent on K, and K is dependent on I Loop: L.D F0,0(R1) ADD.D F4,F0,F2 S.D F4,0(R1) DADDUI R1,R1,#-8 BNE R1,R2,LOOP Data Dependence Graph L.D ADD.D S.D DADDUI BNE Dependences and Correctness Three types of dependences between instructions Control dependence Data dependence Name dependence Why do we care about dependences? Processor hardware can observe those dependences By correctly handling the dependences, sequential execution model will hold 32 Data Dependences Dependences through registers Load regfile ALU Load ALU Br Store ADD r8, r9, r10 BEQ r8, r11, loop Dependence through memory SW LW Memory SW r8, 100(r9) LW r10, 100(r9) 35 Data Dependence Name Dependences LD F2,0(R3) MULTI F0,F2,F4 LD F6,0(R2) SUBD F8,F6,F2 DIVD F10,F0,F6 ADD F12,F8,F2 Note: no branch in this code LD1 MULTI DIVD LD2 SUBD ADD Antidependence (WAR): one instruction overwrite a register or memory location that a prior instruction reads Output dependence (WAW): two instructions write the same register or memory location LW R1, 100(R2) ADD R2, R3, R4 LW R1, 100(R2) Add R2, R1, R2 Add R1, R3, R4 These dependences can be removed

7 Dependences vs Hazards Dependences are properties of programs Hazards are properties of pipelines Dependences indicate the potential for hazards Pipeline implementations determine actual hazards and the length of any stall What hazards are exposed by MIPS 5-stage pipeline? Dependences between Operations Store to load //R3+100==R4? S.D F6,100(R3) L.D F2,0(R4) S.D L.D IF IF ID ID EX EX MEM --? WB MEM Register instruction can be detected by matching register index Detecting memory dependence is more difficult Dynamic Scheduling Dynamic Scheduling General idea: when an instruction stalls, look for independent instructions following it DIV.D F0, F2, F4 ADD.D F10, F0, F8 SUB.D F12, F8, F14 DIV.D ADD.D SUB.D Instruction window: how far to look ahead Out-of-order execution Respect data dependence L.D MULTI L.D SUB.D DIV.D ADD.D F2,0(R3) F0,F2,F4 F6,0(R2) F8,F6,F2 F10,F0,F6 F12,F8,F2 LD1 MULTI DIVD LD2 SUBD ADD What hazards would be exposed? How to schedule pipeline operations? Data Dependence between Operations Is This Working? ALU to ALU SUBD F8,F6,F2 ADD F6,F8,F2 SUBD ADD IF IF ID ID EX -- WB EX WB Load and other insts LD F2,0(R3) MULTI F0,F2,F4 LD MULTI IF IF ID ID EX -- MEM -- WB EX WB 39 Inst IF ID Schd EXE MEM WB L.D MULT L.D SUB.D DIV.D Add.D Assume (1) two-way issue; (2) FU delay as implied 42 7

8 HW Schemes: Instruction Level Parallelism Why in HW at run time? Not all dependences are known at compile time. Compiler simpler. Code for one machine runs well on another. Key idea: Allow instructions behind stall to proceed DIVD F0,F2,F4 ADDD F10,F0,F8 SUBD F12,F8,F14 Enables out-of-order execution => out-of-order completion. ID stage checks both for structural & data hazards. Separate structural & data hazard checks. Scoreboard dates to CDC 6600 in Processor Micro-arch. with Scoreboard Registers Control/ status Scoreboard Data buses Control/ status FP mult FP divide FP add Integer unit HW Schemes: Instruction Level Parallelism Out-of-order execution divides ID stage: 1. Issue decode instructions, check for structural hazards 2.Read operands wait until no data hazards, then read operands Scoreboards allow instruction to execute whenever 1 & 2 hold, not waiting for prior instructions. CDC 6600: In order issue, out of order execution, out of order commit ( also called completion). Four Stages of Scoreboard Control 1. Issue decode instructions & check for structural hazards (ID1: If a function unit for the instruction is free and no other active instruction has the same destination register (WAW), the scoreboard issues the instruction to the function unit and updates its internal data structure. If a structural or WAW hazard exists, then the instruction issue stalls, and no further instructions will issue until these hazards are cleared. 2. Read operands wait until no data hazards, then read operands (ID2):A source operand is available if no earlier issued active instruction is going to write it, or if the register containing the operand is being written by a currently active function unit. When the source operands are available, the scoreboard tells the function unit to proceed to read the operands from the registers and begin execution. The scoreboard resolves RAW hazards dynamically in this step, and instructions may be sent into execution out of order. Scoreboard Implications Out-of-order completion => WAR, WAW hazards? Solutions for WAR: Queue both the operation and copies of its operands. Read registers only during Read Operands stage. For WAW, must detect hazard: stall until other instruction completes. Need to have multiple instructions in execution phase => multiple execution units or pipelined execution units. Scoreboard keeps track of dependences, state or operations. Scoreboard replaces ID, EX, WB with 4 stages. Four Stages of Scoreboard Control 3. Execution operate on operands (EX) The function unit begins execution upon receiving operands. When the result is ready, it notifies the scoreboard that it has completed execution. 4. Write result finish execution (WB) Once the scoreboard is aware that the function unit has completed execution, the scoreboard checks for WAR hazards. If none, it writes results. If WAR, then it stalls the instruction. Example: DIVD F0,F2,F4 ADDDF10,F0,F8 SUBD F8,F8,F14 CDC 6600 scoreboard would stall SUBD until ADDD reads operands 8

9 Scoreboard Example Instruction status Read ExecuWrite Inst. j k Issue opera compl Result LD F6 34+ R2 LD F2 45+ R3 MULTD F0 F2 F4 Function unit status dest S1 S2 FU for j FU for k Fj? Fk? Integer No Mult1 No FU Scoreboard Example Cycle 2 LD F6 34+ R2 1 2 LD F2 45+ R3 MULTDF0 F2 F4 Integer Yes Load F6 R2 Yes Mult1 No 2 FU Issue 2nd LD? Integer Detailed Scoreboard Pipeline Control Instruction status Issue Read operands Execution complete Write result Op D, S1, S2 Wait until Not busy (FU) and not result(d) Rj and Rk Functional unit done f((fj( f ) Fi(FU) or Rj( f )=No) & (Fk( f ) Fi(FU) or Rk( f )=No)) Bookkeeping Busy(FU) yes; Op(FU) op; Fi(FU) `D ; Fj(FU) `S1 ; Fk(FU) `S2 ; Qj Result( S1 ); Qk Result(`S2 ); Rj not Qj; Rk not Qk; Result( D ) FU; Rj No; Rk No f(if Qj(f)=FU then Rj(f) Yes); f(if Qk(f)=FU then Rk(f) Yes); Result(Fi(FU)) 0; Busy(FU) No Scoreboard Example Cycle 3 LD F6 34+ R LD F2 45+ R3 MULTD F0 F2 F4 Integer Yes Load F6 R2 No Mult1 No 3 FU Integer Issue MULT? Scoreboard Example Cycle 1 Instruction status Read Execu Write Instruction j k Issue operancompleresult LD F6 34+ R2 1 LD F2 45+ R3 MULTD F0 F2 F4 Integer Yes Load F6 R2 Yes Mult1 No 1 FU Integer Scoreboard Example Cycle 4 LD F2 45+ R3 MULTD F0 F2 F4 Integer Yes Load F6 R2 No Mult1 No 4 FU Integer 9

10 Scoreboard Example Cycle 5 LD F2 45+ R3 5 MULTD F0 F2 F4 Integer Yes Load F2 R3 Yes Mult1 No 5 FU Integer Scoreboard Example Cycle 8a LD F2 45+ R MULTDF0 F2 F Integer Yes Load F2 R3 No Mult1 Yes Mult F0 F2 F4 Integer No Yes Add Yes Sub F8 F6 F2 IntegerYes No Divide Yes Div F10 F0 F6 Mult1 No Yes 8 FU Mult1Integer Add Divide Scoreboard Example Cycle 6 LD F2 45+ R3 5 6 MULTDF0 F2 F4 6 Integer Yes Load F2 R3 Yes Mult1 Yes Mult F0 F2 F4 Integer No Yes 6 FU Mult1Integer Scoreboard Example Cycle 8b LD F2 45+ R MULTDF0 F2 F Integer No Mult1 Yes Mult F0 F2 F4 Yes Yes Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 8 FU Mult1 Add Divide Scoreboard Example Cycle 7 LD F2 45+ R MULTD F0 F2 F4 6 7 Integer Yes Load F2 R3 No Mult1 Yes Mult F0 F2 F4 Integer No Yes Add Yes Sub F8 F6 F2 IntegerYes No 7 FU Mult1Integer Add Read multiply operands? Scoreboard Example Cycle 9 LD F2 45+ R MULTDF0 F2 F Integer No 10 Mult1 Yes Mult F0 F2 F4 Yes Yes 2Add Yes Sub F8 F6 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 9 FU Mult1 Add Divide Read operands for MULT & SUBD? Issue ADDD? 10

11 Scoreboard Example Cycle 11 LD F2 45+ R MULTDF0 F2 F Integer No 8Mult1 Yes Mult F0 F2 F4 No No 0Add Yes Sub F8 F6 F2 No No Divide Yes Div F10 F0 F6 Mult1 No Yes 11 FU Mult1 Add Divide Dynamic Scheduling Implementation Wakeup I1 I2 I3 I_k SELECT To FUs Adapted from UCB CS252 S98, Copyright 1998 USB Scoreboarding: 1966: scoreboarding in CDC6600 Tomasulo: Three years later in IBM 360/91 Introduced register renaming Use tag-based instruction wakeup 64 Scoreboard Example Cycle 12 LD F2 45+ R MULTDF0 F2 F Integer No 7Mult1 Yes Mult F0 F2 F4 No No Divide Yes Div F10 F0 F6 Mult1 No Yes 12 FU Mult1 Divide Read operands for DIVD? Name Dependences and Register Renaming Original code: ADD R3, R1, R2 SUB R4, R4, R3 ADD R3, R6, R7 SUB R3, R3, R4 What prevents parallelism? Renamed code: R3, R4, R3, R3 renamed to P6, P7, P8, P9 sequentially ADD P6, R1, R2 SUB P7, R4, P6 ADD P8, R6, R7 SUB P9, R5, P7 Finally R3 <= P9, R4 <= P7 65 Scoreboard Example Cycle 13 LD F2 45+ R MULTD F0 F2 F Function unit status dest S1 S2 FU forfu for Fj? Fk? Integer No 6Mult1 Yes Mult F0 F2 F4 No No Add Yes Add F6 F8 F2 Yes Yes Divide Yes Div F10 F0 F6 Mult1 No Yes 13 FU Mult1 Add Divide Register Renaming and Correctness 1. The same set of instructions write to user-visible register and memory; 2. Each instruction receives the same operands as in the sequential execution; and 3. Any register or memory word receives the value of the last write as in the sequential execution 66 11

12 Renaming Implementation First proposed in Tomasulo (1969) Use register status table Renamed to reservation station In P-III Use register alias table Renamed arch. register to physical register Data copied back to arch. register In other processors (e.g. Alpha 21264, Intel P4) Use register mapping table No separate architectural/physical registers; no copy-back Pd Rd Rs Rt Renaming Branch Prediction and Speculative Execution Branch prediction control speculation Must predict on branches What to predict Branch direction Branch target address What info can be used PC value Previous branch outputs also use branch pattern in complex branch predictors What building blocks are need Branch prediction table (BHT), branch target buffer (BTB), pattern registers, and some logics Ps Pt Branch Prediction and Speculative Execution Modern processors must speculate! Branch prediction: SPEC2k INT has one branch per seven instructions! Precise interrupt Memory disambiguation More performance-oriented speculations Generic Superscalar Processor Models Issue queue based Fetch Rename Wakeup select schedule Reservation based Regfile bypass FU FU execute D-cache commit Two disjointed but connected issues: 1. How to make the best prediction 2. What to do when the speculation is wrong Fetch Rename Reg ROB Wakeup select schedule bypass FU FU execute D-cache commit 68 Revised from Paracharla PhD thesis Branch Prediction and Speculative Execution Review the three conditions of correctness: 1. The processor commits the same set of instructions as executed in a sequential processor 2. Any committed instruction receives the same operands (from its parents) as in the sequential execution 3. Any register or memory word receives the value of the last write from the committed instructions and as in the sequential execution 69 12