Multi-cycle Instructions in the Pipeline (Floating Point)

Transcription

1 Lecture 6 Multi-cycle Instructions in the Pipeline (Floating Point) Introduction to instruction level parallelism Recap: Support of multi-cycle instructions in a pipeline (App A.5) Recap: Superpipelining (App A.6) Introduction to instruction level parallelism: ILP (3.1) Bits and pieces on simple superscalars and VLIWs (3.6, 4.1, 4.3) IF ID MEM WB Integer unit: Floating point units: EX M1 M2 M3 M4 M5 M6 M7 A1 A2 A3 A4 DIV Handles integer instructions, branches and loads/stores May take several cycles each Structural and RAW hazards To resolve these hazards: Structural hazards. Stall in ID stage if: the functional unit is occupied (applicable to DIV only) any instruction already executing will reach the WB at the same time as the current RAW hazards: Normal bypassing from MEM and WB stages Stall in ID stage if any of the source operands is destination operand in any of the FP functional units Resolving WAR and WAW Hazards for Multi-cycle Instructions There are no WAR-hazards since the operands are read before the EX-stages in the pipeline Example of a WAW hazard: DIV.D F0,F2,F4 FP divide 24 cycles SUB.D F0,F8,F10 FP sub 3 cycles The SUB finishes before the DIV which will overwrite the result made by the SUB! WAW hazards are eliminated by: Stall the SUB.D until DIV.D reaches the MEM stage, or Disable the write to register F0 for the DIV.D instruction 1

2 To Interrupt or not to Interrupt Example: DIV.D F0,F2,F4 24 cycles ADD.D F10,F10,F8 3 cycles SUB.D F12,F12,F14 3 cycles Suppose the SUB.D instruction generates an arithmetic trap and that the DIV.D instruction hasn t completed Imprecise interrupt signalling Another problem with out-of-order completion Handling imprecise interrupts Ignore Pro: Simple and high performance Con: It is not possible to tie the interrupt to a certain instruction Buffer the results of earlier operations Con: may require large buffers and high complexity hardware Somewhat imprecise interrupts but with state information so that trap-handling routines can create a precise instruction sequence Determine if interrupts are possible early in the pipeline (so that order is maintained at interrupt detection) Lecture 6 The MIPS R4000 Pipeline Introduction to instruction level parallelism Recap: Support of multi-cycle instructions in a pipeline (App A.5) Recap: Superpipelining (App A.6) Introduction to instruction level parallelism: ILP (3.1) Bits and pieces on simple superscalars and VLIWs (3.6, 4.1, 4.3) IF IS RF EX DF DS TC WB MIPS: IF ID EX MEM WB Instruction fetch is done in the IF and IS stages speculatively independent of a cache hit or miss RF performs the same as ID in old MIPS but also check for instruction cache hit/miss The MEM stage in old MIPS is divided into three stages (DF, DS, and TC). Cache misses are detected in TC (Tag check) WB is the same as in old MIPS 2

3 R4000 Performance SPEC92 CPI measurements: Average CPI Load Branch FP data hazard FP struct. Hazard Compared to the old MIPS (CPI=1.54 for gcc, TeX and spice), R4000 has, as expected, a higher CPI The penalty for control hazards is very high for integer programs (up to 0.36) The penalty for FP data hazards is also high The higher clock frequency compensates for the higher CPI Lecture 6 Introduction to instruction level parallelism Recap: Support of multi-cycle instructions in a pipeline (App A.5) Recap: Superpipelining (App A.6) Introduction to instruction level parallelism: ILP (3.1) Bits and pieces on simple superscalars and VLIWs (3.6, 4.1, 4.3) Instruction Level Parallelism - ILP ILP: Overlap execution of unrelated instructions Example: DIV.D F0,F2,F4 ADD.D F10,F1,F2 SUB.D F8,F8,F14 These instructions are independent and could be executed in parallel gcc has 17% control transfer instructions: 5 sequential instructions / branch We must look beyond a single basic block to get more ILP Loop level parallelism one opportunity, SW & HW Loop-level Parallelism Example: for (i=1000; i>0; i=i-1) x[i] = x[i] + 10; There is very little available parallelism within an iteration However, there is parallelism between loop iterations; each iteration is independent of the other Potential speedup = 1000!!! 3

4 MIPS-code for the Loop loop: L.D F0, 0(R1) ; F0 = array element ADD.D F4, F0, F2 ; Add scalar constant S.D F4,0(R1) ; Save result DADDIU R1, R1, #-8 ; decrement array ptr. BNE R1, loop ; reiterate if R1!= 0 Instruction producing result Instruction using result FP ALU op Another FP ALU op 3 FP ALU op Store double 2 Load double FP ALU op 1 Latency Loop Showing Stalls 1 loop: L.D F0, 0(R1) ; F0 = array element 2 stall 3 ADD.D F4, F0, F2 ; Add scalar constant 4 stall 5 stall 6 S.D F4,0(R1) ; Save result 7 DADDIU R1, R1, #-8 ; decrement array ptr. 8 BNE R1, loop ; reiterate if R1!= 0 9 nop Load double Store double 0 Integer op Integer op 0 Where are the stalls? How can we get rid of the stalls? Restructured Loop Minimising Stalls 1 loop: L.D F0, 0(R1) ; F0 = array element 2 DADDIU R1, R1, #-8 ; decrement array ptr. 3 ADD.D F4, F0, F2 ; Add scalar constant 4 stall 5 BNE R1, loop ; reiterate if R1!= 0 6 S.D F4, 8(R1) ; Save result Swap DADDIU and S.D by changing offset in SD 6 clock cycles per iteration Sophisticated compiler analyses required Can we do better? Unroll Loop Four Times Straightforward Way 1 loop: L.D F0, 0(R1) 2 ADD.D F4, F0, F2 3 S.D F4,0(R1), ; drop DADDIU & BNE 4 L.D F6, -8(R1) 5 ADD.D F8, F6, F2 6 S.D F8,-8(R1) ; drop DADDIU & BNE 7 L.D F10, -16(R1) 8 ADD.D F12, F10, F2 9 S.D F12,-16(R1) ; drop DADDIU & BNE 10 L.D F14, -24(R1) 11 ADD.D F16, F14, F2 12 S.D F16,-24(R1) 13 DADDIU R1, R1, #-32 ; alter to 4*8 14 BNE R1, loop 15 NOP *(1+2) + 1 = 28 clock cycles, or 7 per iteration Assumes R1 is a multiple of 4 4

5 Scheduled Unrolled Loop 1 loop: L.D F0, 0(R1) 2 L.D F6, -8(R1) 3 L.D F10, -16(R1) 4 L.D F14, -24(R1) 5 ADD.D F4, F0, F2 6 ADD.D F8, F6, F2 7 ADD.D F12, F10, F2 8 ADD.D F16, F14, F2 9 S.D F4,0(R1) 10 S.D F8,-8(R1) 11 DADDIU R1, R1, # S.D F12,16(R1) ; = BNE R1, loop 14 S.D F16,8(R1) ; 8-32 = clock cycles, or 3.5 per iteration When is it safe to move instructions? Assumptions made: OK to move store past SUBI even though register changes OK to move loads before stores: get right data? When can the compiler make these assumptions safely? Why loop unrolling works Longer sequences of straight code without branches (longer basic blocks) allows for easier compiler static rescheduling Longer basic blocks also facilitates dynamic rescheduling such as Tomasulo s algorithm (see chapter 3.2) Dependencies Two instruction must be independent in order to execute in parallel There are three general types of dependencies that limit parallelism: Data dependencies Name dependencies Control dependencies Dependencies are properties of the program Whether a dependency leads to a hazard or not is a property of the pipeline implementation Data Dependencies An instruction j is data dependent on instruction i if: Instruction i produces a result used by instr. j, or Instruction j is data dependent on instruction k and instr. k is data dependent on instr. j Example: L.D F0,0(R1) ADD.D F4,F0,F2 S.D F4, 0(R1) Easy to detect for registers, hard for memory locations 5

6 Name Dependencies Two instructions use same name (register or memory address) but do not exchange data Antidependence (WAR if hazard in HW) ADD.D F2,F0,F2 ; Must execute before LD L.D F0,0(R1) Output dependence (WAW if hazard in HW) ADD.D F0,F2,F2 ; Must execute before LD L.D F0,0(R1) Where Are the Name Dependencies? 1 loop: L.D F0, 0(R1) 2 ADD.D F4, F0, F2 3 S.D F4, 0(R1) ; drop ADDIU & BNE 4 L.D F0, -8(R1) 5 ADD.D F4, F0, F2 6 S.D F4, -8(R1) ; drop ADDIU & BNE 7 L.D F0, -16(R1) 8 ADD.D F4, F0, F2 9 S.D F4, -16(R1) ; drop ADDIU & BNE 10 L.D F0, -24(R1) 11 ADD.D F4, F0, F2 12 S.D F4, -24(R1) 13 ADDIU R1, R1, #-32 ; alter to 4*8 14 BNE R1, loop 15 NOP How can we remove them? Control Dependencies Determines the order between an instruction and a branch instruction Example: if Test1 then { S1 } if Test2 then { S2 } S1 is control dependent on Test1 S2 is control dependent on Test2; but not on Test1 We cannot move an instruction that is dependent on a branch before the branch instruction We cannot move an instruction not control dependent on a branch after the branch instr. Lecture 6 Introduction to instruction level parallelism Recap: Support of multi-cycle instructions in a pipeline (App A.5) Recap: Superpipelining (App A.6) Introduction to instruction level parallelism: ILP (3.1) Bits and pieces on simple superscalars and VLIWs (3.6, 4.1, 4.3) 6

7 Getting CPI < 1! Issuing multiple instructions per clock cycle (IPC > 1) Superscalar: varying number of instructions/cycle (1-8) scheduled by compiler or HW AMD K7, Opteron, Intel Ppro, Pentium II/III/4/M, most high Simple hardware, complicated compiler or... Very complex hardware but simple for compiler Very Long Instruction Word (VLIW): fixed number of instructions (3-5) scheduled by the compiler IA-64, many DSPs, graphics and media processors Simple hardware, difficult for compiler Requires change of ISA! A Superscalar MIPS Issue 2 instructions each cycle: 1 integer & 1 FP instr. Fetch 64 bits/cycle; one integer instr. and one FP Other combinations possible! Pentium allowed a subset of instructions to be executed in parallel Can only issue 2nd instr. if 1st instr. issues Type Pipe stages Int. IF ID EX MEM WB FP IF ID EX MEM WB Int. IF ID EX MEM WB FP IF ID EX MEM WB Int. IF ID EX MEM WB FP IF ID EX MEM WB EX stage must be fully pipelined to exploit ILP One load delay slot leads to three instructions delay before data can be used! Program example Add a scalar value to an array in memory: Loop: L.D F0, 0(R1) ; Load array el. to F0 ADD.D F4, F0, F2 ; add scalar in F2 S.D F4, 0(R1) ; Store result ADDIU R1, R1, #8 BNE R1, Loop Assume loop unrolled 5-6 times Static Superscalar MIPS Integer instruction FP instruction Clock cycle L o o p : L D F 0, 0 (R 1 ) 1 L D F 6, -8 (R 1 ) 2 L D F 1 0, -1 6 (R 1 ) A D D D F 4, F 0, F 2 3 L D F 1 4, -2 4 (R 1 ) A D D D F 8, F 6, F 2 4 L D F 1 8, -3 2 (R 1 ) A D D D F 1 2, F 1 0, F 2 5 S D 0 (R 1 ), F 4 A D D D F 1 6, F 1 4, F 2 6 S D -8 (R 1 ), F 8 A D D D F 2 0, F 1 8, F 2 7 S D -1 6 (R 1 ), F S D -2 4 (R 1 ), F SUBI R 1,R1,# B N E Z R 1, L o o p 1 1 S D -3 2 (R 1 ),F Difficult to find enough instructions to issue at the same time However, relatively simple hardware 7

8 Limits of Superscalar While integer/fp split is simple for the HW the CPI will be 0.5 only for programs with: Exactly 50% FP operations No hazards If more instructions are issued at the same time, it becomes more difficult to decode and issue For a 2-way SS the ID stage need to examine 2 opcode, 6 reg. specs and decide if 1 or 2 instructions can issue Data and control dependencies are in general more costly in a superscalar pipeline Very Long Instruction Word (VLIW) A number of functional units that independently execute instructions in parallel. No hazard detection needed! The compiler decides which instructions can execute in parallel and puts them in an VLIW instruction Mem ref 1 Mem ref 2 FP op 1 FP op 2 Int op/ branch Clock LD F0,0(R1) LD F6,-8(R1) 1 LD F10,-16(R1) LD F14,-24(R1) 2 LD F18,-32(R1) LD F22,-40(R1) ADDD F4,F0,F2 ADDD F8,F6,F2 3 LD F26,-48(R1) ADDD F12,F10,F2 ADDD F16,F14,F2 4 ADDD F20,F18,F2 ADDD F24,F22,F2 5 SD 0(R1), F4 SD -8(R1), F8 ADDD F28,F26,F2 6 SD -16(R1), F12 SD -24(R1), F8 7 SD -32(R1),F20 SD -40(R1),F24 SUBI R1,R1,#48 8 SD 0(R1),F28 BNEZ R1,LOOP 9 Limits of VLIW Limited Instruction Level Parallelism With n functional units and k pipeline stages we need n x k independent instructions to utilize the hardware Memory and register bandwidth With increasing number of functional units, the number of ports needed at the memory or register file must increase to prevent structural hazards Code size Compiler scheduled pipeline bubbles take up space in the instruction Need more aggressive loop unrolling to work well which also increases code size No binary code compatibility Limits on ILP, a taste of things Theoretically available ILP very high! Practically available much lower (~3-10 instructions per cycle) Current aggressive processors can reach an ILP of about in the absence of memory operations. Memory operations are costly and are becoming increasingly more costly. ILP can be used to somewhat hide memory latency. ILP cost more than it is worth? This is an debated open question but recent trends move away from extremely complex processors. More about this in a few weeks! Cliffhanger! 8

9 Summary See ya! Multi-cycle instructions: Multi-cycle instructions must execute in parallel with other instructions to achieve high performance Requires more sophisticated hazard analysis to detect: RAW hazards WAR hazards WAW hazards Longer pipelines: Higher clock frequency Increasing CPI limits performance ILP: Rescheduling and loop unrolling are important to take advantage of the potential Instruction Level Parallelism Multiple issue Superscalar VLIW 9