Reliability and Energy-aware Cache Reconfiguration for Embedded Systems

Transcription

1 Relablty and Energy-aware Cache Reconfguraton for Embedded Systems Yuanwen Huang and Prabhat Mshra Department of Computer and Informaton Scence and Engneerng Unversty of Florda, Ganesvlle FL , USA {yuanwen, Abstract Cache vulnerablty due to soft errors s one of the relablty concerns n embedded systems. Dynamc reconfguraton technques are wdely studed for mprovng cache energy wthout consderng the mplcatons of cache vulnerablty. Mantanng a useful data longer n the cache can be benefcal for energy mprovement due to reducton n mss rates, however, longer data retenton negatvely mpacts the vulnerablty due to soft errors. Ths paper studes the trade-off between energy effcency mprovement and reducton n cache vulnerablty durng cache reconfguraton. We propose two heurstc approaches for relablty- and energy-aware dynamc cache reconfguraton. Expermental results demonstrate that our proposed approaches can provde drastc reducton n cache vulnerablty wth mnor mpact on energy and performance. I. INTRODUCTION Soft errors are transent faults n CMOS crcuts, whch are caused by energy carryng partcles (cosmc rays or substrate alpha partcles). These transent faults flp bts n storage cells or change the logc values n functonal unts. Soft error rate per chp s expected to grow due to the growng densty of transstors on chp []. Prevous studes have concluded that unprotected memory elements are the most vulnerable components to soft errors [2]. The cache n embedded mcroprocessors s most susceptble to soft errors for several reasons: () cache occupes the majorty of chp area, () cache has an extremely hgh densty of transstors, and () cache cell sze scales down, whch reduces the crtcal charge needed to flp a bn stored data. Due to wdespread use of embedded systems n safety-crtcal devces, s necessary to protect embedded caches from soft errors. Dynamc Cache Reconfguraton (DCR) s a wdely studed method for optmzng energy and performance n embedded systems [3] [4]. The basc dea of cache reconfguraton s that dfferent programs have varyng data and nstructon access characterstcs durng executon (runtme) and DCR tres to fnd the optmal cache confguraton for a gven applcaton (program). For example, we can mprove performance by ncreasng cache sze when a program needs a lot of data accesses. Smlarly, we can save energy by shuttng down a part of the cache f the program s not so data-ntensve. However, cache reconfguraton wll also affect the vulnerablty due to soft errors. A large cache sze for a data-ntensve program mght have fewer cache msses and thus mprove energy and performance effcency, bus also lkely to ncrease the Ths work was partally supported by the NSF grants (CNS and CNS-44667) and SRC grant (24-TS-2554). vulnerablty of cache data because of longer data retenton n the cache. Ths nterestng trade-off between performance, energy and vulnerablty s the motvaton for ths work. Is a major challenge to mprove the relablty of real-tme embedded systems wth specal desgn consderatons of realtme constrans. Hard real-tme systems requre that all tasks must complete executon before ther deadlnes to ensure correct executon. Due to strngent tmng constrants, schedulng for hard real-tme systems must perform task schedulablty analyss based on task attrbutes (such as deadlnes, prortes, and perods). For soft real-tme systems, mnor deadlne msses may resuln temporary servce degradaton, but wll not lead to ncorrect behavor. An effcent cache reconfguraton framework s proposed for energy optmzaton n soft real-tme systems n [4]. They explot the flexblty of soft real-tme systems and manage to acheve consderable energy savngs wth mnor mpacts on user experences. However ther method does not consder the vulnerablty of cache due to soft errors. To the best of our knowledge, there are no pror efforts n analyzng the cache vulnerablty durng cache reconfguraton. We propose a methodology for usng cache reconfguraton n soft real-tme systems. Our approach provdes an effcent cache tunng strategy based on statc proflng and dynamc schedulng of tasks. Our proposed research s able to balance performance, energy consumpton and vulnerablty, so that tasks can meet ther deadlnes and energy savngs whle vulnerablty reducton can also be acheved. The rest of the paper s organzed as follows. Secton II presents related work on DCR and cache vulnerablty. Secton III motvates the reader by llustratng the effect of DCR on performance, energy consumpton and vulnerablty. Secton IV presents our cache reconfguraton methodology. Secton V presents the expermental results. Fnally, Secton VI concludes the paper. II. BACKGROUND AND RELATED WORK Ths secton surveys exstng works n two related domans: cache reconfguraton and cache vulnerablty. A. Cache Reconfguraton Applcatons have vared nstructon and data access patterns, whch means that they requre dfferent cache requrements n terms of cache sze, lne sze, and assocatvty. In nter-task (applcaton-based) cache reconfguraton, DCR tunes the cache when a new task starts ts executon. Fg.

2 llustrates that DCR can mprove overall performance by tunng cache sze for a system wth three tasks. We assume that cache sze s the only tunable parameter of cache for the ease of llustraton (lne sze and assocatvty reman the same). Fg. (a) shows a tradtonal system usng a fxed base cache, whereas n Fg. (b) each task uses ts favorable cache confguraton and the overall executon tme s mproved. these two ntervals, the data needs to be read for reuse, whle a flpped bt can corrupt the data, causng the program to use corrupted cache data. Whle the nterval between the second read and the second wrte s un-vulnerable, the data wll be updated by the wrte operaton even f soft errors corrupt. (a) A tradtonal system (b) A system wth reconfgurable cache Fg. : DCR n a system wth three tasks. DCR has been extensvely studed by prevous works [3] [4] [6]. The underlyng cache archtecture used n our work contans four banks whch can operate as four separate ways. The cache ways can be confgured to shut down so as to vary the cache sze. Smlarly, lne sze can be adjusted by confgurng the fetch unt to dfferent lengths and alter way assocatvty by concatenatng ways. There are many pror efforts n developng energy- and performance-aware cache reconfguraton technques. Wang et al. [3] studed schedulng-aware cache reconfguraton for energy savng n real-tme systems. Ca et al. [7] showed that cache sze could mpact performance, energy and relablty. However, none of the prevous works has consdered cache vulnerablty mprovement durng DCR. B. Cache Vulnerablty In order to facltate relablty analyss of cache, a measurement method s needed for the quantfcaton of cache vulnerablty due to soft errors. Mukherjee et al. [8] ntroduced the concept of Archtectural Vulnerablty Factor (AVF). Vulnerablty analyss dvdes a bt s lfetme nto vulnerable and un-vulnerable ntervals. A bs vulnerable for an nterval, f soft errors that happen n ths nterval wll cause the program to get contamnated data. Smlar to [8] and [], we measure the vulnerablty of cache on a per-byte bass. Actvtes durng the lfetme of a byte ncludes dle, fll, read, wrte and evcton. As shown n Fg. 2, the vulnerable ntervals are marked by two black rectangles: the data s vulnerable between the frst wrte and the second read as well as between the second wrte and the thrd read. Durng Fg. 2: Vulnerable ntervals of a data elemenn cache (where W=Wrte Access, R=Read Access). Byte Cycles s an wdely used term for measurng cache vulnerablty. We measure the vulnerablty of cache as the summaton of vulnerable ntervals of all bytes. It can be defned as follows: Vulnerablty = vulnerable tme of byte all bytes Major relablty mprovement technques nclude error detecton and error preventon [] [9]. Error detecton technques, such as party cachng and error-correctng codes, use spatal redundancy to detect errors. Error preventon technques [], such as perodc flushng and early wrteback, are ntroduced. These hardware technques need extra hardware supporn cache, and are not senstve to the data access pattern of the applcatons. In ths paper, we assume no error preventon, as we am to reduce vulnerablty wth the gven reconfgurable cache archtecture durng DCR. Our goal s to take advantage of the reconfgurable cache and the data access pattern of applcatons to reduce vulnerablty whle stll save energy and meet tmng constrants. III. MOTIVATION: ILLUSTRATIVE EXAMPLE Exstng technques for cache reconfguraton do not consder cache vulnerablty due to soft errors. Fg. 3 llustrates the nterestng behavors of vulnerablty and energy consumpton under dfferent cache confguratons. We run the program pegwt (a benchmark from MedaBench [2]) for 8 tmes, and each run uses a dfferent confguraton for L data cache. Each confguraton conssts of three parameters: cache sze, assocatvty and lne sze. For example, 24B W 64B mples a cache confguraton wth cache sze of 24 bytes, one way wth 64 bytes lne sze. Fg. 3 shows that the energy consumpton, vulnerablty and mss rate change drastcally as we tune cache confguratons. Both energy and vulnerablty relate to cache mss rates and cache confguratons. However, the correlaton behavors are qute dfferent and even conflctng n certan scenaros. In Fg. 3(a), energy consumpton decreases when mss rate decreases (the frst 9 cache confguratons), but keeps ncreasng for the last 9 cache confguratons even though mss rates are farly low. The reason s that total energy consumpton s the sum of dynamc and statc energy. For the frst 9 cache confguratons, the total energy s domnated by dynamc energy consumpton, thus the total energy decreases when

3 mss rate (dynamc energy consumpton) decreases. However, for the last 9 cache confguratons wth large cache sze, the total energy s domnated by statc energy consumpton even though mss rates are low. In Fg. 3(b), the relaton between vulnerablty and mss rate s a lttle more complex. Cache sze has a sgnfcannfluence on vulnerablty. Confguratons wth cache sze of 24B s much less vulnerable than confguratons wth cache sze of 248B and 496B. For confguratons wth the same cache sze, vulnerablty decreases when mss rate ncreases and vce versa. For the same cache sze, lower mss rate means that more drty data s stayng n cache for longer tme, whch contrbutes to vulnerablty. Energy (nj) Vulnerablty (n Byte Cycles) (a) Energy and of pegwt 5 Energy Vulnerablty 2.%.%.% 9.% 8.% 7.% 6.% 5.% 4.% 2.%.%.% 9.% 8.% 7.% 6.% 5.% 4.% (b) Vulnerablty and of pegwt Fg. 3: Energy (a) and vulnerablty (b) values of pegwt benchmark usng dfferent cache confguratons. There are two nterestng observatons here: () small cache sze mght have hgh energy consumpton but less vulnerable; () low mss rate mght be energy frendly but leads to hgher vulnerablty. These observatons motvate us to nvestgate the trade-off between vulnerablty, energy and performance durng DCR. In ths paper, we develop a cache reconfguraton framework that consders both energy and cache vulnerablty. Snce both vulnerablty and energy depend on program characterstcs and cache confguratons, we statcally analyze varous cache confguratons for each applcaton. Such an approach s sutable for embedded systems snce applcatons are known a pror. Based on statc analyss, we propose two heurstc approaches for nter-task dynamc cache tunng that can select sutable confguratons durng runtme. A. System Model IV. DCR FOR ENERGY AND RELIABILITY Let us defne the relablty-aware DCR problem wth consderaton of both energy and cache vulnerablty. The system we consder can be modeled as: A processor wth a reconfgurable cache whch supports m possble cache confguratons C = {c, c 2, c 3,..., c m }. A set of n ndependent tasks T = {t, t 2, t 3,..., t n }. Each task T has attrbutes ncludng arrval tme, perod and deadlne. Non-preemptve executon s employed, whch means, a task wll contnue executon untl completon once t starts to execute. Let e cj, p cj and v cj denote the energy, executon tme (performance) and vulnerablty of task when s run on cache confguraton c j. The relablty-aware DCR problem s to fnd a cache assgnment for the task set such that energy consumpton and vulnerablty are mnmzed wth each of the tasks satsfyng ts deadlne. One common practce for dealng wth mult-objectve optmzaton problem s to optmze one objectve at a tme whle transformng other objectves nto constrants. We ntroduce the Vulnerabltyaware Energy Optmzaton (VAEO) problem, whch ams at mnmzng the total energy consumpton, whle addng vulnerablty of tasks as constrants. A heurstc algorthm based on run-tme task schedulng s proposed for solvng the VAEO problem. We also ntroduce the Energy-aware Vulnerablty Optmzaton (EAVO) problem, whch ams at mnmzng the total vulnerablty whle addng energy consumpton constrants. B. Vulnerablty-aware Energy Optmzaton (VAEO) The VAEO DCR problem can be defned as the followng: n mnmze e cj () subject to = v cj V t, [, n] (2) a t + w t + p cj D t, [, n] (3) Let n represent the total number of task arrvals wthn the least common multple (hyper-perod ) of all task perods. n = ecj s the total energy consumpton of n tasks 2. Equaton 2 and 3 contan the vulnerablty and tmng constrants. V t s the upper bound for vulnerablty of task. Here a t, w t, p cj, D t denote the arrval tme, queung tme, executon tme, and deadlne of task. The optmzaton goal s to fnd a set of cache confguraton assgnments for all tasks so that A hyper-perod s the Least Common Multple (LCM) of all the perods n the task set. The basc dea of usng hyper-perod s that once we fnd a proftable (for energy or vulnerablty) schedule for one hyper-perod, the exactly same schedule can be appled to subsequent hyper-perods. 2 It wll be precse to call n as the total number of jobs as n real-tme system termnology. However, for ease of dscusson, we do not dstngush between tasks and jobs.

4 the total energy consumpton s mnmzed wth vulnerablty and tmng constrants. We choose V t as the vulnerablty of task when s executed wth the base cache, the most proftable cache confguraton decded durng desgn tme. In other words, we set the vulnerablty as a constrant to ensure thas always at least as relable as the base cache. In Equaton 3, arrval tme a t and deadlne D t are known upon the arrval of the task, whle queung tme w t and executon tme p cj depend on the schedulng and cache reconfguraton algorthms. Queung tme w t depends on the scheduler and s determned by the prorty of ths task and the other tasks currently n the queue. Executon tme p cj s determned by the cache confguraton c j whch wll be assgned to ths task by the cache reconfguraton algorthm. C. Heurstc Approach for VAEO Problem Tasks arrve perodcally and each task s nserted nto a lst of ready tasks upon arrval. We propose a heurstc approach, whch employs Earlest Deadlne Frst (EDF) as our underlyng schedulng algorthm. EDF fetches the task wth the hghest prorty (earlest deadlne) to execute. The cache confguraton selecton algorthm wll pck a confguraton for ths task and try to satsfy Equaton 2 and 3 f possble. Our heurstc approach chooses between the VAEO cache confguraton and performance optmal (PO) cache confguraton for ths task. VAEO cache confguraton of a task s the confguraton whch satsfes Equaton 2 and consumes the least energy (.e. the VAEO confguraton) among all possble confguratons. PO cache confguraton of a task s the confguraton whch has the shortest executon tme (.e. the PO confguraton), but PO confguraton mght not satsfy Equaton 2. The ntuton behnd our approach of choosng between PO and VAEO confguraton are as follows: () The VAEO confguraton satsfes the vulnerablty constrann Equaton 2 and s most benefcal for energy savngs, although t mght have long executon tme. We would lke to always choose the VAEO confguraton for energy optmzaton, as long as ths choce would not cause the task tself or any of the subsequent tasks to volate ther deadlnes. (2) The PO confguraton s amed on Equaton 3 for satsfyng tmng constrants. If the VAEO confguraton of a task causes deadlne volatons, we would conservatvely choose the PO confguraton nstead. Wth ths task runnng under the PO confguraton, the subsequent tasks wll have more slack tme for schedulng and possbly save energy. Algorthm llustrates the runtme cache selecton algorthm for VAEO approach. Let us assume that our system uses non-preemptve EDF schedulng for the task set. Tasks arrve perodcally and currently avalable tasks wll be put nto the lst of ready tasks (LRT), whch s mantaned as a prorty queue based on the deadlnes of tasks. Algorthm s called when the processor s ready to execute a new task. The term p P t O stands for the executon tme of task usng ts Algorthm Cache Confguraton Selecton for VAEO Input: Lst of ready tasks (LRT) and task profle table. Output: VAEO or PO cache confguraton. Step : Sort all tasks n LRT by prorty and fetch the task t c wth hghest prorty. Step 2: t to t m are tasks lefn LRT, from hghest to lowest prorty. τ represents the current tme. //***check the schedulablty of each task n LRT***// for j = to m do do f τ + p P O t c + j Dscard task t j end f end for = pp O > D tj then Step 3: Select cache confguraton for current task t c. Let m be the number of tasks n LRT left after Step 2. //***test the feasblty of usng VAEO confg for t c ***// f τ + p V t AEO c > D tc then OK V AEO =false; else OK V AEO =true; for j = to m do f τ + p V t AEO c + j = pp t O > D tj then OK V AEO =false; end f end for end f f OK V AEO ==true then return VAEO confguraton for task t c else return PO confguraton for task t c end f PO confguraton, and p V t AEO usng ts VAEO confguraton. stands for the executon tme Step fetches the current task t c to be executed, whch s the hghest prorty task from LRT. Step 2 checks the schedulablty of the tasks lefn LRT, when the current task t c s executed wth PO cache confguraton. The schedulablty of each task t j lefn the LRT s checked by τ +p P t O c + j = pp t O > D tj, whch tests whether ts deadlne can be met wth the assumpton that all precedng tasks (and tself) use PO cache confguratons. If t j cannot satsfy ts deadlne even wth ths conservatve assumpton, t j should be dscarded. The dscardng process s done from hghest prorty to lowest prorty, so as to acheve fewest dscarded tasks. Ths step ensures that all tasks n LRT wll satsfy ther deadlnes wth ther PO confguratons, when the current task t c s executed wth ts PO confguraton. Ths step wll be skpped f LRT s empty. In Step 3, we try to test the feasblty of usng ts VAEO confguraton for the current task t c, whch wll help mprove vulnerablty and energy consumpton. The approprate cache confguraton for the current task t c s selected by checkng whether s safe to use ts VAEO confguraton. VAEO confguraton s safe, only

5 f no tasks n the LRT wll fal to meet ther deadlnes wth ther PO confguratons. If the VAEO confguraton s not safe for t c, we wll conservatvely execute the current task t c wth ts PO confguraton, whch can ensure all tasks lefn the LRT to satsfy ther deadlnes wth ther PO confguratons (otherwse they would have already been dscarded n Step 2). Ths algorthm runs n tme of O(m) where m s the total number of tasks n LRT. D. Energy-aware Vulnerablty Optmzaton (EAVO) Now we are ready to develop a smlar heurstc approach to solve the EAVO problem, whch has the total vulnerablty of task set as the optmzaton objectve and energy consumpton of tasks as constrants. The EAVO DCR problem can be defned as the followng: n mnmze v cj (4) n = vcj subject to = e cj E t, [, n] (5) a t + w t + p cj D t, [, n] (6) s the total vulnerablty of n tasks. Equaton 5 contans the energy constrants and E t s the upper bound for energy consumpton of task. Equaton 6 contans the tmng constrants, whch s the same as Equaton 3. The optmzaton objectve s to fnd a set of cache confguraton assgnments for all tasks so that the total vulnerablty s mnmzed wthout volatng energy and tmng constrants. We choose E t as the energy consumpton of task when t s executed wth the base cache. In other words, we am to mnmze vulnerablty of task set whle ensurng that tasks can meet ther deadlnes and consume no more energy than the base cache. Smlar to VAEO, our EAVO approach wll choose between the EAVO confguraton and PO confguraton. The cache confguraton selecton algorthm of our EAVO approach s smlar to Algorthm except that all VAEO phrases n Algorthm need to be replaced wth the phrase EAVO. Due to space constrants, we wll not duplcate the algorthm for our EAVO approach. A. Expermental Setup V. EXPERIMENTS The confgurable caches used n our work are from the cache archtecture ntroduced n [4]. The underlyng cache archtecture contans a confgurable cache wth a four-bank cache wth szes of KB, 2 KB and 4 KB, lne szes of 6 bytes, 32 bytes and 64 bytes, and assocatvty of -way, 2-way and 4-way. In order to quantfy relablty-aware DCR trade-off, we selected benchmarks from MedaBench [2] and EEMBC Automotve [3] benchmark sutes. Table shows our four task sets wth three selected benchmarks n each set. All of the tasks are executed wth the defaulnput parameters provded wth the benchmark sutes. The Base Cache 3 s chosen as a 4KB, 2-way set-assocatve cache wth lne sze of 32 bytes and ths base confguraton meets the need of tested benchmarks. Task Task 2 Task 3 Task Set epc* pegwt* cjpeg* Task Set 2 toast* mpeg2* djkstra* Task Set 3 AIFFTR** AIFIRF** A2TIME** Task Set 4 RSPEED** BITMNP** IDCTRN** TABLE I: Task set benchmarks from *MedaBench [2] and **EEMBC [3] We modfed the SmpleScalar smulator [4] for cache vulnerablty analyss and energy consumpton estmaton. We performed the vulnerablty analyss durng cache accesses for each byte n nstructon and data cache. The vulnerablty estmaton functon collects all the vulnerable ntervals for each vald byte n cache. We appled the same energy model as n [4] to calculate both dynamc and statc energy consumpton, and the energy consumpton was estmated usng CACTI 4.2 [5] wth a.8 µm technology. For statc proflng of each task to fnd the PO, VAEO, and EAVO cache confguratons, we developed Perl scrpts to exhaustvely search the desgn space of all possble cache confguratons. Snce we only consder systems wth one level of reconfgurable cache archtecture, the space of possble cache confguratons s small. The statstcs for all possble cache confguratons for a task can be collected n a reasonable tme (a few hours). Once we have the profle tables for all the tasks, we use an EDF scheduler to smulate the system for a hyper-perod. The cache selecton algorthms are ntegrated n the scheduler to make decsons to reconfgure the cache durng smulaton. The optmzaton for nstructon cache and data cache are ndependent. B. Results and Analyss Usng the methodology descrbed n Secton IV, we apply our VAEO and EAVO approaches on each task set. Fg. 4 and Fg. 5 show results for nstructon cache and data cache, respectvely. VAEO approach can mprove both energy and vulnerablty whle EAVO approach can sgnfcantly reduce vulnerablty wth mnor mpact on energy consumpton. There are a few nterestng observatons on our results: () As expected, VAEO approach always consumes less energy, but has hgher vulnerablty than EAVO approach. Ths s algned wth our optmzaton goals: VAEO s for energy optmzaton and EAVO s for vulnerablty optmzaton. (2) VAEO approach mproves vulnerablty as well as energy consumpton. As we mentoned earler, the Base Cache s selected as 496B 2W 32B because ths confguraton wll ensure all tasks to meet ther deadlnes. A large cache sze of 496B can have hgh performance but also cause hgh vulnerablty. So Base Cache s among the cache confguratons wth 3 Base Cache refers to the cache used n typcal real-tme systems, whch s chosen to ensure durable task schedules. Typcally, base cache s the globally optmal cache confguraton determned durng desgn tme for a set of tasks.

6 Energy Normalzed to Base Cache (a) Energy Consumpton of Instructon Cache Energy Normalzed to Base Cache (a) Energy Consumpton of Data Cache Vulnerablty Normalzed to Base Cache (b) Vulnerablty of Instructon Cache Vulnerablty Normalzed to Base Cache (b) Vulnerablty of Data Cache Fg. 4: Instructon cache energy and vulnerablty. VAEO can mprove both energy (9.6%) and vulnerablty (5.8%). EAVO can sgnfcantly reduce vulnerablty (2.9%) wth mnor mpact on energy consumpton (9.7%). hgh vulnerablty and leaves plenty of room for vulnerablty reducton. (3) But EAVO approach may ncrease the energy consumpton. As shown n Secton III, small cache sze and large mss rate tend to have low vulnerablty, whle t usually comes wth a cost of nferor performance and hgh energy consumpton. Moreover, when a task uses ts EAVO cache confguraton has extremely bad performance, t may force the subsequent tasks to choose PO cache confguratons n order to meet ther deadlnes and consume a lot more energy for these tasks. (4) For data cache optmzaton of Task Set, EAVO approach gans nether energy nor vulnerablty mprovement. Thas because EAVO cache confguratons for some tasks have extremely bad performance, whch forces too many subsequent tasks to choose PO cache confguratons and ncrease the vulnerablty for the task set. VI. CONCLUSIONS Dynamc cache reconfguraton s wdely used for mprovng energy and performance n embedded systems. Whle cache vulnerablty s a well studed area, prevous research efforts dd not explore cache vulnerablty n the context of cache reconfguraton. In ths paper, we developed algorthms to reduce cache vulnerablty due to soft errors wth energy and performance consderatons. Our expermental results Fg. 5: Data cache energy and vulnerablty. VAEO can mprove both energy (8%) and vulnerablty (23%). EAVO can sgnfcantly reduce vulnerablty (25.4%) wth mnor mpact on energy consumpton (5.9%) demonstrated that our approach can sgnfcantly mprove the relablty of both nstructon and data caches. REFERENCES [] V. Srdharan and D. Lberty. A Study of DRAM Falures n the Feld. HPCNSA(SC), 22. [2] R. Jeyapaul and A. Shrvastava. Smart Cache Cleanng: Energy effcent vulnerablty reducton n embedded processors. CASES, 2. [3] W. Wang et al. Dynamc Cache Reconfguraton for Soft Real-Tme Systems. TECS, 22. [4] W. Wang et al. Dynamc Reconfguraton n Real-Tme Systems - Energy, Performance, Relablty and Thermal Perspectves. Sprnger, 22. [5] C. Ekeln. Clarvoyant Non-Preemptve EDF Schedulng. ECRTS, 26. [6] P. Hsu and T. Hwang. Thread-crtcalty aware dynamc cache reconfguraton n mult-core system, ICCAD, 23. [7] Y. Ca et al. Cache sze selecton for performance, energy and relablty of tme-constraned systems. ASP-DAC, 26. [8] S. Mukherjee et al. A systematc methodology to compute the archtectural vulnerablty factors for a hgh-performance mcroprocessor. MICRO, 23. [9] V. Srdharan et al. Reducng data cache susceptblty to soft errors. TDSC, 26. [] G. H. Asad et al. Balancng performance and relablty n the memory herarchy. ISPASS, 25. [] A. Bswas et al. Computng archtectural vulnerablty factors for address-based structures. ISCA, 25. [2] C. Lee et al. Medabench: A tool for evaluatng and syntheszng multmeda and communcatons systems. MICRO, 997. [3] EEMBC, The Embedded Mcroprocessor Benchmark Consortum. [4] The SmpleScalar Smulator. [5] CACTI.