IKR EmuLib. A Library for Seamless Integration of Simulation and Emulation. Marc Necker, Christoph Gauger [necker

Transcription

1 Universität Stuttgart INSTITUT FÜR NACHRICHTENVERMITTLUNG UND DATENVERARBEITUNG Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn INSTITUT FÜR KOMMUNIKATIONSNETZE UND RECHNERSYSTEME Prof. Dr.-Ing. Dr. h. c. mult. P. J. Kühn IKR EmuLib A Library for Seamless Integration of Simulation and Emulation Marc Necker, Christoph Gauger [necker gauger]@ikr.uni-stuttgart.de ITG FG Workshop Simulationstechnik Mittweida, November 3, 2005 Outline: Introduction of IKR SimLib Motivation of emulation approach Realization of IKR EmuLib Evaluation of accuracy

2 IKR SimLib History - origin: Pascal simulation library (1980ies) - object-oriented redesign in the context of a dissertation (1992) - since then continuously enhanced and improved Implementation - C++ class library - usage of additional libraries (e.g., container class library) - tested under various platforms: Linux, Solaris, CygWin Main Features - support for transformation of an abstract model into source code - control of event-driven simulation - random number generation (various distributions and source models) - statistical evaluation - reading parameter values and printing results

3 Basic Structure user standard components model components utilities modelling concepts basic entity port concept filters & meters basic concepts simulation control event handling random distributions statistical evaluation I/O concept

4 Model Components: Object Hierarchy model node1 node2 Decomposition support by Hierarchy generator queue server queue server sink - has-relationship - pointer to owner Name Concept - local name as attribute TMyModel - identification of components - access via central component manager TGenerator TMyNode TSink TMyQueue TMyServer

5 Port Concept Simulation Model Traffic Generator Network Model Traffic Sink simulation messages simulation messages Message exchange between model components via ports distinction between input and output ports central port registration using owner address and port name connection of the ports using function call Connect communication via handshake protocol uniform interface for communication between model components

6 Simulation vs. Emulation vs. Prototype Simulation fast and easy exploration of vast parameter space difficulty to model complex componentes & protocols

7 Simulation vs. Emulation vs. Prototype Simulation fast and easy exploration of vast parameter space difficulty to model complex componentes & protocols Emulation easy integration of real world components unsuitable to explore large parameter space

8 Simulation vs. Emulation vs. Prototype Simulation fast and easy exploration of vast parameter space difficulty to model complex componentes & protocols Emulation easy integration of real world components unsuitable to explore large parameter space Prototype trustworthy results difficult setup, limited parameter space

9 Integrated Simulation and Emulation Combined Simulation and Emulation simulative exploration of vast parameter space with approximate models emulative evaluation of selected parameter points with included real-world components Design Objectives Create emulation extension for existing simulation library Enable the reuse of existing simulation models Switch between simulation and emulation in zero time Seamless integration

10 Basic Idea Implement emulation as an IP packet router Delay or drop IP packets according to model behavior Interfaces to model are traffic generators and traffic sinks Simulation Model Traffic Generator Network Model Traffic Sink simulation messages simulation messages

11 Basic Idea Implement emulation as an IP packet router Delay or drop IP packets according to model behavior Interfaces to model are traffic generators and traffic sinks Simulation Model Traffic Generator Network Model Traffic Sink simulation messages simulation messages Emulation Model Network Interface IP Packet Filter Traffic Generator Network Model Traffic Sink IP Packet Routing Network Interface IP packets emulation messages emulation messages IP packets

12 Realization I Interface to network realized by multithreaded-design Listener Thread - reception of IP packets, filtering, time stamping, buffering Model Thread - encapsulation into simulation messages, model processing, transmission to network interface Listener Thread Model Thread simulation model packet filter event processing loop Generators Sinks calendar

13 Realization II Interaction between threads packet arrival Listener Thread Model Thread assign timestamp t 0 append packet to buffer real time real time

14 Realization II Interaction between threads packet arrival Listener Thread Model Thread assign timestamp t 0 append packet to buffer control transfer check buffer: read packet post packet event to time t 0 process next event model execution real time real time

15 Realization II Interaction between threads packet arrival Listener Thread Model Thread assign timestamp t 0 append packet to buffer packet arrival assign timestamp t 1 control transfer control transfer check buffer: read packet post packet event to time t 0 process next event model execution real time real time

16 Realization II Interaction between threads Listener Thread packet arrival assign timestamp t Inaccuracy 0 Model Thread append packet to buffer packet arrival assign timestamp t 1 control transfer control transfer check buffer: read packet post packet event to time t 0 process next event model execution real time real time

17 Realization II Interaction between threads packet arrival assign timestamp t 0 append packet to buffer packet arrival assign timestamp t 1 Listener Thread Model Thread Inaccuracy Classification of inaccuracies control transfer check buffer: read packet Inaccuracies due to asynchronous post packet event to time t packet arrivals 0 Operating system process imposed next inaccuracies event Model imposed inaccuracies model execution Careful examination of emulation error control transfer real time real time

18 Measurement Setup Emulation Model IP packet filter Traffic Gen. Traffic Sink IP packet router packet rate r packet length L D service time T D Hub Agilent Internet Advisor Constant rate UDP source Infinite server model with constant service time T D = 10ms External measurement of delay error (Agilent Internet Advisor) Internal measurement of delay error (emulation self-determined error)

19 Infinite Server Accuracy 10 0 measured error emulation self-determined error ccdf delay error [ms] Excellent correlation between measured and self-determined error Only 0.1% of all packets have an error of more than 0.2 ms

20 HSDPA Scenario Node B UTRAN Core Network RNC SGSN GGSN Internet Server Detailed UTRAN model Fixed Delay and Drop Probability T INet Detailled model of High Speed Downlink Packet Access (HSDPA) one emulated UDP traffic flow in downlink direction one simulated cross-traffic flow with TCP bulk data transfer in downlink direction

21 HSDPA Accuracy Absolute Error packets/s 200 packets/s 400 packets/s ccdf absolute delay error [ms] Only 1% of all packets have an error of more than 2-4 ms Higher absolute error due to model imposed inaccuracies Evaluate relative error

22 HSDPA Accuracy Relative Error packets/s 200 packets/s 400 packets/s ccdf relative delay error Very good relative error in low medium load situations Only 0.1% of all packets have a relative error of more than 5%

23 Conclusion IKREmuLib: Integrated simulation and emulation environment Flexible usage through powerful filtering and routing possibilities Quick transition between simulation and emulation domain Efficiently combine simulated with emulated flows and components Good accuracy for models with delay on the order of tens of ms Outlook Explore possibility for protocol interfaces Evaluate different strategies to enhance accuracy