Intel Quark SoC X1000 Platform MRC Swapping Code Example

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1 Intel Quark SoC X1000 Platform MRC Swapping Code Example Document Number:

2 Legal Disclaimer Legal Disclaimer By using this document, in addition to any agreements you have with Intel, you accept the terms set forth below. You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject matter disclosed herein. INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined. Do not finalize a design with this information. The products described in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling , or go to: Basis, BlueMoon, BunnyPeople, Celeron, Centrino, Cilk, Flexpipe, Intel, the Intel logo, the Intel Anti-Theft technology logo, Intel AppUp, the Intel AppUp logo, Intel Atom, Intel CoFluent, Intel Core, Intel Inside, the Intel Inside logo, Intel Insider, Intel NetMerge, Intel NetStructure, Intel RealSense, Intel SingleDriver, Intel SpeedStep, Intel vpro, Intel Xeon Phi, Intel XScale, InTru, the InTru logo, the InTru Inside logo, InTru soundmark, Iris, Itanium, Kno, Look Inside., the Look Inside. logo, Mashery, MCS, MMX, Pentium, picoarray, Picochip, picoxcell, Puma, Quark, SMARTi, smartsignaling, Sound Mark, Stay With It, the Engineering Stay With It logo, The Creators Project, The Journey Inside, Thunderbolt, the Thunderbolt logo, Transcede, Transrf, Ultrabook, VTune, Xeon, X-GOLD, XMM, X-PMU and XPOSYS are trademarks of Intel Corporation in the U.S. and/or other countries *Other names and brands may be claimed as the property of others. Copyright 2014, Intel Corporation. All rights reserved. 2 Document Number:

3 Contents Contents 1 Introduction Introduction Reference Documents DDR3 Memory Down Bit Swapping Design Rules for Allowable Bit Swapping Example Memory Pin to Pin Connection on Board Design Memory Reference Code Consideration Tables Table 1. Reference Documents... 5 Table 2. Dual Rank Memory Pin Connection for Rank Document Number:

4 Revision History Revision History Date Revision Description 001 Initial release. 4 Document Number:

5 Introduction 1 Introduction 1.1 Introduction This document covers the guidelines on MRC code location in BIOS need to change when bit swapping is used on Intel Quark SoC X1000 memory design. Chapter 2 will shows an example of DDR3 memory bit swapping design and the MRC implementation. 1.2 Reference Documents Table 1. Reference Documents Document Intel Quark SoC X1000 Platform- DDR3 Dual Rank Memory Down Schematic Guide Technical Intel Quark SoC X1000 Platform- DDR3 Dual Rank Memory Down Broad Layout Guide Technical Document No./Location Intel Quark SoC X1000 UEFI Firmware Write Guide Document Number:

6 2 DDR3 Memory Down Bit Swapping Design 2.1 Rules for Allowable Bit Swapping To accommodate the change from the software perspective the UEFI MRC module must be made aware of the mapping of the address and bank bits and remap these appropriately for Jedec configuration and MRC commands on a per rank basis. There are no hardware barriers to achieve this. As a general swapping is allowed on: - DQ[7:0] between ranks and within devices of the same rank - within the byte boundaries i.e. the corresponding strobe - DQS must be always controlling its designated DQ bits within each rank. - BA[2:0] between ranks, BUT NOT between the devices of the same rank. - ADDR[9:3] between ranks, BUT NOT between the devices of the same rank. Section 2.2 is the example of memory pin to pin connection on board which memory swapping has been made. 2.2 Example Memory Pin to Pin Connection on Board Design Table 2. Dual Rank Memory Pin Connection for Rank 1 DDR3 SDRAM Signal from SOC RANK 1 (DQ 8-15) (DQ 0-7) Pin Pinout Description Pin Netname Pin Netname A1 GND A1 GND A1 GND A2 VDD A2 V1P5_S3 A2 V1P5_S3 A3 NC A3 A3 A7 NF A7 A7 A8 GND A8 GND A8 GND 6 Document Number:

7 A9 VDD A9 V1P5_S3 A9 V1P5_S3 B1 GND B1 GND B1 GND B2 GND B2 GND B2 GND B3 DQ<0> B3 M_DQ<10> B3 M_DQ<6> B7 DM/TDQS B7 DDR3_DM1 B7 DDR3_DM0 B8 GND B8 GND B8 GND B9 VDD B9 V1P5_S3 B9 V1P5_S3 C1 VDD C1 V1P5_S3 C1 V1P5_S3 C2 DQ<2> C2 M_DQ<11> C2 M_DQ<7> C3 DQS<0> C3 M_DQS<1> C3 M_DQS<0> C7 DQ<1> C7 M_DQ<12> C7 M_DQ<5> C8 DQ<3> C8 M_DQ<9> C8 M_DQ<4> C9 GND C9 GND C9 GND D1 GND D1 GND D1 GND D2 DQ<6> D2 M_DQ<14> D2 M_DQ<3> D3 DQS_N<0> D3 M_DQS_N<1> D3 M_DQS_N< 0> D7 VDD D7 V1P5_S3 D7 V1P5_S3 D8 GND D8 GND D8 GND D9 GND D9 GND D9 GND E1 VREFDQ E1 VREF E1 VREF E2 VDD E2 V1P5_S3 E2 V1P5_S3 E3 DQ<4> E3 M_DQ<15> E3 M_DQ<2> E7 DQ<7> E7 M_DQ<13> E7 M_DQ<1> E8 DQ<5> E8 M_DQ<8> E8 M_DQ<0> E9 VDD E9 V1P5_S3 E9 V1P5_S3 F1 NC F1 F1 F2 GND F2 GND F2 GND Document Number:

8 F3 RAS_N F3 M_RAS_N F3 M_RAS_N F7 CK<0> F7 M_CK<0> F7 M_CK<0> F8 GND F8 GND F8 GND F9 NC F9 F9 G1 ODT<0> G1 M_ODT<0> G1 M_ODT<0> G2 VDD G2 V1P5_S3 G2 V1P5_S3 G3 CAS_N G3 M_CAS_N G3 M_CAS_N G7 CK_N<0> G7 M_CK_N<0> G7 M_CK_N<0 > G8 VDD G8 V1P5_S3 G8 V1P5_S3 G9 CKE<0> G9 M_CKE<0> G9 M_CKE<0> H1 NC H1 H1 H2 CS_N<0> H2 M_CS_N<0> H2 M_CS_N<0> H3 WE_N H3 M_WE_N H3 M_WE_N H7 A<10> H7 M_MA<10> H7 M_MA<10> H8 ZQ H8 Pull to GND with 240ohm,1% H8 Pull to GND with 240ohm,1% H9 NC H9 H9 J1 GND J1 GND J1 GND J2 BS<0> J2 M_BS<1> J2 M_BS<1> J3 BS<2> J3 M_BS<2> J3 M_BS<2> J7 A<15> J7 M_MA<15> J7 M_MA<15> J8 VREFCA J8 VREF J8 VREF J9 GND J9 GND J9 GND K1 VDD K1 V1P5_S3 K1 V1P5_S3 K2 A<3> K2 M_MA<4> K2 M_MA<4> K3 A<0> K3 M_MA<0> K3 M_MA<0> K7 A<12> K7 M_MA<12> K7 M_MA<12> 8 Document Number:

9 K8 BS<1> K8 M_BS<0> K8 M_BS<0> K9 VDD K9 V1P5_S3 K9 V1P5_S3 L1 GND L1 GND L1 GND L2 A<5> L2 M_MA<6> L2 M_MA<6> L3 A<2> L3 M_MA<2> L3 M_MA<2> L7 A<1> L7 M_MA<1> L7 M_MA<1> L8 A<4> L8 M_MA<3> L8 M_MA<3> L9 GND L9 GND L9 GND M1 V1P5_S3 M1 V1P5_S3 M1 V1P5_S3 M2 A<7> M2 M_MA<8> M2 M_MA<8> M3 A<9> M3 M_MA<9> M3 M_MA<9> M7 A<11> M7 M_MA<11> M7 M_MA<11> M8 A<6> M8 M_MA<5> M8 M_MA<5> M9 VDD M9 V1P5_S3 M9 V1P5_S3 N1 GND N1 GND N1 GND N2 RST_N N2 M_DRAMRST_N N2 M_DRAMRST _N N3 A<13> N3 M_MA<13> N3 M_MA<13> N7 A<14> N7 M_MA<14> N7 M_MA<14> N8 A<8> N8 M_MA<7> N8 M_MA<7> N9 GND N9 GND N9 GND Note: Yellow highlighted signals are the signals that bit swapping have been made. Rank 0 is based on 1:1 mapping. No bit swapping on Rank 0. Document Number:

10 2.3 Memory Reference Code Consideration Memory Reference Code (MRC) is the DRAM/Memory-Controller initialization flow performed by Firmware before DRAM is enabled for functional access. While bit swapping design is allowed and shall work on Intel Quark SoC X1000, it requires an update MRC to accommodate the changes made to the swapped pin. The update shall reflect the bit swapping in hardware accordingly so that MRC as the memory initialization software does not misinterpret the Bank Select (DDR3_BS) and Memory Address (DDR3_MA). Any bit swapping made on the Data Lines (DDR3_DQ) does not require modification in MRC as the remapping made happens during both write and read operations, hence is being cancelled out automatically. MRC module for Intel Quark SoC X1000 can be found in the EDKII of the Intel Quark Board Support Package. Using the bit swapping example in Section 2.1, modification made to a function dram_init_command in the Quark_EDKII_vX.X.X/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/meminit.c will be sufficient. The following example is a snapshot of the modified function to reflect the bit swapping made in Table 2. Dual Rank Memory Pin Connection for Rank 1. // Send DRAM command, data should be formatted // using DCMD_Xxxx macro or emrsxcommand structure. static void dram_init_command( { uint32_t data) uint32_t BankAddress; uint32_t temp; // // For Rank 1 only // if (data & BIT22) { // BA -> BA bit to bit mapping for rank 1 // 0 1 // 1 0 // 2 2 BankAddress = (data >> 3) & 0x07; temp = data; 10 Document Number:

11 data &= 0xFFFFFFE7; data = ((temp >> 1) & 0x08); data = ((temp << 1) & 0x10); // ADDR -> ADDR bit mapping for rank 1 // 3 4 // 4 3 // 5 6 // 6 5 // 7 8 // 8 7 data &= 0xFFFF81FF; data = ((temp >> 1) & 0x02A00); data = ((temp << 1) & 0x05400); } } Wr32(DCMD, 0, data); Note: A different mapping algorithm needs to be applied into the code example shown above if a different bit swapping design is used. Once the modification is made to the dram_init_command in meminit.c, make sure the file is saved properly before performing a full rebuild on EDKII. Document Number: