More on Address Translation. CS170 Fall T. Yang Some of slides from UCB CS162 by Kubiatowicz

Transcription

1 More on Address Translation CS170 Fall T. Yang Some of slides from UCB CS162 by Kubiatowicz

2 Topics Review of last lecture on pagetable based address translation One-level page table Muti-level paging Page sharing among processes Other page table implementation

3 Summary on Memory Management and Translation Memory is a resource that must be multiplexed Controlled overlap: only shared when appropriate Translation: Change virtual addresses into physical addresses Protection: Prevent unauthorized sharing of resources Simple protection through segmentation Base + Limit registers restrict memory accessible to user Can be used to translate as well Page tables Memory divided into fixed-sized chunks of memory Offset of virtual address same as physical address Page sharing among processes is easy 1-level vs multi-level page table TLB Essential for speeding up address translation

4 Maximum virtual space size for 1 or multi-level page-table based address translation Vitual space size =# of tree leaves * page size 1-level page table 2-level page table Memory pages #of leaves = #page table entries per page 3-level page table Level 1 4-level page table Level 2

5 2-level Page Table for Address Translation 2-level page table: Divide virtual addr to 3 parts offset Memory pages Vitual space size =# of tree leaves * page size Level 1 Level 2

6 Virtual Address: Flow of the two-level page table 10 bits 10 bits 12 bits Virtual Virtual P1 index P2 index Offset Physical Address: Physical Page # Offset 4KB PageTablePtr 4 bytes Tree of Page Tables Each table has a fixed size (1024 entries) fitting into one physical frame 4 bytes

7 Example of Page Table Entry (PTE): Intel x86 architecture Address format (10, 10, 12-bit offset) Intermediate page tables called Directories Page Frame Number (Physical Page Number) Free (OS) L D A PWT PCD U W P P: Present (same as valid bit in other architectures) W: Writeable U: User accessible PCD: Page cache disabled (page cannot be cached) A: Accessed: page has been accessed recently D: Dirty (PTE only): page has been modified recently Physical space size 2 # bits in Pyage FrameNumber page size 2 32 page size

8 2-level Page table entry Page Frame Number (Physical Page Number) 0 L D A PWT PCD 4 3 U WP Bits of d = log (page size) Bits of p 1 >= log (# entries in level-1 table) Bits of p 2 = log (# entries in level-2 table) Virtual space size = # entry in level-1 table * # entry in level 2 table * page size Level 1 Level 2 Physical page

9 Analysis of a Two-Level Paging Example A virtual address (on 32-bit machine with 4K page size) is divided into: a page number area with 20 bits a page offset consisting of 12 bits Each page table entry uses 4 bytes. 20 bits for physical page number How to build a two-level paging scheme? How many entries can a memory page hold? What are p 1, p 2? page number page offset p i p 2 d?? 12

10 Analysis of a Two-Level Paging Example A memory page with 4KB holds 1K entries and each uses 4B. 1K entries require 10 bits for P 1 and P 2 offset Bits of p 1 >= log (# entries in level-1 table) Bits of p 2 = log (# entries in level-2 table) The page number is further divided into: a 10-bit level-1 index a 10-bit level-2 index page number page offset p i p 2 d

11 Example of maximum virtual/physcal space size Maximum virtual space size =#leaves * page size # entry in level-1 page table * # entry in level-2 page table * page size = 1K * 1K * 4KB = 2 32 bytes = 4GB Max. Physical space =2 20 *4K=4GB page number page offset p i p 2 d K 4K 4K What if we use 2 bytes for each table entry? Increased virtual space size? Increased physical space size? 1K 1K 1K

12 What if we use 2 bytes for each table entry? Maximum logical space size # entry in level-1 page table * # entry in level-2 page table * page size = 0.5K * 2K * 4KB = 2 32 bytes = 4GB page number page offset p i p 2 d Physical space 2 16 *4K=256MB What if we use 2 bytes for each table entry? Increased virtual space size? Same Increased physical space size? Decrease 0.5K 2K 2K 2K 4K 4K

13 Three-level Paging in Linux Address is divided into 4 parts

14 Address translation with 3-level paging Virtual Address is decomposed as 4 parts p 3 d p 1, p 2, p 3, d Use p 1 to access an entry at level 1 table. Content is location of level 2 table Use p 2 to access level 2 table. Entry content is location of level 2 table Use p 3 to access level 3 table. Entry content is physical page number p 3 Level 1 Level 2 Level 3 Physical page

15 Design consideration for 3-level paging Bits of d? log (page size) Bits of p 1? log (# entries in level-1 table) Bits of p 2? log (# entries in level-2 table) Bits of p 3? log (# entries in level-3 table) Virtual space size? # entry in level-1 table * # entry in level 2 table * *page size p 3 d Level 1 Level 2 p 3 Level 3 Physical page

16 Design consideration for 3-level paging Bits of d = log (page size) Bits of p 1 >= log (# entries in level-1 table) Bits of p 2 = log (# entries in level-2 table) Bits of p 3 = log (# entries in level-3 table) Virtual space size = # entry in level-1 table * # entry in level 2 table * #entry in level-3 table *page size p 3 d Level 1 Level 2 p 3 Level 3 Physical page

17 An example of two-level paging in a 64-bit address space With a 32-bit page table entry and 4KB per age, what is the maximum virtual space that can be mapped? Level 1 Level 2 Physical page

18 An example of two-level paging in a 64-bit address space With a 32-bit page table entry and 4KB per age, maximum virtual space = 2 10 *2 10 *4K=4GB Level 1 Level 2 Physical page

19 An example of three-level paging in a 64-bit address space With a 32-bit page table entry and 4KB per age, how to split a virtual address?

20 An example of three-level paging in a 64-bit address space Page size=4kb Page table entry=4 bytes With a 32-bit page table entry, what is the maximum virtual and physical space size?

21 An example of three-level paging in a 64-bit address space Page size=4kb Page table entry=4 bytes #Entries/page=1K With a 32-bit page table entry and 4K bytes per page, 1K PTEs per page. Maximum virtual space = 1K*1K*1K*4K. Physical space size 2 32 *4K

22 Other Topics on Memory Management Page sharing among process What can page table entries be utilized? Other address translation implementation Hashed page tables Inverted page tables

23 Shared Pages through Paging Shared code One copy of read-only code shared among processes (i.e., text editors, compilers, window systems). Shared code must appear in same location in the logical address space of all processes Private code and data Each process keeps a separate copy of the code and data The pages for the private code and data can appear anywhere in the logical address space

24 Shared Pages Example

25 Example Virtual Address (Process A): Virtual Page # Offset PageTablePtrA page #0 page #1 page #2 page #3 page #4 page #5 PageTablePtrB page #0 page #1 page #2 page #3 page #4 page #5 V,R V,R N V,R N N V,R Shared Page This physical page appears in address space of both processes Virtual Address (Process B): Virtual Page # Offset

26 Optimization of Unix System Call Fork() A child process copies address space of parent. Most of time it is wasted as the child performs exec(). Can we avoid doing copying on a fork()? Virtual Address Virtual Page # Offset (Process A): PageTablePtrA page #0 page #1 page #2 page #3 page #4 page #5 PageTablePtrB page #0 page #1 page #2 page #3 page #4 Virtual Address (Child proc B): Virtual Page # page #5 Offset V,R V,R N V,R N N V,R Parent address space Child address space

27 Unix fork() optimization Virtual Address Virtual Page # Offset (Process A): PageTablePtrA page #0 page #1 page #2 page #3 page #4 page #5 PageTablePtr page #0 page #1 page #2 page #3 page #4 page #5 Virtual Address (Child proc): Virtual Page # Offset V,R V,R N V,R N N V,R Child address space Parent address space

28 Unix fork() optimization Virtual Address Virtual Page # Offset (Process A): PageTablePtrA page #0 page #1 page #2 page #3 page #4 page #5 PageTablePtr page #0 page #1 page #2 page #3 page #4 page #5 Virtual Address (Child proc): Virtual Page # Offset V,R V,R N V,R N N V,R Parent address space Child Child address space When to split? Data write occurs

29 Copy-on-Write: Lazy copy during process creation COW allows both parent and child processes to initially share the same pages in memory. A shared page is duplicated only when modified COW allows more efficient process creation as only modified pages are copied

30 Copy on Write: After Process 1 Modifies Page C How to memorize a page is shared? When to detect the need for duplication? Need a page table entry bit Page table entry Physical page number

31 More examples of utilizing page table entries Page table entry Physical page number How do we use the PTE? Invalid PTE can imply different things: Region of address space is actually invalid or Page/directory is just somewhere else than memory Validity checked first OS can use other bits for location info Usage Example: Copy on Write Indicate a page is shared with a parent Usage Example: Demand Paging Keep only active pages in memory Place others on disk and mark their PTEs invalid

32 More examples of utilizing page table entries Usage Example: Zero Fill On Demand Security and performance advantages New pages carry no information Give new pages to a process initially with PTEs marked as invalid. During access time, page fault à physical frames are allocated and filled with zeros Often, OS creates zeroed pages in background Can a process modify its own translation tables? NO! If it could, could get access to all of physical memory Has to be restricted

33 Other Topics on Memory Management Page sharing among process What can page table entries be utilized? Other address translation implementation Hashed page tables Inverted page tables

34 Hashed Page Tables Common in address spaces > 32 bits Size of page table grows proportionally as large as amount of virtual memory allocated to processes Use hash table to limit the cost of search to one or at most a few page-table entries One hash table per process This page table contains a chain of elements hashing to the same location Use this hash table to find the physical page of each logical page If a match is found, the corresponding physical frame is extracted

35 Hashed Page Table

36 Inverted Page Table One hash table for all processes One entry for each real page of memory Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs

37 Inverted Page Table Architecture

38 Segmentation Paging (single-level page) Paged segmentation Two-level pages Address Translation Comparison Advantages Fast context switching: Segment mapping maintained by CPU No external fragmentation, fast easy allocation Table size ~ # of pages in virtual memory, fast easy allocation Inverted Table Table size ~ # of pages in physical memory Disadvantages External fragmentation Large table size ~ virtual memory Internal fragmentation Multiple memory references per page access Hash function more complex

39 Summary Page Tables Memory divided into fixed-sized chunks of memory Virtual page number from virtual address mapped through page table to physical page number Offset of virtual address same as physical address Large page tables can be placed into virtual memory Usage of page table entries Page sharing. Copy on write Pages on demand Zero fill on demand Multi-Level Tables Virtual address mapped to series of tables Permit sparse population of address space Inverted page table