Main Memory (Part II)
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1 Main Memory (Part II) Amir H. Payberah Amirkabir University of Technology (Tehran Polytechnic) Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 1 / 50
2 Reminder Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 2 / 50
3 Reminder (1/3) External fragmentation vs. internal fragmentation Compaction: shuffle memory contents to place all free memory together in one large block. Other solutions: Segmentation Paging Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 3 / 50
4 Reminder (2/3) Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 4 / 50
5 Reminder (3/3) Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 5 / 50
6 Paging Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 6 / 50
7 Paging vs. Segmentation Segmentation and paging, both, permit the physical address space of a process to be noncontiguous. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 7 / 50
8 Paging vs. Segmentation Segmentation and paging, both, permit the physical address space of a process to be noncontiguous. Paging avoids external fragmentation and the need for compaction, whereas segmentation does not. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 7 / 50
9 Paging (1/2) Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available. Avoids external fragmentation Avoids problem of varying sized memory chunks Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 8 / 50
10 Paging (1/2) Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available. Avoids external fragmentation Avoids problem of varying sized memory chunks Divide physical memory into fixed-sized blocks called frames. Size is power of 2, between 512 bytes and 16 Mbytes. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 8 / 50
11 Paging (1/2) Physical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available. Avoids external fragmentation Avoids problem of varying sized memory chunks Divide physical memory into fixed-sized blocks called frames. Size is power of 2, between 512 bytes and 16 Mbytes. Divide logical memory into blocks of same size called pages. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 8 / 50
12 Paging (2/2) Keep track of all free frames. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 9 / 50
13 Paging (2/2) Keep track of all free frames. To run a program of size N pages, need to find N free frames and load program. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 9 / 50
14 Paging (2/2) Keep track of all free frames. To run a program of size N pages, need to find N free frames and load program. Set up a page table to translate logical to physical addresses. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 9 / 50
15 Paging (2/2) Keep track of all free frames. To run a program of size N pages, need to find N free frames and load program. Set up a page table to translate logical to physical addresses. Still have internal fragmentation. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 9 / 50
16 Address Translation Scheme Address generated by CPU (logical address) is divided into two parts: Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 10 / 50
17 Address Translation Scheme Address generated by CPU (logical address) is divided into two parts: Page number (p): used as an index into a page table that contains base address of each page in physical memory. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 10 / 50
18 Address Translation Scheme Address generated by CPU (logical address) is divided into two parts: Page number (p): used as an index into a page table that contains base address of each page in physical memory. Page offset (d): combined with base address to define the physical memory address that is sent to the memory unit. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 10 / 50
19 Address Translation Scheme Address generated by CPU (logical address) is divided into two parts: Page number (p): used as an index into a page table that contains base address of each page in physical memory. Page offset (d): combined with base address to define the physical memory address that is sent to the memory unit. For given logical address space 2 m and page size 2 n. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 10 / 50
20 Paging Hardware Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 11 / 50
21 Paging Model of Logical and Physical Memory Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 12 / 50
22 Paging Example n = 2 and m = 4, 32-byte memory and 4-byte pages Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 13 / 50
23 Free Frames before allocation after allocation Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 14 / 50
24 Paging Example - Internal Fragmentation Page size = 2048 bytes Process size = bytes Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 15 / 50
25 Paging Example - Internal Fragmentation Page size = 2048 bytes Process size = bytes = 35 pages bytes Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 15 / 50
26 Paging Example - Internal Fragmentation Page size = 2048 bytes Process size = bytes = 35 pages bytes Internal fragmentation: = 962 bytes Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 15 / 50
27 Paging Example - Internal Fragmentation Page size = 2048 bytes Process size = bytes = 35 pages bytes Internal fragmentation: = 962 bytes Worst case fragmentation = 1 frame - 1 byte Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 15 / 50
28 Paging Example - Internal Fragmentation Page size = 2048 bytes Process size = bytes = 35 pages bytes Internal fragmentation: = 962 bytes Worst case fragmentation = 1 frame - 1 byte On average fragmentation = 1 2 frame size Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 15 / 50
29 Small Page Size vs. Big Page Size On average fragmentation = 1 2 are desirable. page size, hence, small page sizes Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 16 / 50
30 Small Page Size vs. Big Page Size On average fragmentation = 1 2 are desirable. page size, hence, small page sizes Small pages, more overhead is in the page-table, this overhead is reduced as the size of the pages increases. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 16 / 50
31 Small Page Size vs. Big Page Size On average fragmentation = 1 2 are desirable. page size, hence, small page sizes Small pages, more overhead is in the page-table, this overhead is reduced as the size of the pages increases. Disk I/O is more efficient when the amount data being transferred is larger (e.g., big pages). Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 16 / 50
32 Small Page Size vs. Big Page Size On average fragmentation = 1 2 are desirable. page size, hence, small page sizes Small pages, more overhead is in the page-table, this overhead is reduced as the size of the pages increases. Disk I/O is more efficient when the amount data being transferred is larger (e.g., big pages). Pages typically are between 4 KB and 8 KB in size. getconf PAGESIZE Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 16 / 50
33 Page Table Implementation Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 17 / 50
34 Page Table Page table is kept in main memory. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 18 / 50
35 Page Table Page table is kept in main memory. Page-table base register (PTBR) points to the page table. Page-table length register (PTLR) indicates size of the page table. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 18 / 50
36 Page Table Page table is kept in main memory. Page-table base register (PTBR) points to the page table. Page-table length register (PTLR) indicates size of the page table. In this scheme every data/instruction access requires two memory accesses. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 18 / 50
37 Page Table Page table is kept in main memory. Page-table base register (PTBR) points to the page table. Page-table length register (PTLR) indicates size of the page table. In this scheme every data/instruction access requires two memory accesses. One for the page table and one for the data/instruction. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 18 / 50
38 Translation Look-aside Buffers (TLB) The two memory access problem can be solved by the use of a special fast-lookup hardware cache called associative memory or translation look-aside buffers (TLBs). Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 19 / 50
39 Associative Memory Associative memory: parallel search Address translation (p, d) If p is in associative register, get frame# out Otherwise, get frame# from page table in memory Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 20 / 50
40 Paging Hardware With TLB Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 21 / 50
41 Effective Access Time Hit ratio: percentage of times that a page number is found in the TLB. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 22 / 50
42 Effective Access Time Hit ratio: percentage of times that a page number is found in the TLB. Effective Access Time (EAT) α: memory access latency h: hit ratio EAT = h α + (1 h) 2α Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 22 / 50
43 Effective Access Time Hit ratio: percentage of times that a page number is found in the TLB. Effective Access Time (EAT) α: memory access latency h: hit ratio EAT = h α + (1 h) 2α h = 80%, α = 100ns EAT = = 120ns Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 22 / 50
44 Effective Access Time Hit ratio: percentage of times that a page number is found in the TLB. Effective Access Time (EAT) α: memory access latency h: hit ratio EAT = h α + (1 h) 2α h = 80%, α = 100ns EAT = = 120ns h = 99%, α = 100ns EAT = = 101ns Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 22 / 50
45 More About TLB Some TLBs store address-space identifiers (ASIDs) in each TLB entry Uniquely identifies each process to provide address-space protection for that process. Otherwise, need to flush at every context switch. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 23 / 50
46 More About TLB Some TLBs store address-space identifiers (ASIDs) in each TLB entry Uniquely identifies each process to provide address-space protection for that process. Otherwise, need to flush at every context switch. TLBs typically small (64 to 1,024 entries) Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 23 / 50
47 More About TLB Some TLBs store address-space identifiers (ASIDs) in each TLB entry Uniquely identifies each process to provide address-space protection for that process. Otherwise, need to flush at every context switch. TLBs typically small (64 to 1,024 entries) On a TLB miss, value is loaded into the TLB for faster access next time. Replacement policies must be considered. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 23 / 50
48 Memory Protection Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 24 / 50
49 Memory Protection Memory protection implemented by associating protection bit with each frame to indicate if read-only or read-write access is allowed. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 25 / 50
50 Memory Protection Memory protection implemented by associating protection bit with each frame to indicate if read-only or read-write access is allowed. Valid-invalid bit attached to each entry in the page table: Valid indicates that the associated page is in the process logical address space, and is thus a legal page. Invalid indicates that the page is not in the process logical address space. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 25 / 50
51 Memory Protection Memory protection implemented by associating protection bit with each frame to indicate if read-only or read-write access is allowed. Valid-invalid bit attached to each entry in the page table: Valid indicates that the associated page is in the process logical address space, and is thus a legal page. Invalid indicates that the page is not in the process logical address space. Or use page-table length register (PTLR). Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 25 / 50
52 Memory Protection Memory protection implemented by associating protection bit with each frame to indicate if read-only or read-write access is allowed. Valid-invalid bit attached to each entry in the page table: Valid indicates that the associated page is in the process logical address space, and is thus a legal page. Invalid indicates that the page is not in the process logical address space. Or use page-table length register (PTLR). Any violations result in a trap to the kernel. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 25 / 50
53 Valid/Invalid Bit In A Page Table Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 26 / 50
54 Shared Pages Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 27 / 50
55 Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (e.g., text editors). Similar to multiple threads sharing the same process space. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 28 / 50
56 Shared Pages Shared code One copy of read-only (reentrant) code shared among processes (e.g., text editors). Similar to multiple threads sharing the same process space. Private code and data Each process keeps a separate copy of the code and data. The pages for the private code and data can appear anywhere in the logical address space. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 28 / 50
57 Shared Pages Example Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 29 / 50
58 Structure of the Page Table Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 30 / 50
59 Structure of the Page Table (1/2) Memory structures for paging can get huge using straight-forward methods. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 31 / 50
60 Structure of the Page Table (1/2) Memory structures for paging can get huge using straight-forward methods. Consider a 32-bit logical address space as on modern computers: Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 31 / 50
61 Structure of the Page Table (1/2) Memory structures for paging can get huge using straight-forward methods. Consider a 32-bit logical address space as on modern computers: Page size of 4KB = Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 31 / 50
62 Structure of the Page Table (1/2) Memory structures for paging can get huge using straight-forward methods. Consider a 32-bit logical address space as on modern computers: Page size of 4KB = Page table would have 1 million entries ( ). Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 31 / 50
63 Structure of the Page Table (1/2) Memory structures for paging can get huge using straight-forward methods. Consider a 32-bit logical address space as on modern computers: Page size of 4KB = Page table would have 1 million entries ( ). If each entry is 4B: 4MB of physical address space memory for page table alone. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 31 / 50
64 Structure of the Page Table (1/2) Memory structures for paging can get huge using straight-forward methods. Consider a 32-bit logical address space as on modern computers: Page size of 4KB = Page table would have 1 million entries ( ). If each entry is 4B: 4MB of physical address space memory for page table alone. That amount of memory used to cost a lot. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 31 / 50
65 Structure of the Page Table (1/2) Memory structures for paging can get huge using straight-forward methods. Consider a 32-bit logical address space as on modern computers: Page size of 4KB = Page table would have 1 million entries ( ). If each entry is 4B: 4MB of physical address space memory for page table alone. That amount of memory used to cost a lot. Don t want to allocate that contiguously in main memory. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 31 / 50
66 Structure of the Page Table (2/2) Hierarchical Paging Hashed Page Tables Inverted Page Tables Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 32 / 50
67 Hierarchical Paging Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 33 / 50
68 Hierarchical Page Tables Break up the logical address space into multiple page tables. A simple technique is a two-level page table. We then page the page table. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 34 / 50
69 Two-Level Page-Table Scheme Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 35 / 50
70 Two-Level Paging Example A logical address, on 32-bit machine with 1K page size, is divided: Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 36 / 50
71 Two-Level Paging Example A logical address, on 32-bit machine with 1K page size, is divided: A page number consisting of 22 bits. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 36 / 50
72 Two-Level Paging Example A logical address, on 32-bit machine with 1K page size, is divided: A page number consisting of 22 bits. A page offset consisting of 10 bits. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 36 / 50
73 Two-Level Paging Example A logical address, on 32-bit machine with 1K page size, is divided: A page number consisting of 22 bits. A page offset consisting of 10 bits. Since the page table is paged, the page number is divided into: A 12-bit page number. A 10-bit page offset. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 36 / 50
74 Two-Level Paging Example A logical address, on 32-bit machine with 1K page size, is divided: A page number consisting of 22 bits. A page offset consisting of 10 bits. Since the page table is paged, the page number is divided into: A 12-bit page number. A 10-bit page offset. Thus, a logical address is: where p 1 is an index into the outer page table, and p 2 is the displacement within the page of the inner page table. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 36 / 50
75 Two-Level Paging Example A logical address, on 32-bit machine with 1K page size, is divided: A page number consisting of 22 bits. A page offset consisting of 10 bits. Since the page table is paged, the page number is divided into: A 12-bit page number. A 10-bit page offset. Thus, a logical address is: where p 1 is an index into the outer page table, and p 2 is the displacement within the page of the inner page table. Known as forward-mapped page table. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 36 / 50
76 Address-Translation Scheme Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 37 / 50
77 64-bit Logical Address Space Even two-level paging scheme not sufficient. If page size is 4KB (2 12 ) Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 38 / 50
78 64-bit Logical Address Space Even two-level paging scheme not sufficient. If page size is 4KB (2 12 ) Then page table has 2 52 entries Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 38 / 50
79 64-bit Logical Address Space Even two-level paging scheme not sufficient. If page size is 4KB (2 12 ) Then page table has 2 52 entries If two level scheme, inner page tables could be 2 10, 4B entries Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 38 / 50
80 64-bit Logical Address Space Even two-level paging scheme not sufficient. If page size is 4KB (2 12 ) Then page table has 2 52 entries If two level scheme, inner page tables could be 2 10, 4B entries Outer page table has 2 42 entries or 2 44 B Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 38 / 50
81 64-bit Logical Address Space Even two-level paging scheme not sufficient. If page size is 4KB (2 12 ) Then page table has 2 52 entries If two level scheme, inner page tables could be 2 10, 4B entries Outer page table has 2 42 entries or 2 44 B Address would look like: Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 38 / 50
82 64-bit Logical Address Space Even two-level paging scheme not sufficient. If page size is 4KB (2 12 ) Then page table has 2 52 entries If two level scheme, inner page tables could be 2 10, 4B entries Outer page table has 2 42 entries or 2 44 B Address would look like: Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 38 / 50
83 Three-level Paging Scheme One solution is to add a 2nd outer page table. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 39 / 50
84 Three-level Paging Scheme One solution is to add a 2nd outer page table. But in the following example the 2nd outer page table is still 2 34 bytes in size. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 39 / 50
85 Three-level Paging Scheme One solution is to add a 2nd outer page table. But in the following example the 2nd outer page table is still 2 34 bytes in size. And possibly 4 memory access to get to one physical memory location. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 39 / 50
86 Hashed Page Tables Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 40 / 50
87 Hashed Page Tables (1/2) Common in address spaces > 32 bits The logical page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 41 / 50
88 Hashed Page Tables (2/2) Each element contains 1 The logical page number 2 The value of the mapped page frame 3 A pointer to the next element Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 42 / 50
89 Hashed Page Tables (2/2) Each element contains 1 The logical page number 2 The value of the mapped page frame 3 A pointer to the next element Logical page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 42 / 50
90 Hashed Page Table Architecture Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 43 / 50
91 Inverted Page Tables Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 44 / 50
92 Inverted Page Table (1/2) Rather than each process having a page table and keeping track of all possible logical pages, track all physical pages. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 45 / 50
93 Inverted Page Table (1/2) Rather than each process having a page table and keeping track of all possible logical pages, track all physical pages. One entry for each real page of memory. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 45 / 50
94 Inverted Page Table (1/2) Rather than each process having a page table and keeping track of all possible logical pages, track all physical pages. One entry for each real page of memory. Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 45 / 50
95 Inverted Page Table (2/2) Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 46 / 50
96 Inverted Page Table (2/2) Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs. Use hash table to limit the search to one, or at most a few, page-table entries. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 46 / 50
97 Inverted Page Table (2/2) Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs. Use hash table to limit the search to one, or at most a few, page-table entries. But how to implement shared memory? One mapping of a virtual address to the shared physical address Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 46 / 50
98 Inverted Page Table Architecture Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 47 / 50
99 Summary Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 48 / 50
100 Summary Paging vs. Segmentation Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 49 / 50
101 Summary Paging vs. Segmentation Physical memory: frames, Logical memory: pages Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 49 / 50
102 Summary Paging vs. Segmentation Physical memory: frames, Logical memory: pages Page table: translates logical to physical addresses Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 49 / 50
103 Summary Paging vs. Segmentation Physical memory: frames, Logical memory: pages Page table: translates logical to physical addresses Translation Look-aside Buffer (TLB) Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 49 / 50
104 Summary Paging vs. Segmentation Physical memory: frames, Logical memory: pages Page table: translates logical to physical addresses Translation Look-aside Buffer (TLB) Memory protection: valid-invalid bit Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 49 / 50
105 Summary Paging vs. Segmentation Physical memory: frames, Logical memory: pages Page table: translates logical to physical addresses Translation Look-aside Buffer (TLB) Memory protection: valid-invalid bit Page table structure: hierarchical paging, hashed page tables, inverted page tables Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 49 / 50
106 Questions? Acknowledgements Some slides were derived from Avi Silberschatz slides. Amir H. Payberah (Tehran Polytechnic) Main Memory 1393/8/17 50 / 50
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