TRACE32 Documents... TRACE32 Instruction Set Simulators... Simulator for MIPS TRACE32 Simulator License Quick Start of the Simulator...

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1 Simulator for MIPS TRACE32 Online Help TRACE32 Directory TRACE32 Index TRACE32 Documents... TRACE32 Instruction Set Simulators... Simulator for MIPS... 1 TRACE32 Simulator License... 4 Quick Start of the Simulator... 5 Peripheral Simulation... 7 Troubleshooting... 8 FAQ... 8 Memory Classes... 9 Belated Trace Analysis MIPS specific SYStem Commands SYStem.CONFIG Configure debugger according to target topology 11 SYStem.CPU Select the used CPU 11 SYStem.CpuAccess Run-time memory access (intrusive) 11 SYStem.LOCK Lock and tristate the debug port 12 SYStem.MemAccess Real-time memory access (non-intrusive) 12 SYStem.Option MMUSPACES Enable space IDs 13 SYStem.Mode Establish the communication with the target 14 SYStem.Option Address32 Use 32-bit addresses 14 SYStem.Option DisMode Define disassembler mode 15 SYStem.Option Endianness Define endianness of target memory 16 SYStem.Option IMASKASM Disable interrupts while ASM single stepping 16 SYStem.Option IMASKHLL Disable interrupts while HLL single stepping 16 SYStem.RESetOut CPU reset command 16 CPU specific MMU Commands MMU.DUMP Page wise display of MMU translation table 17 MMU.List Compact display of MMU translation table 18 MMU.SCAN Load MMU table from CPU 19 Support Available Tools 20 Compilers 25 Target Operating Systems 25 Simulator for MIPS 1

2 3rd-Party Tool Integrations 26 Products Product Information 27 Order Information 27 Simulator for MIPS 2

3 Simulator for MIPS Version 22-Mar-2018 All general commands are described in the IDE Reference Guide (ide_ref.pdf) and General Commands Reference. Simulator for MIPS 3

4 TRACE32 Simulator License [build DVD 02/2016] The extensive use of the TRACE32 Instruction Set Simulator requires a TRACE32 Simulator License. For more information, see Simulator for MIPS 4

5 Quick Start of the Simulator To start the simulator, proceed as follows: 1. Select the device prompt for the Debugger and reset the system. B:: RESet The device prompt B:: is normally already selected in the command line. If this is not the case, enter B:: to set the correct device prompt. The RESet command is only necessary if you do not start directly after booting TRACE Specify the CPU specific settings. SYStem.CPU <cpu_name> The default values of all other options are set in such a way that it should be possible to work without modification. Please consider that this is probably not the best configuration for your target. Simulator for MIPS 5

6 3. Enter debug mode. SYStem.Up This command resets the CPU and enters debug mode. After this command is executed it is possible to access memory and registers. 4. Load the program. Data.LOAD.format <filename> ; load program and symbols The format of the Data.LOAD command depends on the file format generated by the compiler. Refer to Supported Compilers to find the command that is necessary for your compiler. A detailed description of the Data.LOAD command and all available options is given in the reference guide. 5. Start-up example A typical start sequence is shown below. This sequence can be written to a PRACTICE script file (*.cmm, ASCII file format) and executed with the command DO <filename>. B:: WinCLEAR SYStem.CPU <cpu_name> SYStem.Up Data.LOAD.format <filename> Register.Set pc main PER.view ; Select the device prompt ; Clear all windows ; Select CPU type ; Reset the target and enter ; debug mode ; Load the application ; Set the PC to function main ; Show clearly arranged peripherals ; in window *) Data.List ; Open source code window *) Register /SpotLight ; Open register window *) Frame.view /Locals /Caller Var.Watch %Spotlight flags ast ; Open the stack frame with ; local variables *) ; Open watch window for ; variables *) *) These commands open windows on the screen. The window position can be specified with the WinPOS command. Simulator for MIPS 6

7 Peripheral Simulation For more information, see API for TRACE32 Instruction Set Simulator (simulator_api.pdf). Simulator for MIPS 7

8 Troubleshooting No information available. FAQ No information available Simulator for MIPS 8

9 Memory Classes The following MIPS specific memory classes are available. Memory Class P D CP0 CP1 CP2 CP3 DBG E VM Description Program Memory Data Memory Coprocessor 0 Register Coprocessor 1 Register (if implemented) Coprocessor 2 Register (if implemented) Coprocessor 3 Register (if implemented) Debug Memory Class (gives additional information) Emulation Memory, Pseudo Dualport Access to Memory (see SYStem.CpuAccess) Virtual Memory (memory on the debug system) To access a memory class write the class in front of the address. Examples: Data.dump CP0:0--3 displays the register 0 (Index), 1 (Random), 2 (EntryLo0), 3 (EntryLo1) of the System Control Coprocessor (=CP0). The register number can have values between 0 and 31. The value of select must be multiplied by 32 and added to the register number. Data.dump CP0:0x30--0x30 displays the Config1 register (register number: 0x10; select: 0x01). Select is 0 for the registers mentioned above. -MIPS64: For the memory classes CPx and DBG are only 64-bit (QUAD) write accesses possible. Simulator for MIPS 9

10 Belated Trace Analysis The following commands are required for a belated trace analysis: TCB.Version <number> TCB.SourceSizeBits <number> TCB.ThreadSizeBits <number> TCB.InsCompSizeBits <number> TCB.FCR ON OFF TCB.IM ON OFF TCB.LSM ON OFF TCB.Type <number> Inform the TRACE32 Instruction Set Simulator which trace cell version was used to record the loaded trace information. Inform the TRACE32 Instruction Set Simulator how much bits were used in the loaded trace information to identify the source core. Inform the TRACE32 Instruction Set Simulator how much bits were used in the loaded trace information to identify the source thread context. Inform the TRACE32 Instruction Set Simulator how much bits were used for instruction completion information. Inform the TRACE32 Instruction Set Simulator about existence of optional function call - return bit. Inform the TRACE32 Instruction Set Simulator about existence of optional Instruction cache miss bit. Inform the TRACE32 Instruction Set Simulator about existence of optional data cache load store miss bit. Inform the TRACE32 Instruction Set Simulator on the used Trace Control Block Type. Simulator for MIPS 10

11 MIPS specific SYStem Commands SYStem.CONFIG Configure debugger according to target topology The SYStem.CONFIG commands have no effect on the simulator. They are only provided to allow the user to run PRACTICE scripts written for the debugger within the simulator without modifications. SYStem.CPU Select the used CPU SYStem.CPU <cpu> <cpu>: AUTO MIPS4K RC32334 F MIPS5K SYStem.CpuAccess Run-time memory access (intrusive) SYStem.CpuAccess Enable Denied Nonstop Default: Denied. Enable Allow intrusive run-time memory access. Since a non-intrusive run-time memory access (SYStem.MemoryAccess CPU) is available for all TRACE32 instruction set simulators, there is no need for an intrusive run-time memory access. Simulator for MIPS 11

12 Denied Nonstop Lock intrusive run-time memory access. Lock all features of the debugger that affect the run-time behavior. Nonstop reduces the functionality of the debugger to: run-time access to memory and variables trace display The debugger inhibits the following: to stop the program execution all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.) SYStem.LOCK Lock and tristate the debug port SYStem.LOCK [ON OFF] Default: OFF. If the system is locked, no access to the debug port will be performed by the debugger. While locked, the debug connector of the debugger is tristated. The main intention of the lock command is to give debug access to another tool. The command has no effect for the simulator. SYStem.MemAccess Real-time memory access (non-intrusive). SYStem.MemAccess CPU Denied <cpu_specific> SYStem.ACCESS (deprecated) CPU Denied (default) Real-time memory access during program execution to target is enabled. Real-time memory access during program execution to target is disabled. Simulator for MIPS 12

13 SYStem.Option MMUSPACES Enable space IDs SYStem.Option MMUSPACES [ON OFF] SYStem.Option MMUspaces [ON OFF] (deprecated) SYStem.Option MMU [ON OFF] (deprecated) Default: OFF. Enables the use of space IDs for logical addresses to support multiple address spaces. NOTE: SYStem.Option MMUSPACES should not be used if only one translation table is used on the target. If a debug session requires space IDs, you must observe the following sequence of steps: 1. Activate SYStem.Option MMUSPACES. 2. Load the symbols with Data.LOAD. Otherwise, the internal symbol database of TRACE32 may become inconsistent. Examples: ;Dump logical address 0xC00208A belonging to memory space with ;space ID 0x012A: Data.dump D:0x012A:0xC00208A ;Dump logical address 0xC00208A belonging to memory space with ;space ID 0x0203: Data.dump D:0x0203:0xC00208A Simulator for MIPS 13

14 SYStem.Mode Establish the communication with the target SYStem.Mode <mode> <mode>: Down Up Down Up (Disables the debugger and keeps the CPU in reset. (default) Resets the target and sets the CPU to debug mode. After the execution of this command the CPU is stopped and all registers are set to the default level. SYStem.Option Address32 Use 32-bit addresses SYStem.Option Address32 [ON OFF] Default: OFF. This option is functionable for 64bit architectures only, not for 32bit architectures. Enable Address32 if you want to work with 32bit addresses on a 64bit MIPS CPU. If enabled, TRACE32 accepts and displays only 32bit addresses. Internally, they are sign-extended to 64bit addresses before they are used on the CPU. This results in a mapping as follows: Address used in TRACE32 0x x7FFF FFFF 0x xFFFF FFFF Mapped to address on 64bit CPU 0x x FFF FFFF 0xFFFF FFFF xFFFF FFFF FFFF FFFF As a result, with Address32 ON, only the 32bit Compatibility Address Spaces 0x x FFF FFFF and 0xFFFF FFFF xFFFF FFFF FFFF FFFF can be accessed. This option is helpful if you debug a 32bit Linux kernel on a 64bit MIPS CPU. Careful: if 64bit addresses are used in TRACE32 with Address32 ON, bits will truncated. Turn this option off if you need to access real 64bit addresses. Simulator for MIPS 14

15 SYStem.Option DisMode Define disassembler mode SYStem.Option DisMode <mode> <option>: AUTO ACCESS MIPS32 MIPS16 This command specifies the selected disassembler. Default: AUTO. AUTO ACCESS MIPS32 MIPS16 Automatic selection of disassembler mode. The information provided by the compiler output format is used for the disassembler selection. If no information is available it has the same behavior as ACCESS. (default) Disassembler mode will be selected by entered access class. The MIPS32 disassembler is used. The MIPS16 disassembler is used. Simulator for MIPS 15

16 SYStem.Option Endianness Define endianness of target memory SYStem.Option Endianness [AUTO Little Big] Default: AUTO. This option selects the byte ordering mechanism. If it is set to AUTO, the kernel mode endianness will be detected and selected. SYStem.Option IMASKASM Disable interrupts while ASM single stepping SYStem.Option IMASKASM [ON OFF] Default: OFF. If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. SYStem.Option IMASKHLL Disable interrupts while HLL single stepping SYStem.Option IMASKHLL [ON OFF] Default: OFF. If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are restored to the value before the step. SYStem.RESetOut CPU reset command The command asserts nreset on the JTAG connector in the TRACE32 In-Circuit Debugger () but is ignored by the TRACE32 Instruction Set Simulator. However, the command is allowed in the simulator so that you can run scripts which have actually been made for the debugger. For more information about the effect in the debugger, refer to your Processor Architecture Manual (debugger_<arch>.pdf). Simulator for MIPS 16

17 CPU specific MMU Commands MMU.DUMP Page wise display of MMU translation table MMU.DUMP <table> [<range> <addr> <range> <root> <addr> <root>] MMU.<table>.dump (deprecated) <table>: PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> <cpu_specific_tables> Displays the contents of the CPU specific MMU translation table. If called without parameters, the complete table will be displayed. If the command is called with either an address range or an explicit address, table entries will only be displayed, if their logical address matches with the given parameter. The optional <root> argument can be used to specify a page table base address deviating from the default page table base address. This allows to display a page table located anywhere in memory. PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> Display the current MMU translation table entries of the CPU. This command reads all tables the CPU currently uses for MMU translation and displays the table entries. Display the MMU translation table of the kernel. If specified with the MMU.FORMAT command, this command reads the MMU translation table of the kernel and displays its table entries. Display the MMU translation table entries of the given process. In MMU based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and displays its table entries. See also the appropriate OS awareness manuals: RTOS Debugger for <x>. For information about the parameters, see What to know about Magic Numbers, Task IDs and Task Names (general_ref_t.pdf). CPU specific tables: TLB Displays the contents of the Translation Lookaside Buffer. Simulator for MIPS 17

18 MMU.List Compact display of MMU translation table MMU.List <table> [<range> <addr> <range> <root> <addr> <root>] MMU.<table>.List (deprecated) <table>: PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> <space_id>:0x0 Lists the address translation of the CPU-specific MMU table. If called without address or range parameters, the complete table will be displayed. If called without a table specifier, this command shows the debugger-internal translation table. See TRANSlation.List. If the command is called with either an address range or an explicit address, table entries will only be displayed, if their logical address matches with the given parameter. <root> PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> The optional <root> argument can be used to specify a page table base address deviating from the default page table base address. This allows to display a page table located anywhere in memory. List the current MMU translation of the CPU. This command reads all tables the CPU currently uses for MMU translation and lists the address translation. List the MMU translation table of the kernel. If specified with the MMU.FORMAT command, this command reads the MMU translation table of the kernel and lists its address translation. List the MMU translation of the given process. In MMU-based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and lists its address translation. See also the appropriate OS awareness manuals: RTOS Debugger for <x>. For information about the parameters, see What to know about Magic Numbers, Task IDs and Task Names (general_ref_t.pdf). Simulator for MIPS 18

19 MMU.SCAN Load MMU table from CPU MMU.SCAN <table> [<range> <address>] MMU.<table>.SCAN (deprecated) <table>: PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> ALL <cpu_specific_tables> Loads the CPU-specific MMU translation table from the CPU to the debugger-internal translation table. If called without parameters, the complete page table will be loaded. The loaded address translation can be viewed with TRANSlation.List. If the command is called with either an address range or an explicit address, page table entries will only be loaded if their logical address matches with the given parameter. PageTable KernelPageTable TaskPageTable <magic_number> <task_id> <task_name> ALL Load the current MMU address translation of the CPU. This command reads all tables the CPU currently uses for MMU translation, and copies the address translation into the debugger-internal translation table. Load the MMU translation table of the kernel. If specified with the MMU.FORMAT command, this command reads the table of the kernel and copies its address translation into the debugger-internal translation table. Load the MMU address translation of the given process. In MMU-based operating systems, each process uses its own MMU translation table. This command reads the table of the specified process, and copies its address translation into the debugger-internal translation table. See also the appropriate OS awareness manual: RTOS Debugger for <x>. For information about the parameters, see What to know about Magic Numbers, Task IDs and Task Names (general_ref_t.pdf). Load all known MMU address translations. This command reads the OS kernel MMU table and the MMU tables of all processes and copies the complete address translation into the debuggerinternal translation table. See also the appropriate OS awareness manual: RTOS Debugger for <x>. CPU specific tables: TLB Loads the translation table from the CPU to the debugger internal translation table. Simulator for MIPS 19

20 Support Available Tools CPU ICE FIRE DEBUG MONITOR TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR 20KC YES YES 5KC YES YES 5KF YES YES ALUMINIUM YES YES AR2315 YES YES YES AR7 YES YES AR7242 YES YES YES AR9344 YES YES YES AU1000 YES YES AU1000LP YES YES AU1000N YES YES AU1100 YES YES AU1200 YES YES AU1500 YES YES AU1550 YES YES BCM1101 YES YES BCM1103 YES YES BCM1113 YES YES BCM1125 YES YES BCM1190 YES YES BCM1250 YES YES BCM1255 YES YES BCM1280 YES YES BCM1455 YES YES BCM1480 YES YES BCM3349 YES YES BCM3380 YES YES BCM35230 YES YES BCM3549 YES YES BCM3556 YES YES BCM4704 YES YES BCM47186 YES YES BCM471x YES YES BCM4748 YES YES Simulator for MIPS 20

21 CPU BCM5331x YES YES BCM5350 YES YES BCM5354 YES YES BCM5358 YES YES BCM5365 YES YES BCM56xxx YES YES BCM5836 YES YES BCM63168 YES YES BCM63268 YES YES BCM6328 YES YES BCM6338 YES YES BCM6345 YES YES BCM6348 YES YES BCM6358 YES YES BCM6362 YES YES BCM6368 YES YES BCM6369 YES YES BCM6550 YES YES BCM6816 YES YES BCM6818 YES YES BCM6828 YES YES BCM7038 YES YES BCM7111 YES YES BCM7231 YES YES BCM7312 YES YES BCM7317 YES YES BCM7318 YES YES BCM7325 YES YES BCM7335 YES YES BCM7346 YES YES BCM7356 YES YES BCM7358 YES YES BCM7400 YES YES BCM7401 YES YES BCM7402 YES YES BCM7405 YES YES BCM7407 YES YES BCM7413 YES YES BCM7418 YES YES BCM7420 YES YES BCM7425 YES YES Simulator for MIPS 21 ICE FIRE DEBUG MONITOR TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR

22 CPU BCM7435 YES YES BL25580 YES YES C7108 YES YES COACH12 YES YES EMMA3xxx YES YES FALCON YES YES HIDTV_PRO-QX YES YES IKF6833 YES YES IKF6834 YES YES IKF6836 YES YES IKF6850 YES YES IKF6860 YES YES IKF7185 YES YES LX4189 YES YES YES LX4X80 YES YES YES LX5180 YES YES YES LX5280 YES YES YES MDEB YES YES YES MDED YES YES YES MIPS1004K YES YES YES MIPS1004KMT YES YES YES MIPS1074K YES YES YES MIPS24K YES YES YES MIPS24KE YES YES YES MIPS34K YES YES YES MIPS4KC YES YES YES MIPS4KEC YES YES YES MIPS4KM YES YES YES MIPS4KP YES YES YES MIPS4KSD YES YES YES MIPS74K YES YES YES MIPSINTERAPTIV YES YES YES MIPSM14K YES YES YES MIPSM14KC YES YES YES MIPSM4K YES YES YES MP32 YES YES MSP2015 YES YES YES MSP2020 YES YES YES MSP7120 YES YES YES MSP7140 YES YES YES MSP8510 YES YES Simulator for MIPS 22 ICE FIRE DEBUG MONITOR TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR

23 CPU OCTEON_CN30XX YES YES OCTEON_CN31XX YES YES OCTEON_CN38XX YES YES OCTEON_CN50XX YES YES OCTEON_CN52XX YES YES OCTEON_CN54XX YES YES OCTEON_CN55XX YES YES OCTEON_CN56XX YES YES OCTEON_CN57XX YES YES OCTEON_CN58XX YES YES OCTEON_II_CN60XX YES YES OCTEON_II_CN61XX YES YES OCTEON_II_CN62XX YES YES OCTEON_II_CN63XX YES YES OCTEON_II_CN66XX YES YES OCTEON_II_CN67XX YES YES OCTEON_II_CN68XX YES YES OCTEON_III_CN70XX YES YES OCTEON_III_CN71XX YES YES OCTEON_III_CNF71XX YES YES P210 YES YES PIC32MX YES YES YES PIC32MZ YES YES YES PNX8330 YES YES PNX8331 YES YES PNX8332 YES YES PNX8335 YES YES PNX8535 YES YES PNX8541 YES YES PNX8542 YES YES PNX8543 YES YES PNX8932 YES YES PNX8935 YES YES PR3950 YES YES PR7530 YES YES PSB21553_INCA-IP YES YES PXB9101 YES YES PXB9102 YES YES PXB9201 YES YES PXB9202 YES YES RM7935 YES YES Simulator for MIPS 23 ICE FIRE DEBUG MONITOR TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR

24 CPU RM9000 YES YES RM9220 YES YES RM9224 YES YES RT3052 YES YES RT3352 YES YES RT3662 YES YES RTL8650 YES YES YES SMP8634 YES YES SMP8654 YES YES TNETC4320 YES YES TX4938 YES YES YES VCT9xxxP YES YES YES VDSL5100I YES YES VGCA YES YES YES VGCB YES YES YES VR5500A YES YES YES VR5701 YES YES YES WIN1xx YES YES WIN7xx YES YES WINPATH2 YES YES WINPATH3 YES YES WP3SL YES YES XLP1XX YES YES XLP2XX YES YES XLP3XX YES YES XLP4XX YES YES XLP8XX YES YES XLR YES YES XLS YES YES xrx100 YES YES xrx200 YES YES ICE FIRE DEBUG MONITOR TRACE POWER INTEGRATOR INSTRUCTION SIMULATOR Simulator for MIPS 24

25 Compilers Language Compiler Company Option Comment C TCC TASKING IEEE C++ GCC Free Software Foundation, Inc. ELF/DWARF C++ GREEN-HILLS- C++ Greenhills Software Inc. ELF/DWARF C++ SDE Imagination Technologies ELF/STABS Target Operating Systems Company Product Comment ecoscentric Limited ECOS 1.3, 2.0 and 3.0 freertos FreeRTOS up to v9 - Linux Kernel Version 2.4 and 2.6, 3.x, 4.x MontaVista Software, LLC Linux 3.0, 3.1, 4.0, 5.0 Mentor Graphics Nucleus Corporation Enea OSE Systems OSE Delta 4.x and 5.x - OSEK via ORTI Elektrobit Automotive GmbH ProOSEK via ORTI Renesas Technology, Corp. RX4000 esol Co., Ltd. T-Kernel Express Logic Inc. ThreadX 3.0, 4.0, 5.0 Micrium Inc. uc/os-ii 2.0 to uitron HI7000, RX4000, NORTi,PrKernel Wind River Systems VxWorks 5.x and 6.x Microsoft Corporation Windows CE 4.0 to 6.0 Microsoft Corporation Windows Mobile 4.0 to 6.0 Simulator for MIPS 25

26 3rd-Party Tool Integrations CPU Tool Company Host WINDOWS CE PLATF. - Windows BUILDER CODE::BLOCKS - - C++TEST - Windows ADENEO - X-TOOLS / X32 blue river software GmbH Windows CODEWRIGHT Borland Software Windows Corporation CODE CONFIDENCE Code Confidence Ltd Windows TOOLS CODE CONFIDENCE Code Confidence Ltd Linux TOOLS EASYCODE EASYCODE GmbH Windows ECLIPSE Eclipse Foundation, Inc Windows CHRONVIEW Inchron GmbH Windows LDRA TOOL SUITE LDRA Technology, Inc. Windows UML DEBUGGER LieberLieber Software Windows GmbH SIMULINK The MathWorks Inc. Windows ATTOL TOOLS MicroMax Inc. Windows VISUAL BASIC Microsoft Corporation Windows INTERFACE LABVIEW NATIONAL Windows INSTRUMENTS Corporation RAPITIME Rapita Systems Ltd. Windows RHAPSODY IN MICROC IBM Corp. Windows RHAPSODY IN C++ IBM Corp. Windows DA-C RistanCASE Windows TRACEANALYZER Symtavision GmbH Windows ECU-TEST TraceTronic GmbH Windows UNDODB Undo Software Linux TA INSPECTOR Vector Windows VECTORCAST UNIT Vector Software Windows TESTING VECTORCAST CODE COVERAGE Vector Software Windows Simulator for MIPS 26

27 Products Product Information OrderNo Code LA-8812 SIM-MIPS Text TRACE32 Instruction Set Simulator for MIPS TRACE32 Instruction Set Simulator Order Information Order No. Code Text LA-8812 SIM-MIPS TRACE32 Instruction Set Simulator for MIPS Simulator for MIPS 27