Page 1. Instruction-Level Parallelism (ILP) CISC 662 Graduate Computer Architecture Lectures 16 and 17 - Multiprocessors and Thread-Level Parallelism

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1 CISC 662 Graduate Computer Architecture Lectures 16 and 17 - Multiprocessors and Thread-Level Parallelism Michela Taufer Powerpoint Lecture Notes from John Hennessy and David Patterson s: Computer Architecture, 4th edition ---- Additional teaching material from: Jelena Mirkovic (U Del) and John Kubiatowicz (UC Berkeley) Instruction-Level Parallelism (ILP) Instruction-Level Parallelism (ILP): What all we have covered so far: simple pipelining dynamic scheduling: scoreboarding and Tomasulo s alg. dynamic branch prediction multiple-issue architectures: superscalar, VLIW hardware-based speculation compiler techniques and software approaches Bottom line: There just aren t enough instructions that can actually be executed in parallel! instruction issue: limit on maximum issue count branch prediction: imperfect # registers: finite functional units: limited in number data dependencies: hard to detect dependencies via memory 2 Performance beyond ILP There can be much higher natural parallelism in some applications (e.g., Database or Scientific codes) Explicit Thread Level Parallelism or Data Level Parallelism Thread: process with own instructions and data Thread may be a process part of a parallel program of multiple processes, or it may be an independent program Each thread has all the state (instructions, data, PC, register state, and so on) necessary to allow it to execute Data Level Parallelism: Perform identical operations on data, and lots of data Thread Level Parallelism (TLP) ILP exploits implicit parallel operations within a loop or straight-line code segment TLP explicitly represented by the use of multiple threads of execution that are inherently parallel Goal: Use multiple instruction streams to improve 1. Throughput of computers that run many programs 2. Execution time of multi-threaded programs TLP could be more cost-effective to exploit than ILP 3 4 Page 1

2 Thread Level Parallelism (II) Threads: multiple processes that share code and data (and much of their address space)» recently, the term has come to include processes that may run on different processors and even have disjoint address spaces, as long as they share the code Multithreading: exploit thread-level parallelism within a processor fine-grain multithreading» switch between threads on each instruction! coarse-grain multithreading» switch to a different thread only if current thread has a costly stall, e.g., switch only on a level-2 cache miss Multithreaded Execution Multithreading: multiple threads to share the functional units of 1 processor via overlapping processor must duplicate independent state of each thread e.g., a separate copy of register file, a separate PC, and for running independent programs, a separate page table memory shared through the virtual memory mechanisms, which already support multiple processes HW for fast thread switch; much faster than full process switch 100s to 1000s of clocks When switch? Alternate instruction per thread (fine grain) When a thread is stalled, perhaps for a cache miss, another thread can be executed (coarse grain) 5 6 Fine-Grained Multithreading Switches between threads on each instruction, causing the execution of multiples threads to be interleaved Usually done in a round-robin fashion, skipping any stalled threads CPU must be able to switch threads every clock Advantage is it can hide both short and long stalls, since instructions from other threads executed when one thread stalls Disadvantage is it slows down execution of individual threads, since a thread ready to execute without stalls will be delayed by instructions from other threads Used on Sun s Niagara (will see later) Review: Fine-Grained Multithreading Fine-grain multithreading switch between threads on each instruction! multiple threads executed in interleaved manner interleaving is usually round-robin CPU must be capable of switching threads on every cycle!» fast, frequent switches main disadvantage:» slows down the execution of individual threads» that is, traded off latency for better throughput 7 8 Page 2

3 Course-Grained Multithreading Switches threads only on costly stalls, such as L2 cache misses Advantages Relieves need to have very fast thread-switching Doesn t slow down thread, since instructions from other threads issued only when the thread encounters a costly stall Disadvantage is hard to overcome throughput losses from shorter stalls, due to pipeline start-up costs Since CPU issues instructions from 1 thread, when a stall occurs, the pipeline must be emptied or frozen New thread must fill pipeline before instructions can complete Because of this start-up overhead, coarse-grained multithreading is better for reducing penalty of high cost stalls, where pipeline refill << stall time Used in IBM AS/400 Review: Course-Grained Multithreading Coarse-grain multithreading switch only if current thread has a costly stall» e.g., level-2 cache miss can accommodate slightly costlier switches less likely to slow down an individual thread» a thread is switched off only when it has a costly stall main disadvantage:» limited in ability to overcome throughput losses shorter stalls are ignored, and there may be plenty of those» issues instructions from a single thread every switch involves emptying and restarting the instruction pipeling 9 10 For most apps: most execution units lie idle For an 8-way superscalar. From: Tullsen, Eggers, and Levy, Simultaneous Multithreading: Maximizing On-chip Parallelism, ISCA Do both ILP and TLP? TLP and ILP exploit two different kinds of parallel structure in a program Could a processor oriented at ILP to exploit TLP? functional units are often idle in data path designed for ILP because of either stalls or dependences in the code Could the TLP be used as a source of independent instructions that might keep the processor busy during stalls? Could TLP be used to employ the functional units that would otherwise lie idle when insufficient ILP exists? 12 Page 3

4 Simultaneous Multi-threading... One thread, 8 units Cycle M M FX FXFP FPBRCC Two threads, 8 units Cycle M M FX FXFP FPBRCC Simultaneous Multithreading (SMT) Simultaneous multithreading (SMT): insight that dynamically scheduled processor already has many HW mechanisms to support multithreading Large set of virtual registers that can be used to hold the register sets of independent threads Register renaming provides unique register identifiers, so instructions from multiple threads can be mixed in datapath without confusing sources and destinations across threads Out-of-order completion allows the threads to execute out of order, and get better utilization of the HW Just adding a per thread renaming table and keeping separate PCs Independent commitment can be supported by logically keeping a separate reorder buffer for each thread M = Load/Store, FX = Fixed Point, FP = Floating Point, BR = Branch, CC = Condition Codes 13 Source: Micrprocessor Report, December 6, 1999 Compaq Chooses SMT for Alpha 14 Review: Simultaneous Multithreading Example: Pentium with Hyperthreading Key Idea: Exploit ILP across multiple threads! i.e., convert thread-level parallelism into more ILP exploit following features of modern processors:» multiple functional units modern processors typically have more functional units available than a single thread can utilize» register renaming and dynamic scheduling multiple instructions from independent threads can co-exist and coexecute! Time (processor cycle) Multithreaded Categories Superscalar Fine-Grained Coarse-Grained Multiprocessing Simultaneous Multithreading 15 Thread 1 Thread 2 Thread 3 Thread 4 Thread 5 Idle slot 16 Page 4

5 Review: Multithreading (a) A superscalar processor with no multithreading (b) A superscalar processor with coarse-grain multithreading (c) A superscalar processor with fine-grain multithreading (d) A superscalar processor with simultaneous multithreading (SMT) Design Challenges in SMT Since SMT makes sense only with fine-grained implementation, impact of fine-grained scheduling on single thread performance? A preferred thread approach sacrifices neither throughput nor single-thread performance? Unfortunately, with a preferred thread, the processor is likely to sacrifice some throughput, when preferred thread stalls Larger register file needed to hold multiple contexts Clock cycle time, especially in: Instruction issue - more candidate instructions need to be considered Instruction completion - choosing which instructions to commit may be challenging Ensuring that cache and TLB conflicts generated by SMT do not degrade performance Increasing number of running processes Uniprocessor Performance (SPECint) Key Idea: Increase number of running processes multiple processes: at a given point in time» i.e., at the granularity of one (or a few) clock cycles» not sufficient to have multiple processes at the OS level! Two Approaches: multiple CPU s: each executing a distinct process» Multiprocessors or Parallel Architectures single CPU: executing multiple processes ( threads )» Multi-threading or Thread-level parallelism Performance (vs. VAX-11/780) From Hennessy and Patterson, Computer Architecture: A Quantitative Approach, 4th edition, %/year 52%/year??%/year 3X VAX : 25%/year 1978 to 1986 RISC + x86: 52%/year 1986 to 2002 RISC + x86:??%/year 2002 to present 20 Page 5

6 Other Factors Multiprocessors Growth in data-intensive applications Data bases, file servers, Growing interest in servers, server perf. Increasing desktop perf. less important Outside of graphics Improved understanding in how to use multiprocessors effectively Especially server where significant natural TLP Advantage of leveraging design investment by replication Rather than unique design Flynn s Taxonomy Flynn classified by data and control streams in 1966 Single Instruction Single Data (SISD) (Uniprocessor) Multiple Instruction Single Data (MISD) (????) SIMD Data Level Parallelism MIMD Thread Level Parallelism MIMD popular because Flexible: N pgms and 1 multithreaded pgm Cost-effective: same MPU in desktop & MIMD M.J. Flynn, "Very High-Speed Computers", Proc. of the IEEE, V 54, , Dec Single Instruction Multiple Data SIMD (single PC: Vector, CM-2) Multiple Instruction Multiple Data MIMD (Clusters, SMP servers) Flynn s Taxonomy Back to Basics A parallel computer is a collection of processing elements that cooperate and communicate to solve large problems fast. Parallel Architecture = Computer Architecture + Communication Architecture 2 classes of multiprocessors WRT memory: 1. Centralized Memory Multiprocessor < few dozen processor chips (and < 100 cores) in 2006 Small enough to share single, centralized memory 2. Physically Distributed-Memory multiprocessor Larger number chips and cores than 1. BW demands Memory distributed among processors Page 6

7 Centralized vs. Distributed Memory P 1 Mem P n Inter connection network Mem Scale Mem P 1 Mem Inter connection network P n Multiprocessor: Memory Organization Centralized, sharedmemory multiprocessor: usually few processors share single memory & bus use large caches Centralized Memory Distributed Memory Centralized Memory Multiprocessor Also called symmetric multiprocessors (SMPs) because single main memory has a symmetric relationship to all processors Large caches single memory can satisfy memory demands of small number of processors Can scale to a few dozen processors by using a switch and by using many memory banks Although scaling beyond that is technically conceivable, it becomes less attractive as the number of processors sharing centralized memory increases Multiprocessor: Memory Organization Distributed-memory multiprocessor: can support large processor counts» cost-effective way to scale memory bandwidth» works well if most accesses are to local memory node requires interconnection network» communication between processors becomes more complicated, slower Page 7

8 Distributed Memory Multiprocessor Pro: Cost-effective way to scale memory bandwidth If most accesses are to local memory Pro: Reduces latency of local memory accesses Con: Communicating data between processors more complex Con: Must change software to take advantage of increased memory BW E.g., OS has to be smart and allocate pages/migrate pages when not properly located. 2 Models for Communication and Memory Architecture 1. Communication occurs by explicitly passing messages among the processors: message-passing multiprocessors 2. Communication occurs through a shared address space (via loads and stores): shared memory multiprocessors either UMA (Uniform Memory Access time) for shared address, centralized memory MP NUMA (Non Uniform Memory Access time multiprocessor) for shared address, distributed memory MP Share meant as shared address space: In past, confusion whether sharing means sharing physical memory (Symmetric MP) or sharing address space Challenges of Parallel Processing First challenge is % of program inherently sequential Suppose 80X speedup from 100 processors. What fraction of original program can be sequential? a.10% b.5% c.1% d. <1% Challenges of Parallel Processing Second challenge is long latency to remote memory Suppose 32 CPU MP, 2GHz, 200 ns remote memory, all local accesses hit memory hierarchy and base CPI is 0.5. (Remote access = 200/0.5 = 400 clock cycles.) What is performance impact if 0.2% instructions involve remote access? a. 1.5X b. 2.0X c. 2.5X Page 8

9 Challenges of Parallel Processing 1. Application parallelism primarily via new algorithms that have better parallel performance 2. Long remote latency impact both by architect and by the programmer For example, reduce frequency of remote accesses either by Caching shared data (HW) Restructuring the data layout to make more accesses local (SW) HW helps latency via caches Symmetric Shared Memory and Snoopy Protocol Symmetric Shared-Memory Architectures From multiple boards on a shared bus to multiple processors inside a single chip Caches both Private data are used by a single processor Shared data are used by multiple processors Caching shared data reduces latency to shared data, memory bandwidth for shared data, and interconnect bandwidth cache coherence problem Example Cache Coherence Problem u :5 1 P 1 u =? 4 5 u :5 Memory P 2 P 3 I/O devices Processors see different values for u after event 3 With write back caches, value written back to memory depends on happenstance of which cache flushes or writes back value when» Processes accessing main memory may see very stale value Unacceptable for programming, and its frequent! u =? 2 3 u :5 u = Page 9

10 Example Intuitive Memory Model A = 1; P 1 P 2 /*Assume initial value of A and flag is 0*/ flag = 1; print A; while (flag == 0); /*spin idly*/ Intuition not guaranteed by coherence Expect memory to respect order between accesses to different locations issued by a given process to preserve orders among accesses to same location by different processes Coherence is not enough! pertains only to single location P 1 Conceptual Picture Mem P n 37 Memory Disk L2 L1 100:34 P 100:67 100:35 Reading an address should return the last value written to that address Easy in uniprocessors, except for I/O Too vague and simplistic; 2 issues 1. Coherence defines values returned by a read 2. Consistency determines when a written value will be returned by a read Coherence defines behavior to same location; Consistency defines behavior to other locations Note: Words do not say what they mean but architects are using these words 38 Defining Coherent Memory System Write Consistency 1. Preserve Program Order: A read by processor P to location X that follows a write by P to X, with no writes of X by another processor occurring between the write and the read by P, always returns the value written by P 2. Coherent view of memory: Read by a processor to location X that follows a write by another processor to X returns the written value if the read and write are sufficiently separated in time and no other writes to X occur between the two accesses 3. Write serialization: 2 writes to same location by any 2 processors are seen in the same order by all processors If not, a processor could keep value 1 since saw as last write For example, if the values 1 and then 2 are written to a location, processors can never read the value of the location as 2 and then later read it as 1 For now assume: 1. A write does not complete (and allow the next write to occur) until all processors have seen the effect of that write 2. The processor does not change the order of any write with respect to any other memory access if a processor writes location A followed by location B, any processor that sees the new value of B must also see the new value of A These restrictions allow the processor to reorder reads, but forces the processor to finish writes in program order Page 10

11 Basic Schemes for Enforcing Coherence Program on multiple processors will normally have copies of the same data in several caches Unlike I/O, where its rare Rather than trying to avoid sharing in SW, SMPs use a HW protocol to maintain coherent caches Migration and Replication key to performance of shared data Migration - data can be moved to a local cache and used there in a transparent fashion Reduces both latency to access shared data that is allocated remotely and bandwidth demand on the shared memory Replication for shared data being simultaneously read, since caches make a copy of data in local cache Reduces both latency of access and contention for read shared data 2 Classes of Cache Coherence Protocols 1. Directory based Sharing status of a block of physical memory is kept in just one location, the directory 2. Snooping Every cache with a copy of data also has a copy of sharing status of block, but no centralized state is kept All caches are accessible via some broadcast medium (a bus or switch) All cache controllers monitor or snoop on the medium to determine whether or not they have a copy of a block that is requested on a bus or switch access Snoopy Cache-Coherence Protocols Example: Write-thru Invalidate State Address Data P 1 Bus snoop P n P 1 P 2 P 3 u =? 3 u =? 4 5 u :5 u :5 u = 7 Mem I/O devices Cache-memory transaction Cache Controller snoops all transactions on the shared medium (bus or switch) relevant transaction if for a block it contains take action to ensure coherence» invalidate, update, or supply value depends on state of the block and the protocol Either get exclusive access before write via write invalidate (write invalidate) or update all copies on write (write update or write broadcast) 1 u :5 u = 7 Memory I/O devices Must invalidate before step 3 Write update uses more broadcast medium BW all recent MPUs use write invalidate Page 11

12 Architectural Building Blocks Cache block state transition diagram FSM specifying how disposition of block changes» invalid, valid, dirty Broadcast Medium Transactions (e.g., bus) Fundamental system design abstraction Logically single set of wires connect several devices Protocol: arbitration, command / addr, data Every device observes every transaction Broadcast medium enforces serialization of read or write accesses Write serialization 1 st processor to get medium invalidates others copies Implies cannot complete write until it obtains bus All coherence schemes require serializing accesses to same cache block Also need to find up-to-date copy of cache block Locate up-to-date copy of data Write-through: get up-to-date copy from memory Write through simpler if enough memory BW Write-back: harder Most recent copy can be in a cache Can use same snooping mechanism 1. Snoop every address placed on the bus 2. If a processor has dirty copy of requested cache block, it provides it in response to a read request and aborts the memory access Complexity from retrieving cache block from a processor cache, which can take longer than retrieving it from memory Write-back needs lower memory bandwidth Support larger numbers of faster processors Most multiprocessors use write-back Cache Resources for WB Snooping Normal cache tags can be used for snooping Valid bit per block makes invalidation easy Read misses easy since rely on snooping Writes Need to know if know whether any other copies of the block are cached No other copies No need to place write on bus for WB Other copies Need to place invalidate on bus Cache Resources for WB Snooping To track whether a cache block is shared, add extra state bit associated with each cache block, like valid bit and dirty bit Write to Shared block Need to place invalidate on bus and mark cache block as private (if an option) No further invalidations will be sent for that block This processor called owner of cache block Owner then changes state from shared to unshared (or exclusive) Page 12

13 Cache Behavior in Response to Bus Every bus transaction must check the cacheaddress tags Could potentially interfere with processor cache accesses A way to reduce interference is to duplicate tags One set for caches access, one set for bus accesses Another way to reduce interference is to use L2 tags Since L2 less heavily used than L1 Every entry in L1 cache must be present in the L2 cache, called the inclusion property If Snoop gets a hit in L2 cache, then it must arbitrate for the L1 cache to update the state and possibly retrieve the data, which usually requires a stall of the processor Example Protocol Snooping coherence protocol is usually implemented by incorporating a finite-state controller in each node Logically, think of a separate controller associated with each cache block That is, snooping operations or cache requests for different blocks can proceed independently In implementations, a single controller allows multiple operations to distinct blocks to proceed in interleaved fashion That is, one operation may be initiated before another is completed, even through only one cache access or one bus access is allowed at time Write-through Invalidate Protocol 2 states per block in each cache as in uniprocessor state of a block is a p-vector of states hardware state bits associated with blocks that are in the cache other blocks can be seen as being in PrRd / BusRd invalid (not-present) state in that cache Writes invalidate all other cache copies can have multiple simultaneous readers of block, but write invalidates them State Tag Data PrRd: Processor Read PrWr: Processor Write BusRd: Bus Read BusWr: Bus Write P 1 Mem V I PrRd/ -- PrWr / BusWr BusWr / - PrWr / BusWr State Tag Data P n Bus I/O devices 51 Is 2-state Protocol Coherent? Processor only observes state of memory system by issuing memory operations Assume bus transactions and memory operations are atomic and a one-level cache all phases of one bus transaction complete before next one starts processor waits for memory operation to complete before issuing next with one-level cache, assume invalidations applied during bus transaction All writes go to bus + atomicity Writes serialized by order in which they appear on bus (bus order) => invalidations applied to caches in bus order How to insert reads in this order? Important since processors see writes through reads, so determines whether write serialization is satisfied But read hits may happen independently and do not appear on bus or enter directly in bus order Let s understand other ordering issues 52 Page 13

14 Ordering Example Write Back Snoopy Protocol P 0 : P 1 : P 2 : R R R R R R Writes establish a partial order Doesn t constrain ordering of reads, though shared-medium (bus) will order read misses too any order among reads between writes is fine, as long as in program order W R R R R R W R R R R R Invalidation protocol, write-back cache Snoops every address on bus If it has a dirty copy of requested block, provides that block in response to the read request and aborts the memory access Each memory block is in one state: Clean in all caches and up-to-date in memory (Shared) OR Dirty in exactly one cache (Exclusive) OR Not in any caches Each cache block is in one state (track these): Shared : block can be read OR Exclusive : cache has only copy, its writeable, and dirty OR Invalid : block contains no data (in uniprocessor cache too) Read misses: cause all caches to snoop bus Writes to clean blocks are treated as misses Write-Back State Machine - CPU State machine for CPU requests for each cache block Non-resident blocks invalid Invalid CPU read Place read miss on bus CPU Read hit Shared (read/only) Write-Back State Machine - Bus request State machine for bus requests for each cache block Invalid Write miss for this block Shared (read/only) CPU write Cache Block State CPU read hit CPU write hit Place write miss on bus Exclusive (read/write) CPU write Place write miss on bus CPU write miss (?) Write back cache block Place write miss on bus 55 Write miss for this block Write Back Block; (abort memory access) Exclusive (read/write) Read miss for this block Write Back Block; (abort memory access) 56 Page 14

15 Block-replacement State machine for CPU requests for each cache block Cache Block State CPU Write Invalid Place write miss on bus CPU read hit CPU write hit Exclusive (read/write) CPU read Place read miss on bus CPU Read hit Shared (read/only) CPU read miss CPU read miss Write back block, Place read miss Place read miss on bus on bus CPU write miss Place Write Miss on Bus CPU write miss Write back cache block Place write miss on bus 57 Write-back State Machine-III State machine for CPU requests for each cache block and for bus requests for each cache block Cache Block State Write miss for this block Write Back Block; (abort memory access) CPU read hit CPU write hit Write miss for this block Invalid CPU Read Place read miss CPU Write on bus Place Write Miss on bus CPU read miss Write back block, Exclusive (read/write) Place read miss on bus CPU Read hit Shared (read/only) CPU Read miss Place read miss on bus CPU Write Place Write Miss on Bus Read miss for this block Write Back Block; (abort memory access) CPU Write Miss Write back cache block Place write miss on bus 58 Example Example P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 P1: P1: Read Read A1 A1 P2: Read A1 P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read Read A1 A1 P2: Read A1 P2: Write 20 to A1 P2: Write 40 to A2 P2: Write 20 to A1 P2: Write 40 to A2 Assumes A1 and A2 map to same cache block, initial cache state is invalid Assumes A1 and A2 map to same cache block Page 15

16 Example Example P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read Read A1 A1 Excl. A1 10 P2: Read A1 P2: Write 20 to A1 P2: Write 40 to A2 P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read Read A1 A1 Excl. A1 10 P2: Read A1 Shar. A1 RdMs P2 A1 Shar. A1 10 WrBk P1 A1 10 A1 10 Shar. A1 10 RdDa P2 A1 10 A1 10 P2: Write 20 to A1 P2: Write 40 to A2 Assumes A1 and A2 map to same cache block Assumes A1 and A2 map to same cache block Example Example P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read Read A1 A1 Excl. A1 10 P2: Read A1 Shar. A1 RdMs P2 A1 Shar. A1 10 WrBk P1 A1 10 A1 10 Shar. A1 10 RdDa P2 A1 10 A1 10 P2: Write 20 to A1 Inv. Excl. A1 20 WrMs P2 A1 A1 10 P2: Write 40 to A2 P1 P2 Bus Memory step State Addr Value State Addr Value Action Proc. Addr Value Addr Value P1: Write 10 to A1 Excl. A1 10 WrMs P1 A1 P1: P1: Read Read A1 A1 Excl. A1 10 P2: Read A1 Shar. A1 RdMs P2 A1 Shar. A1 10 WrBk P1 A1 10 A1 10 Shar. A1 10 RdDa P2 A1 10 A1 10 P2: Write 20 to A1 Inv. Excl. A1 20 WrMs P2 A1 A1 10 P2: Write 40 to A2 WrMs P2 A2 A1 10 Excl. A2 40 WrBk P2 A1 20 A1 20 Assumes A1 and A2 map to same cache block Assumes A1 and A2 map to same cache block, but A1!= A Page 16

17 Implementation Complications Write Races: Cannot update cache until bus is obtained» Otherwise, another processor may get bus first, and then write the same cache block! Two step process:» Arbitrate for bus» Place miss on bus and complete operation If miss occurs to block while waiting for bus, handle miss (invalidate may be needed) and then restart. Split transaction bus:» Bus transaction is not atomic: can have multiple outstanding transactions for a block» Multiple misses can interleave, allowing two caches to grab block in the Exclusive state» Must track and prevent multiple misses for one block Must support interventions and invalidations Implementing Snooping Caches Multiple processors must be on bus, access to both addresses and data Add a few new commands to perform coherency, in addition to read and write Processors continuously snoop on address bus If address matches tag, either invalidate or update Since every bus transaction checks cache tags, could interfere with CPU just to check: solution 1: duplicate set of tags for L1 caches just to allow checks in parallel with CPU solution 2: L2 cache already duplicate, provided L2 obeys inclusion with L1 cache» block size, associativity of L2 affects L Limitations in Symmetric Shared-Memory Multiprocessors and Snooping Protocols Single memory accommodate all CPUs Multiple memory banks Bus-based multiprocessor, bus must support both coherence traffic & normal memory traffic Multiple buses or interconnection networks (cross bar or small point-to-point) Opteron Memory connected directly to each dual-core chip Point-to-point connections for up to 4 chips Remote memory and local memory latency are similar, allowing OS Opteron as UMA computer Performance of Symmetric Shared- Memory Multiprocessors Cache performance is combination of 1. Uniprocessor cache miss traffic 2. Traffic caused by communication Results in invalidations and subsequent cache misses 4 th C: coherence miss Joins Compulsory, Capacity, Conflict Page 17

18 Coherency Misses 1. True sharing misses arise from the communication of data through the cache coherence mechanism Invalidates due to 1 st write to shared block Reads by another CPU of modified block in different cache Miss would still occur if block size were 1 word 2. False sharing misses when a block is invalidated because some word in the block, other than the one being read, is written into Invalidation does not cause a new value to be communicated, but only causes an extra cache miss Block is shared, but no word in block is actually shared miss would not occur if block size were 1 word Example: True v. False Sharing v. Hit? Assume x1 and x2 in same cache block. P1 and P2 both read x1 and x2 before. Time P1 P2 True, False, Hit? Why? 1 Write x1 2 Read x2 3 Write x1 4 Write x2 5 Read x2 True miss; invalidate x1 in P2 False miss; x1 irrelevant to P2 False miss; x1 irrelevant to P2 False miss; x1 irrelevant to P2 True miss; invalidate x2 in P Distributed Shared Memory and Directory-Based Coherence A Cache Coherent System Must: Provide set of states, state transition diagram, and actions Manage coherence protocol (0) Determine when to invoke coherence protocol (a) Find info about state of block in other caches to determine action» whether need to communicate with other cached copies (b) Locate the other copies (c) Communicate with those copies (invalidate/update) (0) is done the same way on all systems state of the line is maintained in the cache protocol is invoked if an access fault occurs on the line Different approaches distinguished by (a) to (c) Page 18

19 Bus-based Coherence All of (a), (b), (c) done through broadcast on bus faulting processor sends out a search others respond to the search probe and take necessary action Could do it in scalable network too broadcast to all processors, and let them respond Conceptually simple, but broadcast doesn t scale with p on bus, bus bandwidth doesn t scale on scalable network, every fault leads to at least p network transactions Scalable coherence: can have same cache states and state transition diagram different mechanisms to manage protocol Scalable Approach: Directories Every memory block has associated directory information keeps track of copies of cached blocks and their states on a miss, find directory entry, look it up, and communicate only with the nodes that have copies if necessary in scalable networks, communication with directory and copies is through network transactions Many alternatives for organizing directory information Basic Operation of Directory Directory Protocol Memory P Cache P Cache Interconnection Network presence bits dirty bit Directory k processors. With each cache-block in memory: k presence-bits, 1 dirty-bit With each cache-block in cache: 1 valid bit, and 1 dirty (owner) bit Read from main memory by processor i: If dirty-bit OFF then { read from main memory; turn p[i] ON; } if dirty-bit ON then { recall line from dirty proc (cache state to shared); update memory; turn dirty-bit OFF; turn p[i] ON; supply recalled data to i;} Write to main memory by processor i: If dirty-bit OFF then { supply data to i; send invalidations to all caches that have the block; turn dirty-bit ON; turn p[i] ON;... } A directory must track the state of each cache block Similar to Snoopy Protocol: Three states Shared: 1 processors have data, memory up-to-date Uncached (no processor has it; not valid in any cache) Exclusive: 1 processor (owner) has data; memory out-of-date In addition to cache state, must track which processors have data when in the shared state (usually bit vector, 1 if processor has copy) Keep it simple(r): Writes to non-exclusive data write miss Processor blocks until access completes Assume messages received and acted upon in order sent 76 Page 19

20 Directory Protocol No bus and don t want to broadcast: interconnect no longer single arbitration point all messages have explicit responses Terms: typically 3 processors involved Local node where a request originates Remote node has a copy of a cache block, whether exclusive or shared Home node where the memory location of an address resides Example messages on next slide: P = processor number, A = address Directory Protocol Messages (Fig 4.20) Message type Source Destination Msg Content Read miss Local cache Home directory P, A Processor P reads data at address A; make P a read sharer and request data Write miss Local cache Home directory P, A Processor P has a write miss at address A; make P the exclusive owner and request data Invalidate Local cache Home directory A - Request to send invalidates to all remote caches that are caching the block at address A Invalidate Home directory Remote caches A Invalidate a shared copy at address A Fetch Home directory Remote cache A Fetch the block at address A and send it to its home directory; change the state of A in the remote cache to shared Fetch/Invalidate Home directory Remote cache A Fetch the block at address A and send it to its home directory; invalidate the block in the cache Data value reply Home directory Local cache Data Return a data value from the home memory (read miss response) Data write back Remote cache Home directory A, Data Write back a data value for address A (invalidate response) State Transition Diagram for One Cache Block in Directory Based System States identical to snoopy case; transactions very similar Transitions caused by read misses, write misses, invalidates, data fetch requests Generates read miss & write miss message to home directory Write misses that were broadcast on the bus for snooping explicit invalidate & data fetch requests Note: on a write, a cache block is bigger, so need to read the full cache block 79 CPU -Cache State Machine State machine for CPU requests for each memory block Invalid state if in memory Fetch/Invalidate send Data Write Back message to home directory CPU read hit CPU write hit Invalid Exclusive (read/write) Invalidate CPU Read Send Read Miss message CPU Write: Send Write Miss msg to home directory CPU Read hit Shared (read/only) CPU read miss: Send Read Miss CPU Write: Send Write Miss message to home directory Fetch: send Data Write Back message to home directory CPU read miss: send Data Write Back message and read miss to home directory CPU write miss: send Data Write Back message and Write Miss to home directory 80 Page 20

21 State Transition Diagram for Directory Same states & structure as the transition diagram for an individual cache 2 actions: update of directory state & send messages to satisfy requests Tracks all copies of memory block Also indicates an action that updates the sharing set, Sharers, as well as sending a message Example Directory Protocol Message sent to directory causes two actions: Update the directory More messages to satisfy request Block is in Uncached state: the copy in memory is the current value; only possible requests for that block are: Read miss: requesting processor sent data from memory &requestor made only sharing node; state of block made Shared. Write miss: requesting processor is sent the value & becomes the Sharing node. The block is made Exclusive to indicate that the only valid copy is cached. Sharers indicates the identity of the owner. Block is Shared the memory value is up-to-date: Read miss: requesting processor is sent back the data from memory & requesting processor is added to the sharing set. Write miss: requesting processor is sent the value. All processors in the set Sharers are sent invalidate messages, & Sharers is set to identity of requesting processor. The state of the block is made Exclusive Example Directory Protocol Block is Exclusive: current value of the block is held in the cache of the processor identified by the set Sharers (the owner) three possible directory requests: Read miss: owner processor sent data fetch message, causing state of block in owner s cache to transition to Shared and causes owner to send data to directory, where it is written to memory & sent back to requesting processor. Identity of requesting processor is added to set Sharers, which still contains the identity of the processor that was the owner (since it still has a readable copy). State is shared. Data write-back: owner processor is replacing the block and hence must write it back, making memory copy up-to-date (the home directory essentially becomes the owner), the block is now Uncached, and the Sharer set is empty. Write miss: block has a new owner. A message is sent to old owner causing the cache to send the value of the block to the directory from which it is sent to the requesting processor, which becomes the new owner. Sharers is set to identity of new owner, and state of block is made Exclusive. 83 Directory State Machine State machine for Directory requests for each memory block Uncached state if in memory Data Write Back: Sharers = {} (Write back block) Write Miss: Sharers = {P}; send Fetch/Invalidate; send Data Value Reply msg to remote cache Uncached Exclusive (read/write) Read miss: Sharers = {P} send Data Value Reply Write Miss: Sharers = {P}; send Data Value Reply msg Shared (read only) Write Miss: send Invalidate to Sharers; then Sharers = {P}; send Data Value Reply msg Read miss: Sharers += {P}; send Fetch; send Data Value Reply msg to remote cache (Write back block) Read miss: Sharers += {P}; send Data Value Reply 84 Page 21

22 Example Example step P1: Write 10 to A1 P1: Read A1 P2: Read A1 Processor 1 Processor 2 Interconnect Directory Memory P1 P2 Bus Directory Memor StateAddr ValueStateAddrValueActionProc. Addr Value Addr State{Procs}Value Processor 1 Processor 2 Interconnect Directory Memory P1 P2 Bus Directory Memor step StateAddr ValueStateAddrValueActionProc. Addr Value Addr State{Procs}Value P1: Write 10 to A1 WrMs P1 A1 A1 Ex {P1} Excl. A1 10 DaRp P1 A1 0 P1: Read A1 P2: Read A1 P2: Write 20 to A1 P2: Write 40 to A2 P2: Write 20 to A1 P2: Write 40 to A2 A1 and A2 map to the same cache block A1 and A2 map to the same cache block Example Example P1 P2 Bus Directory Memor step StateAddr ValueStateAddrValueActionProc. Addr Value Addr State{Procs}Value P1: Write 10 to A1 WrMs P1 A1 A1 Ex {P1} Excl. A1 10 DaRp P1 A1 0 P1: Read A1 Excl. A1 10 P2: Read A1 P2: Write 20 to A1 P2: Write 40 to A2 Processor 1 Processor 2 Interconnect Directory Memory Processor 1 Processor 2 Interconnect Directory Memory P1 P2 Bus Directory Memor step StateAddr ValueStateAddrValueActionProc. Addr Value Addr State{Procs}Value P1: Write 10 to A1 WrMs P1 A1 A1 Ex {P1} Excl. A1 10 DaRp P1 A1 0 P1: Read A1 Excl. A1 10 P2: Read A1 Shar. A1 RdMs P2 A1 Shar. A1 10 Ftch P1 A1 10 A1 A1 10 Shar. A1 10 DaRp P2 A1 10 A1 Shar. {P1,P2} 10 P2: Write 20 to A P2: Write 40 to A2 10 A1 and A2 map to the same cache block Write Back A1 and A2 map to the same cache block Page 22

23 Example Example Processor 1 Processor 2 Interconnect Directory Memory P1 P2 Bus Directory Memor step StateAddr ValueStateAddrValueActionProc. Addr Value Addr State{Procs}Value P1: Write 10 to A1 WrMs P1 A1 A1 Ex {P1} Excl. A1 10 DaRp P1 A1 0 P1: Read A1 Excl. A1 10 P2: Read A1 Shar. A1 RdMs P2 A1 Shar. A1 10 Ftch P1 A1 10 A1 A1 10 Shar. A1 10 DaRp P2 A1 10 A1 Shar. {P1,P2} 10 P2: Write 20 to A1 Excl. A1 20 WrMs P2 A1 10 Inv. Inval. P1 A1 A1 Excl. {P2} 10 P2: Write 40 to A2 10 Processor 1 Processor 2 Interconnect Directory Memory P1 P2 Bus Directory Memor step StateAddr ValueStateAddrValueActionProc. Addr Value Addr State{Procs}Value P1: Write 10 to A1 WrMs P1 A1 A1 Ex {P1} Excl. A1 10 DaRp P1 A1 0 P1: Read A1 Excl. A1 10 P2: Read A1 Shar. A1 RdMs P2 A1 Shar. A1 10 Ftch P1 A1 10 A1 A1 10 Shar. A1 10 DaRp P2 A1 10 A1 Shar. {P1,P2} 10 P2: Write 20 to A1 Excl. A1 20 WrMs P2 A1 10 Inv. Inval. P1 A1 A1 Excl. {P2} 10 P2: Write 40 to A2 WrMs P2 A2 A2 Excl. {P2} 0 WrBk P2 A1 20 A1 Unca. {} 20 Excl. A2 40 DaRp P2 A2 0 A2 Excl. {P2} 0 A1 and A2 map to the same cache block A1 and A2 map to the same cache block (but different memory block addresses A1 A2) Implementing a Directory Basic Directory Transactions We assume operations atomic, but they are not; reality is much harder; must avoid deadlock when run out of buffers in network (see Appendix E) Optimizations: read miss or write miss in Exclusive: send data directly to requestor from owner vs. 1st to memory and then from memory to requestor Requestor C P A 3. Read req. to owner C P A M/D M/D 4a. Data Reply 1. Read request to directory 2. Reply with owner identity 4b. C P A Revision message to directory Directory node for block M/D C P A C P A 3a. 3b. Inval. req. to sharer M/D Inval. ack Requestor M/D Inval. req. to sharer 2. 4a. 4b. C P A 1. RdEx request to directory Reply with sharers identity Inval. ack M/D C P A M/D Directorynode Node with dirty copy (a) Read miss to a block in dirty state Sharer Sharer (b) Write miss to a block with two sharers Page 23

24 Example Directory Protocol (1 st Read) Example Directory Protocol (Read Share) D D Read pa P1: pa S R/reply Dir ctrl M P1: pa P2: pa R/_ S R/reply Dir ctrl M U U E E E E S I R/req P1 ld va -> rd pa S I P2 R/_ S I R/req P1 ld va -> rd pa R/_ S I R/req P2 ld va -> rd pa Example Directory Protocol (Wr to shared) Example Directory Protocol (Wr to Ex) D RU/_ D RX/invalidate&reply RX/invalidate&reply P1: pa EX P2: pa reply xd(pa) R/_ S U R/reply Dir ctrl M Inv ACK P1: pa Inv pa R/_ S U R/reply Dir ctrl M Read_toUpdate pa Read_to_update pa Invalidate pa Write_back pa Reply xd(pa) W/_ E W/req E E W/_ E W/req E W/_ E W/req E W/req E W/req E W/req E R/_ S I R/req P1 st va -> wr pa R/_ Inv/_ S I R/req P2 R/_ Inv/_ S I R/req P1 R/_ Inv/_ S I R/req P2 st va -> wr pa Page 24

25 A Popular Middle Ground Two-level hierarchy Individual nodes are multiprocessors, connected nonhiearchically e.g. mesh of SMPs Coherence across nodes is directory-based directory keeps track of nodes, not individual processors Coherence within nodes is snooping or directory orthogonal, but needs a good interface of functionality SMP on a chip directory + snoop? And in Conclusion End of uniprocessors speedup => Multiprocessors Parallelism challenges: % parallalizable, long latency to remote memory Centralized vs. distributed memory Small MP vs. lower latency, larger BW for Larger MP Message Passing vs. Shared Address Uniform access time vs. Non-uniform access time Snooping cache over shared medium for smaller MP by invalidating other cached copies on write Sharing cached data Coherence (values returned by a read), Consistency (when a written value will be returned by a read) Shared medium serializes writes Write consistency Page 25