MP1800A Series Signal Quality Analyzer MU182020A/40A, MU182021A/41A 25 Gbit/s 1ch MUX/DEMUX, 25 Gbit/s 2ch MUX/DEMUX

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1 Product Brochure MP1800A Series Signal Quality Analyzer MU182020A/40A, MU182021A/41A 25 Gbit/s 1ch MUX/DEMUX, 25 Gbit/s 2ch MUX/DEMUX MU181020B/40B 14 Gbit/s PPG/ED MU181800B 14 GHz Clock Distributor

2 For 100 GbE, Ultrafast Interconnects, and 40G R&D The increasing numbers of Internet users, spread of rich-content services, and rising access speeds of DSL, WiFi, WiMax, FTTx, etc., are forcing Internet Exchanges (IX) and ISPs to tackle the serious problems of inadequate bandwidth. Solutions to further increases in transmission capacities meeting IX and ISP needs are being discussed by IEEE, ITU-T and OIF with focus on standards for next-generation 100 GbE, 40 Gbit/s Networking and ultrafast PC interconnects. Progress in standards is driving vendor R&D towards prompt rollout of faster devices. To help customers bring these new products to market in the fastest possible time, Anritsu has developed the MP1800A with all the key functions and performance required for R&D and design verification of devices for 100G/40 GbE, long-haul 40 Gbit/s transmission and ultrafast interconnects. Applications IEEE802.3ba Standard 100 GbE 20G band ultrafast interconnects 40 Gbit/s long haul transmission using phase modulation such as DQPSK MU181800B 14 GHz Clock Distributor Features Evaluation of next-generation interfaces supporting operation frequencies up to 28 Gbit/s Direct-drive EML using high-quality, high-amplitude waveforms up to 3.5 Vp-p Two channels synchronization enables evaluation of skew, emphasis, and crosstalk effects Testing DQPSK modulators, etc., using I and Q signal dynamic control Easy operation using Auto Search function Modular design supporting staged infrastructure upgrades meeting customers' evolving needs MU182020A 25 Gbit/s 1ch MUX MU182040A 25 Gbit/s 1ch DEMUX MU182021A 25 Gbit/s 2ch MUX MU182041A 25 Gbit/s 2ch DEMUX 2

3 Application 100 GbE EML/Optical Device Evaluation 4ch PPG + 2ch MUX Data #1 Data #2 xdata #1 xdata #2 EML 4 PD 4 Opt-MUX Opt-DEMUX Data #1 2ch DEMUX + 4ch ED LAN-WDM Data #2 100 Gbit/s MP1800A 25 Gbit/s 4 25 Gbit/s 4 MP1800A 1/1 or 1/2 Clock 1/1 or 1/2 Clock MG3693B 100 GbE EML/Optical Device Evaluations Required Test 25 Gbit/s BER Measurement Optimum optical output waveform adjustment using crosspoint adjustment Interlane timing and skew control Input sensitivity testing 100 GbE, 25G 4λ evaluation The MP1800A can evaluate EML devices and optical modulators for 100 GbE services standardized by IEEE802.3ba using MUX/DEMUX modules supporting frequencies up to 28 Gbit/s. 4ch EML devices can be driven using Data and xdata for 2ch MUX independently and simoustaniously, offering evaluation with excellent cost performance. Providing optimum signal quality for EML evaluation 25G band EML devices can be direct-driven by variable data output function at up to 3.5 Vp-p. The amplitude and crosspoint are easily adjusted on-screen, shortening evaluation times and offering high-reliability evaluation. Skew and crosstalk effect check Application using 20G class signals requires both logic tests and actual equipment tests. The MP1800A supports both pattern synchronization and phase adjustment functions, permitting easy testing of Rx device skew tolerance and crosstalk effects. Built-in Auto Search function Auto-adjustment of data and clock error is simplified using the built-in Auto Search function. 3

4 20G Band Ultrafast Interconnect Evaluation Jitter Jittered 1/2 Clock Jitter 4ch PPG + 2ch MUX Data #1 1ch DEMUX + 2ch ED + Synthesizer Data #2 xdata #1 xdata #2 Data 20 Gbit/s MP1800A Jittered 20 Gbit/s 4 MP1800A 20G Ultrafast Interconnect Jitter Tolerance Evaluation Required Test 20 Gbit/s BER Measurement Jitter tolerance testing Emphasis efficiency check Interlane timing and skew control Jitter tolerance testing The jitter tolerance of high-speed devices up to 25 Gbit/s can be tested using the internal jitter modulation function. Emphasis effect check Because the amplitude and phase between two synchronized channels can be adjusted easily, waveforms with any emphasis are easily generated for testing the emphasis effect on the PCB. Skew and Crosstalk effect check Processing 20G-class signals requires both logic tests and actual equipment tests. The MP1800A supports both pattern synchronization and phase adjustment functions, permitting easy tests of Rx device skew tolerance and crosstalk effects. 4

5 40G Band DQPSK Optical Module/Device Evaluation 4ch PPG + 2ch MUX RZ-DQPSK Modulator RZ-DQPSK Demodulator 2ch DEMUX + 4ch ED I Channel Q Channel LD π/2 RZ RZ-DQPSK 40 Gbit/s T T π/2 I Channel Q Channel MP1800A 20 Gbit/s x 2 20 Gbit/s x 2 MP1800A 1/1 Clock 1/1 Clock MG3693B 40G Band DQPSK Optical Module/Device Evaluation Required Test Modulated I and Q Channel BER measurement Optimum optical output waveform adjustment using crosspoint adjustment Inter I, Q signal timing and skew control Input sensitivity test BER Measurement using modulated I, Q channels The Pre-Code function automatically generates 100G DP-QPSK and 40G DQPSK, DPSK, and ODB modulation signals for evaluating optical modulators. The De-Code function is for evaluating the logic of precoders in optical modules. Hardware-based generation of modulation signals produces pure PRBS31 signals without pattern length restrictions, resulting in high-reliability evaluations using high-load pseudo random patterns closely approximating real signals. Providing optimum signal quality for EML evaluation 25G-band EML devices can be direct-driven by variable data output function at up to 3.5 Vp-p. The amplitude and crosspoint are easily adjusted on-screen, shortening evaluation times and offering high-reliability evaluation. Skew effect check Processing 20G-class signals requires both logic tests and actual equipment tests. The MP1800A supports both pattern synchronization and phase adjustment functions, permitting easy tests of Rx device skew tolerance and crosstalk effects. 5

6 Selection Guide Category Model Number Model Name 1: Select as necessary 2: Select any one 28 Gbit/s 1ch MUX/ DEMUX 100 GbE 20G Band Ultrafast Interconnects MP1800A Signal Quality Analyzer Main Frame MP1800A Slot for PPG and/or ED MP1800A Slot for PPG and/or ED MU181000A 12.5 GHz Synthesizer 1 Synthesizer MU181000A-001 Jitter Modulation 1 MG3693B 2 to 30 GHz Signal Generator MU181020A 12.5 Gbit/s PPG 4 4 MU181020A to 12.5 Gbit/s 4 4 MU181020A-010 Variable Data Output (0.05 to 0.8 Vp-p) 12.5 Gbit/s MU181020A-011 Variable Data Output (0.25 to 2.5 Vp-p) PPG MU181020A-012 High Performance Data Output (0.05 to 2.0 Vp-p) MU181020A-013 Variable Data Output (0.5 to 3.5 Vp-p) MU181020A-021 Differential Clock Output (0.1 to 2.0 Vp-p) MU181020A-030 Variable Data Delay 4 4 MU181020B 14 Gbit/s PPG 2 4 MU181020B to 14 Gbit/s 2 4 MU181020B-011 Variable Data Output (0.25 to 2.5 Vp-p) 14 Gbit/s MU181020B-012 High Performance Data Output (0.05 to 2.0 Vp-p) PPG MU181020B-013 Variable Data Output (0.5 to 3.5 Vp-p) MU181020B-021 Differential Clock Output (0.1 to 2.0 Vp-p) MU181020B-030 Variable Data Delay 2 4 MU181040A 12.5 Gbit/s ED Gbit/s MU181040A to 12.5 Gbit/s 2 4 ED MU181040A-020 Clock Recovery MU181040A-030 Variable Clock Delay 2 4 MU181040B 14 Gbit/s ED Gbit/s MU181040B to 14 Gbit/s 2 4 ED MU181040B-020 Clock Recovery MU181040B-030 Variable Clock Delay 2 4 MU182020A 25 Gbit/s 1ch MUX 1 MU182020A Gbit/s Extension 1 MU182020A-002 Clock Input Band Switch 1 MU182020A-010 Variable Data Output (0.25 to 1.75 Vp-p) 1ch MU182020A-011 Variable Data Output (0.5 to 2.5 Vp-p) MUX MU182020A-013 Variable Data Output (0.5 to 3.5 Vp-p) 1*2 MU182020A-021 Variable Clock Output (0.5 to 2.0 Vp-p) MU182020A Gbit/s Variable Data Delay MU182020A Gbit/s Variable Data Delay MU182040A 25 Gbit/s 1ch DEMUX 1 1 MU182040A Gbit/s Extension 1 1ch MU182040A-002 Clock Input Band Switch 1 DEMUX MU182040A GHz Variable Clock Delay 1 MU182040A GHz Variable Clock Delay 1 MU182021A 25 Gbit/s 2ch MUX MU182021A Gbit/s Extension 1 MU182021A-002 Clock Input Band Switch 1*1 1 MU182021A-010 Variable Data Output (0.25 to 1.75 Vp-p) 2ch MU182021A-011 Variable Data Output (0.5 to 2.5 Vp-p) 1*2 1*2 1*2 MUX MU182021A-013 Variable Data Output (0.5 to 3.5 Vp-p) MU182021A-021 Variable Clock Output (0.5 to 2.0 Vp-p) MU182021A Gbit/s Variable Data Delay 1 1 MU182021A Gbit/s Variable Data Delay 1 MU182020A-040 Emphasis Control*3 1 MU182041A 25 Gbit/s 2ch DEMUX 1 1 MU182041A Gbit/s Extension 1 2ch MU182041A-002 Clock Input Band Switch 1*1 1 DEMUX MU182041A GHz Variable Clock Delay 1 MU182040A GHz Variable Clock Delay 1 Software MX180005A Jitter Application Software 1 40G DQPSK 3: When the MU182021A-040 is installed and a Power Divider is connected externally by combining between each Data, an emphasis signal can be generated downstream of the Power Divider. An optional external attenuator can be added to the combined signal to help reduce waveform distortion or jitter caused by reflection, etc. When generating an emphasis signal as described above, we recommend using the following accessories. 41KC-3 Coaxial Attenuator (3 db) 41KC-6 Coaxial Attenuator (6 db) 41KC-10 Coaxial Attenuator (10 db) 41KC-20 Coaxial Attenuator (20 db) K240C Power Divider K120MM-20CM DC to 40 GHz, 50 Ω, 20 cm, K(m) to K(m) 6

7 MU181800B 14 GHz Clock Distributor Operation Frequency Clock Input Clock Output 0.1 to 14 GHz MU181020B 14 Gbit/s PPG Option Operating Bit Rate External Clock Input Generation Pattern Error Insertion Auxiliary Input Auxiliary Output Gating Output PRBS Zero Substitution Data Alternate Mixed Pattern Sequence Pattern Input Level: 0.4 to 2.0 Vp-p Waveform: <0.5 GHz square wave, 0.5 GHz square wave or sine wave Input Impedance, : 50 Ω/GND, SMA 5ch Single-end Output Level: Min. 0.4 Vp-p, Max. 1.0 Vp-p Duty: 50%±10% (50% Clock Input Duty) Channel Skew: 10 ps (14 GHz) Output Impedance, : 50 Ω/GND, SMA 0.1 to 14 Gbit/s Input frequency: 0.1 to 14 GHz Input level: Min. 0.4 Vp-p, Max. 1.5 Vp-p ( 4 to +7.5 dbm) Square wave (<0.5 GHz), Square or sine wave ( 0.5 GHz) Duty: 50% Input Impedance, : 50 Ω/AC, SMA MU181020B to 14 Gbit/s Steps: 2 n 1 (n = 7, 9, 10, 11, 15, 20, 23, 31) Mark ratio: 1/2, 1/4, 1/8, 0/8; 1/2, 3/4, 7/8, 8/8 supported at reverse logic AND bit shift: 1 bit, 3 bits, (Prohibited at 1/2, 1/2, 0/8, 8/8 mark ratio) Pattern with continuous 0s appended to M-sequence signal+1 bit Pattern: 2 n or 2 n 1 (n = 7, 9, 10, 11, 15, 20, 23) 0 continuous substitution count: 1 to (pattern length 1) bits Other: 0 at next bit after 0 substitution changed to 1 Data length: 2 to 134,217,728 bits/ch, Steps: 1 bit Data length: 128 to 67,108,864 bits/ch (independent bits for A/B) Steps: 128 bits Loop count: 511 times A/B set independently A/B switching: Internal: Auto-switching by A/B loop times setting External: Controlled by external signal Editing: Pattern editing for A/B independently Pattern: PRBS, Data-1 to Data-511 Data+PRBS Length: 768 to ,217,728, Steps: 128 bits Data length: 512 to 134,217,728 bits Block count: 1 to 128 Block length: 16,384 to 1,048,576 bits, Steps: 128 bits Loop count: 1 to 1,024 times, Repeat Block Transition Conditions: A pattern match, B pattern match, Manual, Loop Time complete, External trigger (rising edge) Next destination: Specified Block No. or Stop Error event: Repeat, Single, Error rate: #E n (# = 1 to 9, n = 2 to 12) Internal/External ALTN Trigger/Sequence Trigger/Error Injection/Burst Enable (Switchable) Input frequency: 64 bit width Input level: H: 0 V, L: 1 V Input Impedance, : 50 Ω/GND, SMA 1/n Clock (n = 2, 4, 8, 9, 10, 11., 510, 511) Pattern Sync Output level: H: 0 V, L: 1 V Output Impedance, : 50 Ω/GND, SMA Burst Output Signal at Burst, Timing Signal at Repeat 1ch Output Output level: H: 0 V, L: 1 V Output Impedance, : 50 Ω/GND, SMA 7

8 Option No Option MU181020B-011/111 MU181020B-012/112 MU181020B-013/113 Output Number Data Output 2 (Data/Data) Offset 0.25 to 2.5 Vp-p Steps: 2 mv Setting accuracy: ±50 mv ±17% 2.0 to +3.3 Voh Steps: 1 mv Current Limiting Sourcing 50 ma/sinking 80 ma 0.05 to 2.0 Vp-p Steps: 2 mv Setting accuracy: ±50 mv ±17% 0.5 to 3.5 Vp-p Steps: 2 mv Setting accuracy: ±50 mv ±17% (Crosspoint 20 to 80%, 10 Gbit/s, : 1.0 to 3.0 Vp-p) Output Level H: 0 V/L: 1.0 V Fixed Interface NECL, SCFL, NCML, PCML, LVPECL (+3.3 V), LVDS Crosspoint 50%±15% Tr/Tf 35 ps typ. (20 to 80%) ( 5 Gbit/s) 30 to 70% Steps: 1% 28 ps typ.(20 to 80%) ( 5 Gbit/s) 20 to 80% Steps: 1% 20 ps typ.(20 to 80%) (10, 12.5, 14 Gbit/s 2 Vp-p) NECL, SCFL, NCML, PCML, LVPECL 20 to 90% Steps: 0.1% Total Jitter 10 ps typ. 10 ps p-p typ. 8 ps p-p typ. 8 ps p-p typ. 25 ps typ.(20 to 80%) (10 Gbit/s 1 Vp-p) Distortion (0-peak) ±25 mv ±6% typ. ±25 mv ±10% typ. Termination GND/50 Ω Output ON/OFF Always ON ON/OFF SMA K AC, DC At DC GND, 2 V, +1.3 V, +3.3 V, Open (LVDS)/50 Ω AC, DC At DC GND, 2 V, +1.3 V, +3.3 V/50 Ω Clock Output Clock Option No Option MU181020B-021/121 Differential Clock Output Output Number 1 (Clock) 2 (Clock/Clock) Min Vp-p Max. 0.9 Vp-p (AC) Duty 50%±15% Offset 0.1 to 2.0 Vp-p Steps: 2 mv 25 to 75 Steps: to +3.3 Voh Steps: 1 mv Current Limiting Sourcing 50 ma/sinking 80 ma Fixed Interface NECL, SCFL, NCML, PCML, LVPECL (+3.3 V), LVDS Tr/Tf 30 ps typ.(20 to 80%) 24 ps typ.(20 to 80%) Total Jitter 1 ps typ.(rms) 1 ps typ.(rms) Termination GND/50 Ω Output ON/OFF Always ON ON/OFF SMA K MU181020B-030/130 Variable Data Delay Operation Temperatures 15 to 35 C MU181040B 14 Gbit/s ED Operation Bit Rate Reception Pattern Option PRBS Zero Substitution Data Mixed Pattern 0.1 to 14 Gbit/s Sequence Pattern Block count: 1 to 128 AC, DC At DC GND, 2 V, +1.3 V, +3.3 V, Open (LVDS)/50 Ω Independent Mode Phase setting range: 1 to +1 UI, Steps: 1 mui Unit: UI/ps CH Synchronization or Combination Mode Phase setting range: 64 to +64 UI, Steps: 1 mui Unit: UI/ps MU181040B-002 Steps: 2 n 1 (n = 7, 9, 10, 11, 15, 20, 23, 31) Mark ratio: 1/2, 1/4, 1/8, 0/8; 1/2, 3/4, 7/8, 8/8 supported at reverse logic AND bit shift: 1 bit, 3 bits (Prohibited at 1/2, 1/2, 0/8, 8/8 mark ratio) Pattern with continuous 0s appended to M-sequence signal +1 bit Pattern: 2 n or 2 n 1 (n = 7, 9, 10, 11, 15, 20, 23) 0 continuous substitution count: 1 to (pattern length 1) bits Other: 0 at next bit after 0 substitution changed to 1 Data length: 2 to 134,217,728 bits/ch, Steps: 1 bit Pattern: PRBS, Data-1 to Data-511 Data+PRBS Length: 768 to ,217,728, Steps: 128 bits Data length: 512 to 134,217,728 bits 8

9 Detection Item Display Item Option Input Signal Synchronization Error Analysis MU181040B-002 Total Error, Insertion Error, Omission Error, Transition Error, Non-Transition Error Bit error rate, Bit error count, Input signal frequency Auto Sync.: ON/OFF Input signal capture (128 Mbits), Eye Margin, Eye Diagram, Q measurement, Bathtub, ISI Analysis Burst Signal Measurement Burst Trigger: Internal/External Input Option Number No Option MU181040B-020/120* Clock Recovery Clock Input Data Input Auxiliary Input Auxiliary Output Data Monitor Output Bit Rate Recovered Clock Output Operating Frequency Range Clock Source Input Waveform Input Number 1 Input Level Termination Condition Input Number Input Impedance Signal Format Input Threshold 0.1 to 14 GHz 0.1 GHz to 0.2 GHz 0.25 to 0.4 GHz 0.5 to 0.8 GHz 1 to 1.6 GHz 2 to 3.2 GHz 4.25 GHz 4.9 to 6.25 GHz 9.8 to 12.5 GHz POS/NEG reversible (without MU181040B-030/130) : 0.55 ±0.15 Vp-p : SMA Recovered/External (MU181040B-020/120 installed) Square wave (<0.5 GHz), Square or sine wave ( 0.5 GHz) Duty 50% Min Vp-p, Max. 1.5 Vp-p GND/50 Ω, Variable/50 Ω, Differential/100 Ω NECL, PCML (+3.3 V), LVPECL (+3.3 V), GND Variable: 2.5 to +3.5 V, Steps: 10 mv SMA 2 (Data, Data) Single: 50 Ω Differential: 50/100 Ω NRZ Min. 0.1 Vp-p, Max. 2.0 Vp-p 3.5 to +3.3 V, Steps: 1 mv Input Sensitivity 20 mvp-p typ. (14 Gbit/s PRBS ) Phase Margin 50 ps p-p typ. (14 Gbit/s PRBS ) Termination Condition Output Number Insertion Loss Termination MU181040B-030/130 Variable Clock Delay GND/50 Ω, Variable/50 Ω, Differential/100 Ω NECL, PCML (+3.3 V), LVPECL (+3.3 V), GND Variable: 2.5 to +3.5 V, Steps: 10 mv K Sequence Trigger/Capture Trigger/Burst Enable (switchable) Input frequency: 64 bit width Input level: H: 0 V, L: 1 V Input Impedance, : 50 Ω/GND, SMA 1/N Clock (N = 8 to 511, Steps 1), Pattern Sync, Error, Sync Gain Output level: H: 0 V, L: 1 V 2 (Data, Data) 6 db +1 db/ 2.5 db AC/50 Ω SMA Operation Temperatures 15 to 35 C Phase Setting Range: 1 to +1 UI, Steps: 1 mui Unit: UI/ps : We recommend adding the option of MU181040B-030/130 Variable Clock Delay when using MU181040B-020/120 Clock Recovery. MU182020A 25 Gbit/s 1ch MUX Operating Bit Rate External Clock Input Input Frequency Input 8 to 25 Gbit/s 8 to 28 Gbit/s (Installed option-001) 4.0 to 12.5 GHz 4.0 to 14.0 GHz (Installed option-001) 4.0 to 12.5 GHz, 8.0 to 25.0 GHz (Installed option-002) 4.0 to 14.0 GHz, 8.0 to 28.0 GHz (Installed option-001 and 002) 0.3 to 1.0 Vp-p SMA (f.) K (f.) (Installed option-002) 9

10 Data Output Setting Accuracy Offset Cross Point Adjust Tr/Tf Total Jitter Distortion (0-peak) Output On/Off Function Clock Output Offset Duty Output On/Off Function 1/2 Data Input Number of Input 1/2 Clock Input Number of Input 1/2 Clock Output Data Output Delay Phase Variable Range Phase Setting Error 10 2 (Data, xdata) 0.25 to 1.75 Vp-p/Steps: 2 mv (Installed option-010) 0.5 to 2.5 Vp-p/Steps: 2 mv (Installed option-011) 0.5 to 3.5 Vp-p/Steps: 2 mv (Installed option-013) ±50 mv ±17% (Cross point 50% or 30 to 80%, 25Gbit/s) 2.0 to +3.3 Voh/Steps: 1 mv 20 to 80%/Steps: 0.1% (25 Gbit/s) Typ.12 ps (20 to 80%) Typ.8 ps p-p Typ.±25 mv ±10% (25 Gbit/s) K (f.) Enable * : The above specifications were measured with the oscilloscope, intrinsic jitter should be less than 200 fs (rms), and more than 70 GHz bandwidth. Output clock frequency is same of input clock frequency. 1 (Clock) Min. 0.3 Vp-p, Max. 1.0 Vp-p (Fixed) Min. 0.7 Vp-p, Max. 1.0 Vp-p (Fixed) (Installed option-002) 0.5 to 2.0 Vp-p/Steps: 2 mv (Installed option-021) 2.0 to +3.3 Voh/Steps: 1 mv (Installed option-021) 25 to +25/Steps: 1 (Installed option-021) K(f.) (Installed option-002 or 021) Enable (Installed option-002 or 021) 2 (1/2 Data Input A, 1/2 Data Input B) 0/ 1.0 V to 1.0 Vp-p Operation Temperatures 15 to 35 C MU182040A 25 Gbit/s 1ch DEMUX Operating Bit Rate External Clock Input Input Frequency Input Data Input Input Signal Format Number of Input Input Threshold Voltage Input Sensitivity Phase Margin Termination 1/2 Data Output Number of output 1/2 Clock Output Number of output Variable Clock Delay Phase Variable Range Phase Setting Error Auto Search Function 2 Min. 0.4 Vp-p, Max. 1.2 Vp-p option-030 or 031 2,000 to +2,000 mui/steps: 2 mui Typ.50 muip-p 8 to 25 Gbit/s 8 to 28 Gbit/s (Installed option-001) 4.0 to 12.5 GHz 4.0 to 14.0 GHz (Installed option-001) 4.0 to 12.5 GHz, 8.0 to 25.0 GHz (Installed option-002) 4.0 to 14.0 GHz, 8.0 to 28.0 GHz (Installed option-001 and 002) 0.3 to 1.0 Vp-p K(f.) (Installed option-002) Single-ended/Differential selectable NRZ 2 (Data, xdata) 0.25 to 2.0 Vp-p 3.5 to +3.3 V/Steps: 1 mv Typ.50 mvp-p (25 Gbit/s, PRBS31) Typ.28 ps (25 Gbit/s, PRBS31) 50 Ω/GND, 50 Ω/Variable ( 2.5 to +3.5 V) K(f.) 2 (1/2 DataA, 1/2 DataB) 0/ 0.4 V 2 Min. 0.4 Vp-p, Max. 1.2 Vp-p option-030 or 031 2,000 to +2,000 mui/steps: 2 mui Typ.50 muip-p Enable Operation Temperatures 15 to 35 C

11 MU182021A 25 Gbit/s 2ch MUX Operating Bit Rate External Clock Input Input Frequency Input Data Output Setting Accuracy Offset Cross Point Adjust Tr/Tf Total Jitter Distortion (0-peak) Output On/Off Function Clock Output Offset Duty Output On/Off Function 1/2 Data Input Number of Input 1/2 Clock Input Number of Input 1/2 Clock Output Data Output Delay Phase Variable Range Phase Setting Error Skew between Data1 and 2 8 to 25 Gbit/s 8 to 28 Gbit/s (Installed option-001) 4.0 to 12.5 GHz 4.0 to 14.0 GHz (Installed option-001) 4.0 to 12.5 GHz, 8.0 to 25.0 GHz (Installed option-002) 4.0 to 14.0 GHz, 8.0 to 28.0 GHz (Installed option-001 and 002) 0.3 to 1.0 Vp-p K(f.) (Installed option-002) 4 (Data1, xdata1, Data2, xdata2) 0.25 to 1.75 Vp-p/Steps: 2 mv (Installed option-010) 0.5 to 2.5 Vp-p/Steps: 2 mv (Installed option-011) 0.5 to 3.5 Vp-p/Steps: 2 mv (Installed option-013) ±50 mv ±17% (Cross point 50% or 30 to 80%, 25 Gbit/s) 2.0 to +3.3 Voh/Steps: 1 mv 20 to 80%/Steps: 0.1% (25 Gbit/s) Typ.12 ps (20 to 80%) Typ.8 ps p-p Typ. ±25 mv ±10% (25 Gbit/s) K(f.) Enable * : The above specifications were measured with the oscilloscope, intrinsic jitter should be less than 200 fs (rms), and more than 70 GHz bandwidth. Output clock frequency is same of input clock frequency. 1 (Clock) 2 (Clock/xClock) (Installed option-021) Min. 0.3 Vp-p, Max. 1.0 Vp-p (Fixed) Min. 0.7 Vp-p, Max. 1.0 Vp-p (Fixed) (Installed option-002) 0.5 to 2.0 Vp-p/Steps: 2 mv (Installed option-021) 2.0 to +3.3 Voh/Steps: 1 mv (Installed option-021) 25 to +25/Steps: 1 (Installed option-021) K(f.) (Installed option-002 or 021) Enable (Installed option-002 or 021) 4 (1/2 Data1A, 1/2 Data1B, 1/2 Data2A, 1/2 Data2B) 0/ 1.0 V to 1.0 Vp-p 4 Min. 0.4 Vp-p, Max. 1.2 Vp-p option-030 or ,000 to +64,000 mui/steps: 2 mui Typ.50 muip-p Emphasis Control Operation Temperatures 15 to 35 C MU182041A 25 Gbit/s 2ch DEMUX Operating Bit Rate External Clock Input Input Frequency Input Enable (Installed option-040) 8 to 25 Gbit/s 8 to 28 Gbit/s (Installed option-001) 4.0 to 12.5 GHz 4.0 to 14.0 GHz (Installed option-001) 4.0 to 12.5 GHz, 8.0 to 25.0 GHz (Installed option-002) 4.0 to 14.0 GHz, 8.0 to 28.0 GHz (Installed option-001 and 002) 0.3 to 1.0 Vp-p K(f.) (Installed option-002) 11

12 Data Input Input Signal Format Number of Input Input Threshold Voltage Input Sensitivity Phase Margin Termination 1/2 Data Output 1/2 Clock Output Variable Clock Delay Phase Variable Range Phase Setting Error Auto Search Function Single-ended/Differential selectable NRZ 4 (Data1, xdata1, Data2, xdata2) 0.25 to 2.0 Vp-p 3.5 to +3.3 V/Steps: 1 mv Typ.50 mv (25 Gbit/s, PRBS31) Typ.28 ps (25 Gbit/s, PRBS31) 50 Ω/GND, 50 Ω/Variable ( 2.5 to +3.5 V) K(f.) 4 (1/2 Data1A, 1/2 Data1B, 1/2 Data2A, 1/2 Data2B) 0/ 0.4 V 4 Min. 0.4 Vp-p, Max. 1.2 Vp-p option-030 or 031 2,000 to +2,000 mui/steps: 2 mui Typ.50 muip-p Enable Operation Temperatures 15 to 35 C Catalog No. MP1800A_25G-E-A-1-(3.00) Printed in Japan PSD/CDT