Break Your SoC with Automatically Generated C Test Cases

Transcription

1 Break Your SoC with Automatically Generated C Test Cases Frederic Krampac Senior Applications Engineer Breker Verification Systems, Inc.

2 The Myths of SoC Verification The IPs are well verified the SoC will work The IPs, fabric and memory subsystem are well verified the entire flow will work Each IP works software will be able to stitch them together into use cases Power and clock management can be verified at the IP or subsystem level 2

3 The Truth of SoC Verification Schedules are tight, resources are limited Only limited chip-level verification is performed System bugs found by software team or customer Bus/fabric bandwidth is less than predicted Bus bridge hangs under stress Access by multiple IPs reveals address decode bug Memory fails on concurrent access to same bank Clocking change during execution hangs system 3

4 The SoC Verification Iceberg Connectivity Tests IP Integration Tests System Use Cases Concurrency Coherency System and Power Management Performance Verification 4

5 Digital Camera SoC Example Testbench SoC RTL CPU Memory Image Processor System and Power Control Camera Display SD Card 5

6 Manually Developed SoC Tests Connectivity Tests IP Integration Tests System Use Cases Concurrency Coherency System & Power Management Performance Verification test.c test.c Compiler Manual development and maintenance Difficult to manage: Multiple threads Multiple processors Multiple memories Interaction with I/O ports Testbench SoC RTL CPU Memory Image Processor Camera Display SD Card System and Power Control 6

7 TrekBox TrekSoC Automatic Self- Verifying C Test Cases Register / Memory Map Driver Scenarios Application Scenarios System Scenarios TrekSoC events.rc test.c test.c test.c Compiler Connectivity Tests IP Integration Tests System Use Cases Concurrency Coherency System & Power Management Performance Verification mailbox Testbench SoC RTL CPU Memory Image Processor Camera Display SD Card System and Power Control 7

8 TrekBox Scenario Model SoC IP Cam TrekSoC Automatic Self- Verifying C Test Cases TrekSoC test.c test.c SD events.rc test.c Compiler Connectivity Tests IP Integration Tests System Use Cases Concurrency Coherency System & Power Management Performance Verification mailbox Testbench SoC RTL CPU Memory Image Processor Camera Display SD Card System and Power Control 8

9 Scenario Model for Digital Camera: Data Flow Graph Display Display Image Processor Decode SD Card Read SD Card SD Card SD Card Write Image Processor Encode Camera CCD 9

10 Self-Verifying C Test Case // System Configuration void configure_system (void) { static U32 state = 1; switch(state) { case (0x1): active_threads = 4; // initialize thead counter WREG8(0x , 0x80); // UART_LCR: BREAK_CONTROL=0... WREG8(0x , 0x00); // UART_DIVISOR_MSB: MSB=0 WREG8(0x , 0x06); // UART_LCR: BREAK_CONTROL=0... WREG8(0x , 0x00); // UART_IER: MODEM_STATUS=0... WREG8(0x , 0x46); // UART_FCR: RX_FIFO_CLR= // Test Thread A void test_thread_a (void) { static U32 state = 0x1; switch(state) { case (0x1): trek_do_expect(6); // Begin Thread A state++; trek_do_expect(7); // Waiting for UART0_tx to be idle... case (0x2): if ( UART0_tx_busy == 1 ) break; UART0_tx_busy = 1; trek_do_expect(9); // Begin UART0 uart_fill_tx trek_write_fifo_mem8(0x , MADDR(0x ), 4); state++; trek_do_expect(10); // Poll for UART0.UART_LSR.TX_FIFO_EMPTY case (0x3): if (!REGTEST8(0x , 0x20, 0x20)) break; trek_do_expect(11); //... got UART0.UART_LSR.TX_FIFO_EMPTY state++; TrekSoC generates automatically from the scenario models Well commented Multi-threaded Multi-processor Does mean, nasty things to try to break the SoC Exercises deep corner cases 10

11 Multi-Threaded, Multi- Processor C Test Case 11

12 TrekSoC vs. Alternatives Why not SoC-level UVM? No testbench-cpu links Virtual sequencer too complex Full-chip simulation too slow Why not hand-written C tests? No testbench-cpu links Multi-threaded tests impossible to write by hand Why not just run production code? No testbench-cpu links Full-chip simulation even slower with CPU running code System Hookup IP Integration Multi-Master Concurrency Multi-CPU Interactions Data Ordering Cache Coherency Virtual Memory Clocks and Power Asynchronous Events Application Use Cases Performance Analysis Production is well-behaved and does not hit corner cases Production code is rarely available before SoC tape-out 12

13 Summary Standalone IP verification is not sufficient for an SoC TrekSoC automatically generates C test cases Run on the embedded processors and link to testbench Exercise deep corner cases and measure performance Scenario models are easy and natural to create Incremental ROI: basic tests require minimal information Graphs efficiently capture verification knowledge Graphs help internal communication and teams TrekSoC finds more bugs with 2-3x productivity gain 13

14 Thanks for Listening! 14