Will Everything Start To Look Like An SoC?

Transcription

1 Will Everything Start To Look Like An SoC? Vikas Gautam, Synopsys Verification Futures Conference 2013 Bangalore, India March 2013 Synopsys

2 SystemVerilog Inherits the Earth e erm SV urm AVM 1.0/2.0/3.0 OVM 1.0/2.0 UVM 1.0/1.1 UVM 1.2 SC SystemC TLM 1.0 SystemC TLM 2.0 SV VMM 1.0 VMM 1.1 VMM 1.2 OV RVM SystemVerilog and UVM are now mainstream Previous languages / methodologies will persist but new developments will be slow... and new users will be rare. Synopsys

3 Methodology Deployment Ecosystem Verification Planning Verification Management Coverage & Analysis Constraint Solver Protocol Debug Template Generators Native UVM VIP Synopsys UVM-Aware Debug UVM AMS Testbench UVM TLM/SC Adaptors

4 Will Everything Look Like an SoC? Mobile Low-power External Standards Graphics Processing Software Links to Analog System on Chip Performance/power Optimisation Internal and External Standards Links to Analog Multiple Processors Multiple Protocols Software Processor High-performance Internal Architecture Data Processing Software SoC-targeted Tool Developments Will Benefit ALL chip Designs Automotive Industrial Aerospace Medical Military Infrastructure Scientific Synopsys

5 Significant Challenges Remain Convergence Driving SoC Complexity PC + Mobile Increasing HW Functionality 10X Increase In Verification Complexity 10X Increase Needed in Productivity Platform Convergence CPU + Graphics + Modem Multimedia + Networking Today s Verification Complexity Needs Accelerated Innovation Increasing complexity of specs Shrinking time to market Exploding SW content Increasing development cost 44M+ lines of RTL & Testbench 168GB+ memory required 10+ protocols TB of coverage data 300,000+ assertions 200+ power domains Debug 35% of verification 2:1 verif/design engineers 2X CPU farm 10x Performance 10x Capacity 10x VIP Productivity 10x Constraints & Coverage Advanced LP solutions High-speed AMS Simulation 10x Debug Productivity 10x Reuse methodology Hw/Sw Co-Verification Synopsys

6 10x Performance, 10x Capacity Massive Parallelism Many designs have repeated structures Many tests are run on the same DUT Can we automatically utilise this in order to increase performance? New Compute Platforms Are CPUs the best simulation platform? Can we use FPGAs for acceleration? SIMD, Single-Instruction-Multiple-Data What of other computing platforms? Employ GPU via OPENCL compilers? Cloud-based simulation? Synopsys

7 VIP Productivity Challenge More protocols in use per chip, each protocol evolving Synopsys

8 VIP Productivity Challenge A small step in for a protocol can be a giant leap in complexity. SDIO I2C PCI AMBA AHB UART USB2.0 AMBA APB MMC-SD 10X Protocols USB 2.0 Traffic Increasing complexity per protocol (20x scenarios, 10x data) USB 3.0 Traffic AMBA4 AXI HDMI USB OTG I2C SATA HDMI AMBA4 ACE UART PCIe MIPI DSI HDMI USB2.0 SDIO USB3.0 MMC-SD MIPI CSI SLIM Bus MIPI LLI GPIO MIPI HSI USB 3.0 Synopsys

9 Today s VIP Productivity Challenges Current VIP technology running out of steam OVM SV Interface erm e UVM VMM OVM SV Interface Vera VMM UVM OVM SV Interface C e and C based VIP Vera-based VIP UVM Configuration & Test Development 20x increase in scenarios 2-4 weeks before the first test Performance 3M+ lines of VIP code per SOC Multiple layers of PLI wrappers Debug Several days to find root cause, due to limited visibility Current debug tools not protocol-aware Coverage Closure 2 man-months to create coverage plan per title 3 man-months to implement coverage and scenarios Synopsys

10 Protocol L2 Link L1 Physical Driver Sequencer Configuration VIP Moves to SystemVerilog 20+ Industry Experts collaborated on Requirements and Architecture 100% SystemVerilog High Performance Ease of Use Native Methodology Support Customization Coverage Sequence Collections Sequence Collection Configuration Creator User Verification Plan Built-in Coverage Testbench Native SystemVerilog Protocol VIP Protocol Test Plan Coverage Database Built-in Verification Plans Protocol Aware Debug User Tests Debug Virtual Sequencer Test Suite Protocol Analyzer DUT Monitor Coverage Model AIP VIP Source Visibility DVE Native UVM / VMM / OVM Synopsys

11 Analyze 10x Constraints and Coverage Efficiency Plan Trend analysis Grading Exclusions Interactive authoring Annotation Verification & Coverage Data Integrated execution Regression monitoring Manage Synopsys

12 Advanced Low-Power Solutions VCS-NLP provides a unique voltage-aware modeling engine combined with industry leading native compiled-code simulation 50% faster and higher capacity than non-native mode Minimal runtime impact vs. non-lp simulation Ease-of-use Supports industry-standard IEEE 1801 (UPF) Leverages VCS use model including testbench, coverage, and debug Single compile step All VCS command line options supported Ease-of-debug Enhanced low power debug Synopsys

13 10x Debug Productivity Methodology-aware Debug Supports VMM-UVM-OVM Windows for: Class Object Resource Factory Phase Sequence Protocol-aware Debug Transaction Recording Verdi Debug Transactions Handshaking Transcript Synopsys

14 Earliest Detection of Bugs Abstracted Static Equivalence Checking X-Propagation prediction at RTL How Can The Industry Deliver These Advances and Beyond? Synopsys

15 Partnership with Industry Leaders VCS customer spotlights on EE Times: Synopsys

16 Synopsys Thank You