20. Paging: Smaller Tables

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Clyde Morrison
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1 20. Paging: Smaller Tables Oerating System: Three Easy Pieces 1

2 Paging: Linear Tables We usually have one age table for every rocess in the system. w Assume that 32-bit address sace with 4KB ages and 4-byte age-table entry. 4B entry entry entry 4KB Page 0 Page 1 Page 2 entry Page n Page Table of Process A Physical Memory Page table size =!"!!#! %&'() = %+&,-. Page tables are too big and thus consume too much memory. AOS@UC 2

3 Paging: Smaller Tables Page table are too big and thus consume too much memory. w Assume that 32-bit address sace with 16KB ages and 4-byte age-table entry. 4B entry entry entry 16KB Page 0 Page 1 Page 2 entry Page n Page Table of Process A Physical Memory! "!! #$ & = #() er age table But big ages might lead to internal fragmentation. AOS@UC 3

4 The Problem Single age table for the entries address sace of rocess. Virtual Address Sace code hea stack Allocate Physical Memory A 16KB Address Sace with 1KB Pages PFN valid rot resent dirty 10 1 r-x rw rw rw- 1 1 A Page Table For 16KB Address Sace AOS@UC 4

5 The Problem Most of the age table is unused, full of invalid entries. Virtual Address Sace code 0 hea stack Allocate Physical Memory A 16KB Address Sace with 1KB Pages PFN valid rot resent dirty 10 1 r-x rw rw rw- 1 1 A Page Table For 16KB Address Sace AOS@UC 5

6 Hybrid Aroach to the Problem: Paging and Segments In order to reduce the memory overhead of age tables. w Using base not to oint to the segment itself but rather to hold the hysical address of the age table of that segment. w The bounds register is used to indicate the end of the age table. AOS@UC 6

7 Simle Examle of Hybrid Aroach Each rocess has three age tables associated with it. w When rocess is running, the base register for each of these segments contains the hysical address of a linear age table for that segment Seg VPN Offset 32-bit Virtual address sace with 4KB ages Seg value Content 00 unused segment 01 code 10 hea 11 stack AOS@UC 7

8 TLB miss on Hybrid Aroach The hardware get to hysical address from age table. w The hardware uses the segment bits(sn) to determine which base and bounds air to use. w The hardware then takes the hysical address therein and combines it with the VPN as follows to form the address of the age table entry(pte). 01: SN = (VirtualAddress & SEG_MASK) >> SN_SHIFT 02: VPN = (VirtualAddress & VPN_MASK) >> VPN_SHIFT 03: AddressOfPTE = Base[SN] + (VPN * sizeof(pte)) AOS@UC 8

9 Problem of Hybrid Aroach Hybrid Aroach inherits Segmentation issues w If we have a large but sarsely-used hea, we can still end u with a lot of age table waste (most of the free sace should be tracked) w Causing external fragmentation to arise again w Page Tables have arbitrary size: it s hard to find sace for them (or handle it dynamically) AOS@UC 9

10 Multi-level Page Tables Turns the linear age table into something like a tree. w Cho u the age table into age-sized units. w If an entire age of age-table entries is invalid, don t allocate that age of the age table at all. w To track whether a age of the age table is valid, use a new structure, called age directory. AOS@UC 10

11 Multi-level Page Tables: Page directory Linear Page Table Multi-level Page Table PTBR 201 PBTR 200 valid rot PFN 1 rx 12 1 rx 13 1 rw rw 86 1 rw 15 PFN 204 PFN 203 PFN 202 PFN 201 PFN200 valid PFN The Page Directory valid rot PFN 1 rx 12 1 rx 13 1 rw 100 PFN201 [Page 1 of PT:Not Allocated] [Page 2 of PT: Not Allocated] 1 rw 86 1 rw 15 PFN204 Linear (Left) And Multi-Level (Right) Page Tables AOS@UC 11

12 Multi-level Page Tables: Page directory entries The age directory contains one entry er age of the age table. w It consists of a number of age directory entries (PDE). PDE (minimaly) has a valid bit and age frame number (PFN). AOS@UC 12

13 Multi-level Page Tables: Advantage & Disadvantage Advantage w Only allocates age-table sace in roortion to the amount of address sace you are using. w The OS can grab the next free age when it needs to allocate or grow a age table. Disadvantage w Multi-level table is a small examle of a time-sace trade-off. w Comlexity. AOS@UC 13

14 A Detailed Multi-Level Examle To understand the idea behind multi-level age tables better, let s do an examle code code (free) (free) hea hea (free) (free) stack stack Flag Detail Address sace 16 KB Page size 64 byte Virtual address 14 bit VPN 8 bit Offset 6 bit # Page table entry 2 " (256) A 16-KB Address Sace With 64-byte Pages VPN Offset AOS@UC 14

15 A Detailed Multi-Level Examle: Page Directory Idx The age directory needs one entry er age of the age table w it has 16 entries. The PDE is invalid à Raise an excetion (The access is invalid) Page Directory Index VPN 14-bits Virtual address Offset AOS@UC 15

16 A Detailed Multi-Level Examle: Page Table Idx The PDE is valid, we have more work to do. w To fetch the age table entry(pte) from the age of the age table ointed to by this age-directory entry. This age-table index can then be used to index into the age table itself. Page Directory Index Page Table Index VPN 14-bits Virtual address Offset AOS@UC 16

17 Examle 17

18 More than Two Level In some cases, a deeer tree is ossible (and needed) VPN offset Flag Virtual address Page size VPN Offset Detail 30 bit 512 byte 21 bit 9 bit AOS@UC 18

19 More than Two Level : Page Table Index In some cases, a deeer tree is ossible (and needed) Page Directory Index Page Table Index VPN offset Flag Virtual address Page size VPN Offset Page entry er age Detail 30 bit 512 byte 21 bit 9 bit 128 PTEs log $ 128 = 7 4bytes er PTE AOS@UC 19

20 More than Two Level : Page Directory Within a Page If our age directory has 2 "# entries, it sans not one age but 128 assuming size_of(pde) == size_of(pte) To remedy this roblem, we build a further level of the tree, by slitting the age directory itself into multile ages of the age directory PD Index 0 PD Index 1 Page Table Index VPN offset AOS@UC 20

21 Multi-level Page Table Control Flow 01: VPN = (VirtualAddress & VPN_MASK) >> SHIFT 02: (Success,TlbEntry) = TLB_Looku(VPN) 03: if(success == True) //TLB Hit 04: if(canaccess(tlbentry.protectbits) == True) 05: Offset = VirtualAddress & OFFSET_MASK 06: PhysAddr = (TlbEntry.PFN << SHIFT) Offset 07: Register = AccessMemory(PhysAddr) 08: else RaiseExcetion(PROTECTION_FAULT); 09: else // erform the full multi-level looku w (1 lines) extract the virtual age number(vpn) w (2 lines) check if the TLB holds the translation for this VPN w (5-8 lines) extract the age frame number from the relevant TLB entry, and form the desired hysical address and access memory AOS@UC 21

22 Multi-level Page Table Control Flow 11: else 12: PDIndex = (VPN & PD_MASK) >> PD_SHIFT 13: PDEAddr = PDBR + (PDIndex * sizeof(pde)) 14: PDE = AccessMemory(PDEAddr) 15: if(pde.valid == False) 16: RaiseExcetion(SEGMENTATION_FAULT) 17: else // PDE is Valid: now fetch PTE from PT w (11 lines) extract the Page Directory Index(PDIndex) w (13 lines) get Page Directory Entry(PDE) w (15-17 lines) Check PDE valid flag. If valid flag is true, fetch Page Table entry from Page Table AOS@UC 22

23 The Translation Process: Remember the TLB 18: PTIndex = (VPN & PT_MASK) >> PT_SHIFT 19: PTEAddr = (PDE.PFN << SHIFT) + (PTIndex * sizeof(pte)) 20: PTE = AccessMemory(PTEAddr) 21: if(pte.valid == False) 22: RaiseExcetion(SEGMENTATION_FAULT) 23: else if(canaccess(pte.protectbits) == False) 24: RaiseExcetion(PROTECTION_FAULT); 25: else 26: TLB_Insert(VPN, PTE.PFN, PTE.ProtectBits) 27: RetryInstruction() AOS@UC 23

24 Inverted Page Table Keeing a single age table that has an entry for each hysical age of the system. The entry tells us which rocess is using this age, and which virtual age of that rocess mas to this hysical age. Used with a hashing table (hash anchor table) in order to allow ractical imlementations AOS@UC 24

25 x86-64: today 4 levels(256tb), lanned 5 (128 PB) L4 L3 L2 L1 AOS@UC 25

26 Disclaimer: This lecture slide has been adated for AOS course at University of Cantabria by V.Puente. Was initially develoed for Oerating System course in Comuter Science Det. at Hanyang University. This lecture slide set is for OSTEP book written by Remzi and Andrea Araci-Dusseau (at University of Wisconsin) 26

Paging: Smaller Tables

20 Paging: Smaller Tables We now tackle the second problem that paging introduces: page tables are too big and thus consume too much memory. Let s start out with a linear page table. As you might recall