Virtual Memory. Yannis Smaragdakis, U. Athens

Transcription

1 Virtual Memory Yannis Smaragdakis, U. Athens

2 Example Modern Address Space (64-bit Linux) location of code : 0x40057d location of heap : 0xcf2010 location of stack : 0x7fff9ca45fcc 0x x xcf2000 0xd13000 Address Space Code (Text) Data Heap heap (free) stack 0x7fffca x7fffca4f000 Stack 2

3 (Sample) Memory Hierarchy Chassis 1 kbyte registers CPU Motherboard 100 kbyte 1 nsec Level-1 cache 1 Mbyte Level-2 cache Cache 1 Gbyte 10 nsec RAM (+ROM) Main/internal memory 1 Tbyte 1 10 msec 10 sec hard disk Removable storage (tapes, CD, DVD, ) External (out-of-core) memory 3

4 Questions Which addresses are physical, which virtual? what happens with multiple processes? who translates addresses? Why do caches work well? (locality!) How do you get more stack memory? More heap memory? How do you return it? What do you think the OS does? What system calls? man mmap, man sbrk 4

5 How Do Addresses Get Translated? Several older techniques: base and bounds registers segmentation with hw support, on x86 segmentation fault message? Modern technique: paging also on xv6 5

6 Paging Translate addresses at page granularity addr = virtual page num (VPN) + offset Keep directory of page mappings VPN ofset Va5 Va4 Va3 Va2 Va1 Va0 6

7 Page Tables A directory of page addresses page table entry: may include other info valid, protected, present, dirty, recently-accessed bit What data structures can you imagine? What's the space overhead of each? 7

8 Translation Logic (pseudocode) 1 // Extract the VPN from the virtual address 2 VPN = (VirtualAddress & VPN_MASK) >> SHIFT 3 4 // Form the address of the page-table entry (PTE) 5 PTEAddr = PTBR + (VPN * sizeof(pte)) 6 7 // Fetch the PTE 8 PTE = AccessMemory(PTEAddr) 9 10 // Check if process can access the page 11 if (PTE.Valid == False) 12 RaiseException(SEGMENTATION_FAULT) 13 else if (CanAccess(PTE.ProtectBits) == False) 14 RaiseException(PROTECTION_FAULT) 15 else 16 // Access is OK: form physical address and fetch it 17 offset = VirtualAddress & OFFSET_MASK 18 PhysAddr = (PTE.PFN << PFN_SHIFT) offset 19 Register = AccessMemory(PhysAddr) What is the time overhead? 8

9 Minimizing Space Overhead Most of a flat table would be unused code heap stack Virtual Address f Allocate Physical Memory f f Space PFN valid prot present dirty f 1 r-x rw rw rw

10 Solution: 2-level Page Tables Page Table RAM x y z CR3 Page Directory T[x,y,z] = CR3[x][y] + z 10

11 Let's Get Some Numbers bits = 32 2^10 (= 1024) entries of 4 bytes = a 4096-byte page! 2-level tables work well for 32-bit machines 64-bit machines use a 3-level table! We save space, but we could do the same with other associative structures, right? Need to jointly solve time overhead! 11

12 Minimizing Time Overhead Hardware to the rescue Translation Lookaside Buffer (TLB) a cache of recent page address lookups exploits spatial, temporal locality, like all caches a few tens of entries, fully associative (optional) Hardware-traversal of page tables when TLB lookup fails hardware-managed TLB common on CISC machines software-managed TLB on RISC machines interrupt, handled by kernel 12

13 TLB Schematically A cache on the chip's memory-management unit (MMU) Logical Address CPU TLB Lookup MMU TLB popular v to p TLB Miss Page Table all v to p entries TLB Hit Address Translation with MMU Physical Address Page 0 Page 1 Page 2 Page n Physical Memory 13

14 What Happens to TLB When Switching Processes? Typically entries have address space id (ASID) LRU replacement otherwise Other options? Shared parts of address space? 14

15 Time for a New Problem: What If Physical Memory Gets Full? Idea: replace a page to make room much like any other cache disk used as larger memory recall memory hierarchy picture also called eviction Policy vs mechanism distinction with algorithm in the middle 15

16 Mechanisms Swap space (file, partition) present bit in PTE Page fault when accessed page not present Page replacement algorithm implements/approximates a replacement policy Terminology: page in/page out in: just mmap swap file page!? out: only if page has dirty/modified bit on Terminology: paging, thrashing 16

17 Replacement Policies: OPT Ideal replacement policy: replace page that will be accessed the furthest in the future policy called OPT or MIN optimal (provably) but requires knowing the future 17

18 Other Replacement Policies FIFO memories too large for it to work well, misses all behavior RANDOM LRU (Least Recently Used) the golden standard of caching, uses history of accesses LFU (Least Frequently Used) bad for programs, good for data streams 18

19 Approximating LRU The policy requires work per memory access Approximation algorithms minimize the overhead Clock: uses recently-referenced bit, resets it FIFO/LRU hybrid queue: FIFO for some pages, then move-to-front for those evicted from FIFO 19

20 Clock G H F A E B D C Use bit Meaning 0 Evict the page 1 Clear Use bit and advance hand The Clock page replacement algorithm When a page fault occurs, the page the hand is pointing to is inspected. The action taken depends on the Use bit 20

21 Other Interesting Tidbits Virtual memory is only a part of memory! explicit I/O and mmapped file contents treated the same replaced in unified way, typically remember LFU policy? Replacement only a part of the performance story prefetching clustering writes more in file systems 21