A Memory Grouping Method for Sharing Memory BIST Logic

Transcription

1 A Memory Grouping Method for Sharing Memory BIST Logic Masahide Miyazai, Tomoazu Yoneda, and Hideo Fuiwara Graduate Schoo of Information Science, Nara Institute of Science and Technoogy (NAIST), Taayama, Ioma, Nara , Japan Emai:{masah-mi, Yoneda, Abstract - With the increasing demand for SoCs to incude rich functionaity, SoCs are being designed with hundreds of sma memories with different sizes and frequencies. If memory BIST ogics were individuay added to these various memories, the area overhead woud be very high. To reduce the overhead, memory BIST ogic must therefore be shared. This paper proposes a memory-grouping method for memory BIST ogic sharing. A memory-grouping probem is formuated and an agorithm to sove the probem is proposed. Experimenta resuts showed that the proposed method reduced the area of the memory BIST wrapper by up to 40.55%. The resuts aso showed that the abiity to seect from two types of connection methods produced a greater reduction in area than using a singe connection method. I. Introduction With the increasing number of functions being incuded in SoCs, many memories with different sizes and frequencies are being used. The atest SoCs contain hundreds of memories. Testing a the memories in these SoCs sequentiay woud tae a ong time. Therefore, a memory BIST design that aows two or more memories to be tested simutaneousy is needed. However, due to power-consumption constraints, not a memories can be activated at the same time. To sove this probem, a scheduing technique for minimizing the test appication time under power-consumption constraints is needed. Adding individua circuits for memory BISTs to ots of sma memories woud resut in huge area overheads. To reduce these overheads, memory BIST ogic must be abe to be shared. A BIST architecture, based on a singe micro-programmabe BIST processor and a set of memory wrappers, was proposed to simpify the testing of systems containing many distributed SRAMs of different sizes [1]. To reduce the BIST area overhead, it was proposed to share a singe wrapper between a custer of SRAMs (same type, width, and addressing space). However, in some cases, memories that have different widths or addressing spaces can be connected and share BIST ogic. There can aso be two or more connection methods. To achieve a satisfactory soution, the memory-connection type shoud be considered aong with decisions on memory groups. In this paper, we propose two types of memory-connection methods for BIST wrapper sharing. A memory-grouping probem for test circuit minimization under constraints of power consumption and test appication time is aso formuated together with an agorithm that soves the probem. In addition, the effectiveness of this technique is demonstrated experimentay. This paper is organized as foows. In section II, our method for memory BIST ogic sharing is described. In section III, the memory-grouping probem and an agorithm to sove the probem are presented. The experimenta resuts are shown in section IV. II. Memory BIST Logic sharing In this section, we describe our method of BIST ogic sharing for singe port and word access memory. Figure 1 shows an exampe of a memory BIST wrapper. The data generator generates input test sequences. The address generator generates read and write addresses and the response anayzer captures test output responses and detects fauts. The by-pass FFs are not used to test memory, but are used to care the memory interface signa during a scan test. The area of the address generator, data generator, and response anayzer are amost proportiona to the bit width of the address, input data, and output data, respectivey. However, some of these ogics can be shared by different memories wherever the number of words or the data bit width are the same; hence, the area of test circuits can be reduced. In this paper, we treat the foowing two memory connection methods for memory BIST ogic sharing: parae connection and seria connection. Parae connection can be used to connect memories that have the same number of words. Figure shows an exampe of parae connection. In this exampe, three data and address generators are reduced to one by distributing the same test data and address signas from a coupe of data and address generators to (1) - (4), enabing four memories to be tested simutaneousy.

2 Fig.1 Memory BIST Wrapper Fig.3 Seria connection of memories III. Memory-Grouping Probem and Agorithm A. Formuation of Memory-Grouping Probem Fig. Parae connection of memories Seria connection aows memories with the same bit width to be connected. Figure 3 shows an exampe of four seriay connected 8x3 word memories. In this exampe, the four memories are tested as an 8x18 word memory. The address generator generates an additiona bit signa, and the signa is used to seect the memories from (1) - (4), enabing the four memories to be tested seriay. If a the memories have individua BIST ogic, a 3-bit data generator and response anayzer are required, but in this exampe, a the memories can be tested using a shared 8bit generator and 8bit response anayzer. Seria connection reduces the area more than parae connection and aso uses ess power than parae connection. However, the time required for seria connection testing is onger than that for parae connection testing. To achieve the minimum area and a reasonabe test appication time under power consumption constraints, the type of memory connection shoud be considered during decisions on memory grouping. The ayout design must aso tae into account distance constraints in reation to these connections. In this subsection, we present a memory-grouping probem. We assume that the foowing information for each memory mi is given: - b i : data bit width of m i -w i : word depth of m i - p i : maximum power consumption of testing m i - f i : operating frequency of m i -x i : X coordinate of m i, y i : Y coordinate of m i We define two types of compatibiity, namey p-compatibiity and s-compatibiity, as foows: Given a set of memories V={m 1, m, m n }, a pair of memories m i, m V is p-compatibe if they satisfy the foowing conditions: w i =w (1) f i =f () ( xi x ) ( yi y ) <D (3) D is a constraint vaue that the designer decides according to the design condition. P-compatibiity is represented by a graph G p = (V, E p ), where V is a set of a memory and the edge between a pair of vertices (m i, m )E p exists if m i and m are p-compatibe. If a set of memories can be connected in parae, the graph induced on G p by the memories has to be a cique. In the same way, a pair of memories m i, m V is s-compatibe if they satisfy the foowing conditions: b i =b (4) f i =f (5)

3 ( xi x ) ( yi y ) <D (6) S-compatibiity is represented by a graph G s = (V, E s ), where V is a set of memories and the edge between a pair of vertices (m i, m ).E s exists if m i and m are s-compatibe. If a set of memories can be connected seriay, the graph induced on G s by the memories has to be a cique. To design memory BIST wrappers using these techniques for memory BIST ogic sharing, we have to find a partition of V such that the memories that share the wrapper are incuded in the same boc. Moreover, the partition =B 1, B,... B has to satisfy the foowing conditions: G ip is the graph induced on G p by boc B i. G is is the graph induced on G s by boc B i. G ip or G is is a cique. When ony the graph G ip (G is ) is a cique, the memories incuded in B i are connected in parae (seriay). If G ip and G is are both cique, we have to seect the type of connection. For a partition, we can cacuate the area of the BIST wrapper, test appication time, and power consumption of each boc. The area and test appication time depend on the test-pattern agorithm. In this wor, these were cacuated according to a pubished design [4] using an 8N agorithm as foows. If the connection type of boc B i ={m 1, m, m } is a parae connection, Area S = 0.75 og w og w 18 3maxb 66 5og w (7) i p 1 Power consumption P = (8) 8 w / Test appication time T = (9) (f =f 1 =f =...=f ) f If the connection type of boc B ={m 1, m, m } is a seria connection, Area S B = 0.75 og w og wi 1 1 5og wi og 9b 14b (10) (b =b 1 =b =...=b ) Power consumption P B = max p (11) 1 b Test appication time T B = 8 w / f 1 (number of bacground patterns) (1) The expressions for area cacuation (7) and (10) do not consider the infuence of timing conditions, but feedbac is avaiabe from previous designs. Parae-connected memories are tested concurrenty, and the power consumption is the sum of the power consumption of each memory. In contrast, seria-connected memories are activated one by one. Therefore, the power consumption is the maximum power consumption of the connected memories. When a partition is found, the area, power consumption and test appication time of each boc are cacuated using the above expression. The tota area of the memory BIST wrappers S tota is cacuated as the sum of S. S tota S i1 B (13) To contro each memory BIST wrapper, at east one BIST controer must be used. In this study, the number of memory BIST wrappers was reduced by using the proposed connections. There was therefore no increase in the number of controers. In addition, our target design incudes a ot of memories so that the area of the memory BIST wrappers is predominant. Therefore the area of the BIST controers is disregarded. To cacuate the tota test appication time of a memory BIST under a power-consumption constraint, we used a rectange pacing agorithm that has been described esewhere [5]. The agorithm optimizes the test schedue of each core so that the tota test appication time of an SoC is minimized under maximum power constraints. The inputs of the scheduing agorithm are the maximum aowed power consumption, the test appication time, and the power consumption of each core. In this study, we considered a boc to be a core. Therefore, we input {P B } {T B } as the information for each core. In addition, we assumed the bit width of the inter-connect between each wrapper and contro ogic remained unchanged. We therefore disregarded the maximum TAM width. To reduce the tota area of memory BIST wrappers by memory BIST ogic sharing, we formuated the foowing memory-grouping probem. Inputs: a) A set of memories S and Information for each memory: M=M i (b i, w i, p i, f i, x i y i ) where, b i, w i, p i, f i, x i and y i are as foows: b i : data bit width of m i w i : word depth of m i p i : maximum power consumption of testing m i f i : frequency of m i x i : X coordinate of m i

4 y i : Y coordinate of m i Outputs: a) A partition of a given set of memories S for which a the bocs satisfy the foowing conditions: G ip is the graph induced on G p by boc B i. G is is the graph induced on G s by boc B i. G ip or G is is a cique. b) Type of connection of each boc c) Test schedue of each memory Constraints: a) Maximum distance of memory connection: D b) Maximum avaiabe pea power of the SoC: P c) Maximum test appication time of memory: T Obective: To minimize S tota. To sove this probem, an agorithm is proposed beow. B. Memory Grouping Agorithm Fig.4 shows the pseudo code of the Memory Grouping Agorithm. Our proposed agorithm repeats division from 0-partition that ony one boc incudes a memory to obtaining a target partition. As the agorithm divides the boc, S tota increases. The min-cut method [][3] is used to eave the possibiity of the area reduction as much as possibe. Moreover, it uses the foowing strategies to decide the compatibiity of each boc of the partition. Seria connection can reduce the area than parae connection, and the power consumption is smaer than that of parae connection. Therefore, it is possibe that giving priority to seria connection reduces S tota. Based on this prospect, proposed agorithm searches for the partition that minimizes S tota ony using s-compatibiity in the first search. First, the agorithm initiaizes variabes. The minimum vaue of S tota is stored into S min, and, in the first step, S min is set to the tota area of memory BIST wrapper without sharing. The partition of a set of memory S is stored into, and the initia partition is set to 0-partition of S. (ine 1-). Next, the agorithm creates two compatibiity graphs (ine 3), and seect s-compatibiity graph as the graph G that is used to find partition (ine 4). In order to chec the compatibiity of each boc, the agorithm construct a set of graph C a (ine 6). Each graph G i that is the member of C a is induced on G by boc B i that is the member of. Then, for a B i that incude two or more memories, execute the foowing operations (ine 7-1). The minimum cut edge is cacuated and deete them from G i. By this operation, the vertex set B i is divided into two bocs, eaving much possibiity of the area reduction. If a the graph of new graph set C a are cique, cacuate S tota and test schedue of the new partition. If S min >S tota and the test scheduing succeeded, is stored into best as the best partition, and S tota is stored into S min (ine 8-17). If there is a graph G i that is not a cique, or the test scheduing faied, is stored into (ine 18-0). If there is no partition that shoud be tried, the first search is end (ine-4). Then the agorithm stores p-compatibiity graph into G, and coects the bocs that have ony one memory into one boc (ine5-9). Then, the agorithm searches for the partition that S tota is minimized using p-compatibiity (ine5-4). In the second search, it doesn t touch the bocs in which two or more memories are incuded after first search. Their connection type is fixed to seria connection. The connection type of the rest is determined to be parae connection. This agorithm performs n(n-1) times division and scheduing in the worst case. The compexity of the scheduing agorithm and min-cut agorithm are O(VogV) and O(V ogv), respectivey. Therefore the compexity of this agorithm is O(V 3 ogv). In this paper, we described our method for a singe port and the word access memory. However, this method is appicabe to other memories if the compatibiity is defined about the memory type and the connecting method, and the area, power consumption, test appication time can be shown by expression. IV. Experimenta Resuts We carried out experiments to evauate the proposed method. The proposed agorithm was impemented in C and the experiments were conducted on a 600-MHz Windows PC. Tabe 1 shows the information in each memory used in the experiment. The -4th coumns denote the data bit width, word depth, and operating frequencies, respectivey. The 5th coumn shows the power consumption. In this experiment, the power consumption of each memory was a reative vaue in which memory No. 1 was assumed to be 100 under the foowing assumption: a) The area is proportiona to (number of words number of bits). b) The power consumption is proportiona to the area. c) The power consumption is proportiona to the frequency. Tabe1. Information on Memories *1 Reative vaues in which memory No.1 is assumed to be 100

5 Procedure Memory_Grouping (M, P, T, D){ 1 S min = the tota area of memory BIST wrapper without sharing; maxedgenum=0; edgenum=0; ={B}, B={m 1, m, m n }; ; ; best ; s compatibe ; 3 G s = s-compatibiity_graph of B; G p = p-compatibiity_graph of B; 4 G = G s ; 5 oop: 6 Construct a set of graph C a ={ G i G i is induced graph on G by B i } 7 for( {B i ( s ) which incudes two or more memories}){ compatibe 8 deete min-cut edge from G i, mae a set of graph C min ={G i1,g i }; 9 C a = (C a - G i ) C min ; 10 Set edgenum= (the number of edges of G C a ); 11 Set a partition ={B vertex set of G C a };if a G are cique,cacuate S tota of 1 if(( G C, G a is cique ) (S min >S tota of )){ 13 cacuate T tota =Schedue(P, {P B }, {T B }); 14 if((schedue succeeded) (T tota T)){ 15 S min = S tota ; = best ; 16 } 17 } 18 if(edgenum > maxedgenum ((Schedue faied, or T tota T) ( G C, G a is not a cique))){ 19 = ; maxedgenum=edgenum; 0 } 1 } if( ){ 3 = ; ; go to oop; 4 } 5 ese if(g=g s ){ 6 G = G p ; 7 ={ scompatibe B which incudes two or more memories }; best 8 B s = B (B ( best )); scompatibe 9 ={B s } ; go to oop; scompatibe 30 }ese{end;} Fig.4 Memory Grouping Agorithm The 6th and 7th coumns show ocation. In this experiment, the number of memories was varied between 3 and 50, and the program was executed respectivey. When the number of memories was N<11, we used No. 1 to N, and for the rest, we extended the same set of No. 1-10, with the Y coordinate changing between 0 to 50. In an actua test, severa bacground patterns (e.g. marching, checer, checer-bar) are used, but in this experiment, the test appication time was cacuated by assuming the number of bacground patterns=1. In addition, the foowing constraint vaues were used: Maximum distance of memory connection: D=40 Maximum avaiabe pea power of the SoC: P=5000 Maximum test appication time of memory: T=300 s Experiments were carried out for the foowing five cases: (1) Not shared (a the memories had individua BIST wrappers); () parae connection (memory BIST ogic was shared using ony parae connection as described in the proposed technique); (3) seria connection (memory BIST ogic was shared using ony seria connection as described in the proposed technique); (4) parae and seria connection (memory BIST ogic was shared using both parae and seria connection as described in the proposed technique); and (5) exhaustive search (memory BIST ogic was shared using ony parae connection after an exhaustive search). Tabe shows the experimenta resuts. The first coumn

6 shows the number of memories and the second coumn shows the tota area of memory BIST wrappers without sharing. Coumns 3-5 shows the tota area of memory BIST wrappers using the proposed techniques. The third coumn shows the resuts of using ony parae connection, whie the fourth coumn shows the resuts of using ony seria connection. The fifth coumn shows the resuts of using both parae and seria connection and the sixth coumn shows the minimum soution obtained using an exhaustive search. We were ony abe to compete an exhaustive search when the number of memories was ess than 7. In these cases, the resuts of the exhaustive search showed that the memory BIST ogic sharing technique reduced the area of the BIST wrappers by between 1.59 and 47.83% as minimum soutions. However, the technique achieved ony 64.45% of the minimum soution in these cases, so there is room for improving the quaity of the soution. The average reduction ratio for parae connection, seria connection, and parae and seria connection were 1.08%, 37.5%, and 40.55%, respectivey. In a cases, parae and seria connection achieved the best soution. This resut demonstrates that seection from two types of connection methods reduces the area more than using a singe connection method. Finay, Figure 5 shows the execution time of the impemented memory-grouping program. In a cases, the program was executed within 10 seconds using the proposed agorithm. The technique thus obtained good resuts within a very short CPU time so it is suitabe for practica appication. Tabe. Area of Memory-BIST Logic Fig.5 CPU Time of Memory Grouping program V. Summary and Concusions A memory grouping probem was formuated and an agorithm to sove the probem was proposed. Experimenta resuts showed that the proposed method reduced the area of memory BIST wrappers by up to 40.55%. It was aso shown that the abiity to seect from two types of connection methods reduced the area more than using a singe connection method. In future wor we wi investigate improving the quaity of the soution and minimizing the test appication time. Acnowedgements Authors woud ie to than Prof. Michio Inoue and Prof. Satoshi Ohtae and members of Computer Design and Test Lab. (Nara Institute of Science and Technoogy) for their vauabe discussions. References [1] A.Benso, S.Di Caro, G. Di Natae and P. Prinetto, A Programmabe BIST Architecture for Custers of Mutipe-Port SRAMs, in Proc. Internationa Test Conf., pp , October 000. [] H. Nagamochi and T. Ibarai, A inear-time agorithm for finding a sparse -connected spanning subgraph of a -connected graph, Agorithmica, vo. 7, 199, pp [3] H. Nagamochi and T. Ibarai, Computing the edge-connectivity of mutigraphs and capacitated graphs, SIAM J. Discrete Mathematics, vo. 5, 199, pp [4]Chares E. Stroud, A Designer s Guide to Buit-In Sef-Test, Kuwer Academic Pubishers, The Netherands, 00. [5]V. Iyengar, K. Charabarty and E. J. Marinissen, On using rectange pacaging for SOC wrapper/tam co-optimization, in Proc. VLSI Test Symposium, pp , May 00. [6]Y. Huang, N. Muheree, S. Reddy, C. Tsai, W. Cheng, O. Samman, P. Reuter, and Y. Zaidan, Optima Core Wrapper Width Seection and SOC Test Scheduing Based On 3-Dimensiona n Pacing Agorithm, in Proc. Internationa Test Conf., pp. 74-8, October 00.