Comparison of pipelined IEEE-754 standard floating point multiplier with unpipelined multiplier
|
|
- Barry Hunter
- 5 years ago
- Views:
Transcription
1 Journal of Scientific & Industrial Research Vol. 65, November 2006, pp Comparison of pipelined IEEE-754 standard floating point multiplier with unpipelined multiplier Kavita Khare 1, *, R P Singh 1 and Nilay Khare 2 1 Department of Electronics and Communication Engineering, MANIT, Bhopal 2 CSE & IT Department, University Institute of Technology, Rajiv Gandhi Prodyougiki Vishvavidyalaya, Bhopal Received 07 April 2005; revised 21 June 2006; accepted 20 July 2006 The IEEE-754 standard floating point multiplier that provides highly precise computations to achieve high throughput and low area on the IC have been improved by insertion of pipelining technique. Floating point multiplier-using pipelining has been simulated, analyzed and its superiority over traditional designs is discussed. To achieve pipelining, one must subdivide the input process into sequence subtasks, each of which can be executed by specialized hardware stage that operates concurrently with other stages in the pipeline without the need of extra computing units. Detailed synthesis and simulation report operated upon Xilinx ISE 5.2i and Modelsim software is given. Hardware design is implemented on Virtex FPGA chips. Keywords: Floating point adder, IEEE floating point standard, Latency, Model-Sim, VHDL, Xilinx ISE 5.2i Introduction Until recently, any meaningful floating-point arithmetic (FPA) has been virtually impossible to implement on Field Programmable Gate Arrays (FPGA) based systems due to the limited density and speed of older FPGAs. In addition, mapping difficulties occurred due to inherent complexity of FPA. With the introduction of high-level languages such as VHDL, rapid prototyping of floating point units has become possible. Advanced digital signal processing requires FPA to achieve higher accuracy and high dynamic range for numerical computation. The IEEE has produced a standard for FPA. This standard specifies how single precision (32 bit) and double precision (64 bit) floating point numbers are to be represented, as well as how arithmetic should be carried out on them. Methodology In this paper, single precision representation is dealt with 1. The IEEE single precision floating point standard representation requires a 32 bit word, which may be represented from 0 to 31, left to right. First bit is the sign bit, s, the next eight bits are the exponent *Author for correspondence Tel: ; Fax: kavita_khare1@yahoo.co.in bits, E, and the final 23 bits are the mantissa, m. In IEEE-754 format 2, the significant always takes on an implied 1 for the most significant digit assuming the value represented is normalized (Table 1). Essential idea behind floating point number systems is to formulate representations and computation procedures in which the scaling procedures introduced by fixedpoint systems 2-4. Value of number, N = (-1) S X 2 (E-127) X (1.m) where, 0 <E> 255, Actual exponent is: e = E 127 Magnitude of numbers is in the range: (1.0) to ( ) Table 1 Single precision floating point number Exponent Significand Number presented Non zero Denormalized number (May be returned as a result of underflow in multiplication) 1 to 254 Anything Floating Point Number Infinity. (Positive divided by zero yields infinity ) 255 Non zero NaN (Zero divide by zero yields NaN Not A Number )
2 KHARE et al.: COMPARISON OF PIPELINED IEEE-754 MULTIPLIER WITH UNPIPELINED MULTIPLIER 901 Here pipelining offers an economic way to realize temporal parallelism in digital systems that achieve faster clock rates while sacrificing latency 1. Most modern processors, from PCs to supercomputer rely on pipeline techniques and floating-point multipliers (FPMs)/adders to achieve high throughput. A new algorithm for pipeline insertion is developed here and used for FP multiplication. The method of pipeline insertion consisted in the introduction of rows of latches through the multiplier structure, which divides into rows of cells that operate independently from each other 5. Multiplication operator expects to produce the result after a single clock cycle, thus producing a circuit requiring substantial amounts of CLB resources. Instead a pipelined approach for the integer multiplier has been examined to continue producing a result in each clock cycle. By using a pipelined multiplier, resource consumption decreases and speed increases. FPMs are designed and synthesized through Xilinx ISE 5.2i into a Virtex device. Floating Point Multiplier and its VHDL Implementation Assuming that the operands are already in the IEEE 754 format, performing floating-point multiplication result [R = X * Y = (-1) Xs (Xm 2Xe) * (-1) Ys (Ym 2Ye)] involves the following steps: 1) If one or both operands is equal to zero, return the result as zero, otherwise; 2) Compute the sign of the result Xs XOR Ys; 3) Compute the mantissa of the result [a) Multiply the mantissas: Xm * Ym; b) Round the result to the allowed number of mantissa bits]; 4) Compute the exponent of the result [Result exponent = biased exponent (X) + biased exponent (Y) bias]; 5) Normalize if needed, by shifting mantissa right, incrementing result exponent; and 6) Check result exponent for overflow/underflow [a) If larger than maximum exponent allowed return exponent overflow; b) If smaller than minimum exponent allowed return exponent underflow]. These independent operations within a multiplier make it ideal for pipelining. The three steps can be done for multiplier: 1) Unpack the operands, re-insert the hidden bit, and which for any exceptions on the operands (such as zeros or NaN); 2) Multiplication of the significands, calculation of the sign of the two significands and addition of the exponents takes place; and 3) Normalization and exponent adjustment 5. Rounding occurs in floating point multiplication when the mantissa of the product is reduced from 48 bits to 24 bits. The least significant 24 bits are discarded. Overflow occurs when the sum of the exponents exceeds 127, the largest value which is defined in bias-127 exponent representation. When this occurs, the exponent is set to 128 (E = 255) and the mantissa is set to zero indicating + or-infinity. Underflow occurs when the sum of the exponents is more negative than -126, the most negative value which is defined in bias -127 exponent representation. When this occurs, the exponent is set to -127 (E = 0). If m = 0, the number is exactly zero. If m is not zero, then a denormalized number is indicated which has an exponent of -127 and a hidden bit of 0. The smallest such number which is not zero is This number retains only a single bit of precision in the rightmost bit of the mantissa. Various VHDL modules developed are 7,8 : multiplier_pckg.vhd declares the various data types, functions and procedures in the design; multiplier.vhd consists of the various component instantiations and their port mapping; flag_check_ load.vhd first stage of the pipeline that performs the function of loading the operands, checking for the exceptional inputs, compares the exponents and generates the exponent difference; prod_sign.vhd second stage in the pipeline that shifts the mantissa according to the exponent difference value generated in the previous stage; speip_flag.vhd third stage in the pipeline that performs the basic addition or subtraction; and reg.vhd, reg_bit.vhd, reg_bitvector.vhd, reg_exp.vhd, reg_int.vhd, reg_mantissa.vhd, reg_mnt.vhd describe the various registers used to interface the various stages. Field Programmable Gate Arrays (FPGA) FPGA can be volatile or non-volatile. It consists of a two-dimensional array of logic blocks. Each logic block is programmable to implement any logic function. Thus, they are also called configurable logic blocks (CLBs). Switchboxes or channels contain interconnection resources that can be programmed to connect CLBs to implement more complex logic functions. Designers can use existing CAD tools to convert HDL code in order to program FPGAs. An FPGA contains 2,000-2,000,000 gates (or more). Since FPGA can be reprogrammed, the turn around time is only a few minutes. Advantages of FPGAs are
3 902 J SCI IND RES VOL 65 NOVEMBER 2006 lower prototyping costs and shorter production lead
4 KHARE et al.: COMPARISON OF PIPELINED IEEE-754 MULTIPLIER WITH UNPIPELINED MULTIPLIER 903 Table 2 Comparison between pipelined and unpipelined multipliers Device utilization summary: [Selected device Virtex 2p (2vp50ff1517-6)] Results Unpipelined multipliers Pipelined multipliers Number of slices 2222 out of (21%) 756 out of (3%) Number of slice flipflops 102 out of (0%) 4234 out of (20%) 305 out of (0%) Number of 4 input LUTs 102 out of 588 (17%) 1316 out of (2%) Number of bonded IOBs 100 out of 916 (10%) Timing summary (Speed Grade: -6) Minimum period ns 3.070ns MHz 1.265ns Maximum frequency MHz 1.265ns Minimum input arrival time before clock ns Maximum output required time after clock ns Thermal summary multiplier Estimated junction temperature: Ambient temp: Case temp: Theta J-A: 0C/W 0C/W Power summary of multiplier S No. Results Unpipelined multiplier Pipelined multiplier Power summary I (ma) P (mw) I (ma) P (mw) 1 Total estimated power consumption 3 Vccint 1.5V: Vcc.5V: Clocks: Nets: Logic: Inputs: Outputs: Quiescent 1.5V: Quiescent 2.5V: Fig. 2 Chip schematic of pipelined and unpipelined multipliers Fig. 1 Flow diagram of pipelined multiplier times, which advances the time-to-market and in turn increases profitability. It can also ensure the reliability of the design on the board 9,10. Xilinx Vertex-II FPGA used here has input output blocks (IOB) in two or four on the perimeter of each device. IOB includes 6 storage elements, each can be
5 904 J SCI IND RES VOL 65 NOVEMBER 2006 Fig. 4 Simulation Results of: a) Unpipelined multiplier; b) Pipelined multiplier Fig. 3 RTL Schematic of: a) Unpipelined multiplier (32 pages); b) Pipelined multiplier configured as an edge triggered D-Type flip flop or a level sensitive switch. Device has CLB in arrays of switch. Each CLB has 4 slices.
6 KHARE et al.: COMPARISON OF PIPELINED IEEE-754 MULTIPLIER WITH UNPIPELINED MULTIPLIER 905 Results and Conclusions Both unpipelined and pipelined FP multipliers have been implemented in VHDL (Figs 1-5). Reports of device utilization summary and timing summary are given in Table 2. Several units were synthesized of FP multiplier to quantify the performance and space requirements under the reported approach. The synthesis was carried from a VHDL source and the target device was a Xilinx Virtex-II FPGA (2V1000FG456 6) 11. Effect of increasing the number of pipeline stages effectively increases the operating frequency. If pipelined multiplier is used, device utilization and power consumption is reduced, further speed of output increases from to MHz, hence throughput increases (Table 2). References 1 Khare K, Singh R P & Khare N, Comparison of pipelined IEEE-754 standard floating point adder with unpipelined adder, J Sci Ind Res, 64 (2005) Shirazi Nabeel & Athanas P, Quantitative analysis of floating point arithmetic based custom computing machines, IEEE Symp on FPGA for Custom Computing Machines (Napa Valley, California) 1995, Eldon John A & Robertson Craig, A floating point format for signal processing, IEEE Acoustics, Speech, and Signal Processing Conf (USA) 1992, Yalamanchi S & Koltur R, Single Precision Floating-Point Unit, FDU project, Asato C D, A data-path multiplier with automatic insertion of pipeline stages, IEEE J Solid-State Circuits, 4 (1990) Walters A, Scaleable filter implement using 32 bit floating point complex arithmetic on a FPGA based custom computing platform, M S Thesis, Blacksburg, Virginia, Ashenden Peter J, The Designers Guide to VHDL (Harcourt Asia Pvt Ltd., Singapore) 2000, Douglas P, VHDL, 2 nd edn (McGraw Hill, Singapore) 1994, Armstrong J R & Gray F G, Structured Logic Design with VHDL (Prentice Hall, India) 1993, Eshraghian K & Weste Neil H E, Principle of CMOS and VLSI Design: A system perspective, 2 nd edn (Addision Wesley Publishing company, Singapore) 1993, Puspam Vikram, Miller Andy & Chappman Ken, Xilinx application notes Xapp 219, Oct Fig. 5 FPGA Editor of: a) Unpipelined multiplier; b) Pipelined multiplier
International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
An Efficient Implementation of Double Precision Floating Point Multiplier Using Booth Algorithm Pallavi Ramteke 1, Dr. N. N. Mhala 2, Prof. P. R. Lakhe M.Tech [IV Sem], Dept. of Comm. Engg., S.D.C.E, [Selukate],
More informationAn FPGA Based Floating Point Arithmetic Unit Using Verilog
An FPGA Based Floating Point Arithmetic Unit Using Verilog T. Ramesh 1 G. Koteshwar Rao 2 1PG Scholar, Vaagdevi College of Engineering, Telangana. 2Assistant Professor, Vaagdevi College of Engineering,
More informationAn Efficient Implementation of Floating Point Multiplier
An Efficient Implementation of Floating Point Multiplier Mohamed Al-Ashrafy Mentor Graphics Mohamed_Samy@Mentor.com Ashraf Salem Mentor Graphics Ashraf_Salem@Mentor.com Wagdy Anis Communications and Electronics
More informationImplementation of Double Precision Floating Point Multiplier in VHDL
ISSN (O): 2349-7084 International Journal of Computer Engineering In Research Trends Available online at: www.ijcert.org Implementation of Double Precision Floating Point Multiplier in VHDL 1 SUNKARA YAMUNA
More informationInternational Journal of Advanced Research in Computer Science and Software Engineering
ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: Configuring Floating Point Multiplier on Spartan 2E Hardware
More informationDesign and Optimized Implementation of Six-Operand Single- Precision Floating-Point Addition
2011 International Conference on Advancements in Information Technology With workshop of ICBMG 2011 IPCSIT vol.20 (2011) (2011) IACSIT Press, Singapore Design and Optimized Implementation of Six-Operand
More informationFigurel. TEEE-754 double precision floating point format. Keywords- Double precision, Floating point, Multiplier,FPGA,IEEE-754.
AN FPGA BASED HIGH SPEED DOUBLE PRECISION FLOATING POINT MULTIPLIER USING VERILOG N.GIRIPRASAD (1), K.MADHAVA RAO (2) VLSI System Design,Tudi Ramireddy Institute of Technology & Sciences (1) Asst.Prof.,
More informationAn FPGA based Implementation of Floating-point Multiplier
An FPGA based Implementation of Floating-point Multiplier L. Rajesh, Prashant.V. Joshi and Dr.S.S. Manvi Abstract In this paper we describe the parameterization, implementation and evaluation of floating-point
More informationVHDL IMPLEMENTATION OF FLOATING POINT MULTIPLIER USING VEDIC MATHEMATICS
VHDL IMPLEMENTATION OF FLOATING POINT MULTIPLIER USING VEDIC MATHEMATICS I.V.VAIBHAV 1, K.V.SAICHARAN 1, B.SRAVANTHI 1, D.SRINIVASULU 2 1 Students of Department of ECE,SACET, Chirala, AP, India 2 Associate
More informationDesign and Implementation of IEEE-754 Decimal Floating Point Adder, Subtractor and Multiplier
International Journal of Engineering and Advanced Technology (IJEAT) ISSN: 2249 8958, Volume-4 Issue 1, October 2014 Design and Implementation of IEEE-754 Decimal Floating Point Adder, Subtractor and Multiplier
More informationRun-Time Reconfigurable multi-precision floating point multiplier design based on pipelining technique using Karatsuba-Urdhva algorithms
Run-Time Reconfigurable multi-precision floating point multiplier design based on pipelining technique using Karatsuba-Urdhva algorithms 1 Shruthi K.H., 2 Rekha M.G. 1M.Tech, VLSI design and embedded system,
More informationPrachi Sharma 1, Rama Laxmi 2, Arun Kumar Mishra 3 1 Student, 2,3 Assistant Professor, EC Department, Bhabha College of Engineering
A Review: Design of 16 bit Arithmetic and Logical unit using Vivado 14.7 and Implementation on Basys 3 FPGA Board Prachi Sharma 1, Rama Laxmi 2, Arun Kumar Mishra 3 1 Student, 2,3 Assistant Professor,
More informationImplementation of Floating Point Multiplier Using Dadda Algorithm
Implementation of Floating Point Multiplier Using Dadda Algorithm Abstract: Floating point multiplication is the most usefull in all the computation application like in Arithematic operation, DSP application.
More informationQuixilica Floating Point FPGA Cores
Data sheet Quixilica Floating Point FPGA Cores Floating Point Adder - 169 MFLOPS* on VirtexE-8 Floating Point Multiplier - 152 MFLOPS* on VirtexE-8 Floating Point Divider - 189 MFLOPS* on VirtexE-8 Floating
More informationInternational Journal of Advanced Research in Computer Science and Software Engineering
ISSN: 2277 128X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: Implementation of Floating Point Multiplier on Reconfigurable
More informationDESIGN AND IMPLEMENTATION OF VLSI SYSTOLIC ARRAY MULTIPLIER FOR DSP APPLICATIONS
International Journal of Computing Academic Research (IJCAR) ISSN 2305-9184 Volume 2, Number 4 (August 2013), pp. 140-146 MEACSE Publications http://www.meacse.org/ijcar DESIGN AND IMPLEMENTATION OF VLSI
More informationDevelopment of an FPGA based high speed single precision floating point multiplier
International Journal of Electronic and Electrical Engineering. ISSN 0974-2174 Volume 8, Number 1 (2015), pp. 27-32 International Research Publication House http://www.irphouse.com Development of an FPGA
More informationISSN Vol.02, Issue.11, December-2014, Pages:
ISSN 2322-0929 Vol.02, Issue.11, December-2014, Pages:1208-1212 www.ijvdcs.org Implementation of Area Optimized Floating Point Unit using Verilog G.RAJA SEKHAR 1, M.SRIHARI 2 1 PG Scholar, Dept of ECE,
More informationFPGA Implementation of Multiplier for Floating- Point Numbers Based on IEEE Standard
FPGA Implementation of Multiplier for Floating- Point Numbers Based on IEEE 754-2008 Standard M. Shyamsi, M. I. Ibrahimy, S. M. A. Motakabber and M. R. Ahsan Dept. of Electrical and Computer Engineering
More informationA Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Modified CSA
RESEARCH ARTICLE OPEN ACCESS A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier using Nishi Pandey, Virendra Singh Sagar Institute of Research & Technology Bhopal Abstract Due to
More informationUniversity, Patiala, Punjab, India 1 2
1102 Design and Implementation of Efficient Adder based Floating Point Multiplier LOKESH BHARDWAJ 1, SAKSHI BAJAJ 2 1 Student, M.tech, VLSI, 2 Assistant Professor,Electronics and Communication Engineering
More informationImplementation of IEEE754 Floating Point Multiplier
Implementation of IEEE754 Floating Point Multiplier A Kumutha 1 Shobha. P 2 1 MVJ College of Engineering, Near ITPB, Channasandra, Bangalore-67. 2 MVJ College of Engineering, Near ITPB, Channasandra, Bangalore-67.
More informationPipelined High Speed Double Precision Floating Point Multiplier Using Dadda Algorithm Based on FPGA
RESEARCH ARTICLE OPEN ACCESS Pipelined High Speed Double Precision Floating Point Multiplier Using Dadda Algorithm Based on FPGA J.Rupesh Kumar, G.Ram Mohan, Sudershanraju.Ch M. Tech Scholar, Dept. of
More informationFig.1. Floating point number representation of single-precision (32-bit). Floating point number representation in double-precision (64-bit) format:
1313 DESIGN AND PERFORMANCE ANALYSIS OF DOUBLE- PRECISION FLOATING POINT MULTIPLIER USING URDHVA TIRYAGBHYAM SUTRA Y SRINIVASA RAO 1, T SUBHASHINI 2, K RAMBABU 3 P.G Student 1, Assistant Professor 2, Assistant
More informationDesign and Implementation of VLSI 8 Bit Systolic Array Multiplier
Design and Implementation of VLSI 8 Bit Systolic Array Multiplier Khumanthem Devjit Singh, K. Jyothi MTech student (VLSI & ES), GIET, Rajahmundry, AP, India Associate Professor, Dept. of ECE, GIET, Rajahmundry,
More informationComparison of Adders for optimized Exponent Addition circuit in IEEE754 Floating point multiplier using VHDL
International Journal of Engineering Research and Development e-issn: 2278-067X, p-issn: 2278-800X, www.ijerd.com Volume 11, Issue 07 (July 2015), PP.60-65 Comparison of Adders for optimized Exponent Addition
More informationA High Speed Binary Floating Point Multiplier Using Dadda Algorithm
455 A High Speed Binary Floating Point Multiplier Using Dadda Algorithm B. Jeevan, Asst. Professor, Dept. of E&IE, KITS, Warangal. jeevanbs776@gmail.com S. Narender, M.Tech (VLSI&ES), KITS, Warangal. narender.s446@gmail.com
More informationFLOATING POINT ADDERS AND MULTIPLIERS
Concordia University FLOATING POINT ADDERS AND MULTIPLIERS 1 Concordia University Lecture #4 In this lecture we will go over the following concepts: 1) Floating Point Number representation 2) Accuracy
More informationFloating Point Arithmetic
Floating Point Arithmetic CS 365 Floating-Point What can be represented in N bits? Unsigned 0 to 2 N 2s Complement -2 N-1 to 2 N-1-1 But, what about? very large numbers? 9,349,398,989,787,762,244,859,087,678
More informationDesign and Simulation of Pipelined Double Precision Floating Point Adder/Subtractor and Multiplier Using Verilog
Design and Simulation of Pipelined Double Precision Floating Point Adder/Subtractor and Multiplier Using Verilog Onkar Singh (1) Kanika Sharma (2) Dept. ECE, Arni University, HP (1) Dept. ECE, NITTTR Chandigarh
More informationDesign of Double Precision Floating Point Multiplier Using Vedic Multiplication
Design of Double Precision Floating Point Multiplier Using Vedic Multiplication 1 D.Heena Tabassum, 2 K.Sreenivas Rao 1, 2 Electronics and Communication Engineering, 1, 2 Annamacharya institute of technology
More informationBy, Ajinkya Karande Adarsh Yoga
By, Ajinkya Karande Adarsh Yoga Introduction Early computer designers believed saving computer time and memory were more important than programmer time. Bug in the divide algorithm used in Intel chips.
More informationMIPS Integer ALU Requirements
MIPS Integer ALU Requirements Add, AddU, Sub, SubU, AddI, AddIU: 2 s complement adder/sub with overflow detection. And, Or, Andi, Ori, Xor, Xori, Nor: Logical AND, logical OR, XOR, nor. SLTI, SLTIU (set
More informationA Library of Parameterized Floating-point Modules and Their Use
A Library of Parameterized Floating-point Modules and Their Use Pavle Belanović and Miriam Leeser Department of Electrical and Computer Engineering Northeastern University Boston, MA, 02115, USA {pbelanov,mel}@ece.neu.edu
More informationImplementation and Comparative Analysis between Devices for Double Precision Interval Arithmetic Radix 4 Wallace tree Multiplication
Implementation and Comparative Analysis between Devices for Double Precision Interval Arithmetic Radix 4 Wallace tree Multiplication Krutika Ranjankumar Bhagwat #1, Dr. Tejas V. Shah * 2, Prof. Deepali
More informationANALYSIS OF AN AREA EFFICIENT VLSI ARCHITECTURE FOR FLOATING POINT MULTIPLIER AND GALOIS FIELD MULTIPLIER*
IJVD: 3(1), 2012, pp. 21-26 ANALYSIS OF AN AREA EFFICIENT VLSI ARCHITECTURE FOR FLOATING POINT MULTIPLIER AND GALOIS FIELD MULTIPLIER* Anbuselvi M. and Salivahanan S. Department of Electronics and Communication
More informationImplementation of IEEE-754 Double Precision Floating Point Multiplier
Implementation of IEEE-754 Double Precision Floating Point Multiplier G.Lakshmi, M.Tech Lecturer, Dept of ECE S K University College of Engineering Anantapuramu, Andhra Pradesh, India ABSTRACT: Floating
More informationFloating Point. The World is Not Just Integers. Programming languages support numbers with fraction
1 Floating Point The World is Not Just Integers Programming languages support numbers with fraction Called floating-point numbers Examples: 3.14159265 (π) 2.71828 (e) 0.000000001 or 1.0 10 9 (seconds in
More informationArchitecture and Design of Generic IEEE-754 Based Floating Point Adder, Subtractor and Multiplier
Architecture and Design of Generic IEEE-754 Based Floating Point Adder, Subtractor and Multiplier Sahdev D. Kanjariya VLSI & Embedded Systems Design Gujarat Technological University PG School Ahmedabad,
More informationARCHITECTURAL DESIGN OF 8 BIT FLOATING POINT MULTIPLICATION UNIT
ARCHITECTURAL DESIGN OF 8 BIT FLOATING POINT MULTIPLICATION UNIT Usha S. 1 and Vijaya Kumar V. 2 1 VLSI Design, Sathyabama University, Chennai, India 2 Department of Electronics and Communication Engineering,
More informationADDERS AND MULTIPLIERS
Concordia University FLOATING POINT ADDERS AND MULTIPLIERS 1 Concordia University Lecture #4 In this lecture we will go over the following concepts: 1) Floating Point Number representation 2) Accuracy
More informationDouble Precision Floating-Point Arithmetic on FPGAs
MITSUBISHI ELECTRIC ITE VI-Lab Title: Double Precision Floating-Point Arithmetic on FPGAs Internal Reference: Publication Date: VIL04-D098 Author: S. Paschalakis, P. Lee Rev. A Dec. 2003 Reference: Paschalakis,
More informationFloating-point representations
Lecture 10 Floating-point representations Methods of representing real numbers (1) 1. Fixed-point number system limited range and/or limited precision results must be scaled 100101010 1111010 100101010.1111010
More informationFloating-point representations
Lecture 10 Floating-point representations Methods of representing real numbers (1) 1. Fixed-point number system limited range and/or limited precision results must be scaled 100101010 1111010 100101010.1111010
More informationImplementation of Double Precision Floating Point Multiplier on FPGA
Implementation of Double Precision Floating Point Multiplier on FPGA A.Keerthi 1, K.V.Koteswararao 2 PG Student [VLSI], Dept. of ECE, Sree Vidyanikethan Engineering College, Tirupati, India 1 Assistant
More informationFPGA Implementation of MIPS RISC Processor
FPGA Implementation of MIPS RISC Processor S. Suresh 1 and R. Ganesh 2 1 CVR College of Engineering/PG Student, Hyderabad, India 2 CVR College of Engineering/ECE Department, Hyderabad, India Abstract The
More informationImplementation of Double Precision Floating Point Multiplier Using Wallace Tree Multiplier
Implementation of Double Precision Floating Point Multiplier Using Wallace Tree Multiplier Y. Ramya sri 1, V B K L Aruna 2 P.G. Student, Department of Electronics Engineering, V.R Siddhartha Engineering
More informationDouble Precision Floating-Point Multiplier using Coarse-Grain Units
Double Precision Floating-Point Multiplier using Coarse-Grain Units Rui Duarte INESC-ID/IST/UTL. rduarte@prosys.inesc-id.pt Mário Véstias INESC-ID/ISEL/IPL. mvestias@deetc.isel.ipl.pt Horácio Neto INESC-ID/IST/UTL
More informationFloating Point Numbers
Floating Point Numbers Summer 8 Fractional numbers Fractional numbers fixed point Floating point numbers the IEEE 7 floating point standard Floating point operations Rounding modes CMPE Summer 8 Slides
More informationReview on Floating Point Adder and Converter Units Using VHDL
Review on Floating Point Adder and Converter Units Using VHDL Abhishek Kumar 1, Mayur S. Dhait 2 1 Research Scholar, Agnihotri College of Engineering, Nagthana Road, Wardha (M.S), India 2 Professor, Department
More informationECE232: Hardware Organization and Design
ECE232: Hardware Organization and Design Lecture 11: Floating Point & Floating Point Addition Adapted from Computer Organization and Design, Patterson & Hennessy, UCB Last time: Single Precision Format
More informationCOMPARISION OF PARALLEL BCD MULTIPLICATION IN LUT-6 FPGA AND 64-BIT FLOTING POINT ARITHMATIC USING VHDL
COMPARISION OF PARALLEL BCD MULTIPLICATION IN LUT-6 FPGA AND 64-BIT FLOTING POINT ARITHMATIC USING VHDL Mrs. Vibha Mishra M Tech (Embedded System And VLSI Design) GGITS,Jabalpur Prof. Vinod Kapse Head
More informationNumber Systems Standard positional representation of numbers: An unsigned number with whole and fraction portions is represented as:
N Number Systems Standard positional representation of numbers: An unsigned number with whole and fraction portions is represented as: a n a a a The value of this number is given by: = a n Ka a a a a a
More informationImplementation of a High Speed Binary Floating point Multiplier Using Dadda Algorithm in FPGA
Implementation of a High Speed Binary Floating point Multiplier Using Dadda Algorithm in FPGA Ms.Komal N.Batra 1, Prof. Ashish B. Kharate 2 1 PG Student, ENTC Department, HVPM S College of Engineering
More informationAn Implementation of Double precision Floating point Adder & Subtractor Using Verilog
IOSR Journal of Electrical and Electronics Engineering (IOSR-JEEE) e-issn: 2278-1676,p-ISSN: 2320-3331, Volume 9, Issue 4 Ver. III (Jul Aug. 2014), PP 01-05 An Implementation of Double precision Floating
More informationSIMULATION AND SYNTHESIS OF 32-BIT MULTIPLIER USING CONFIGURABLE DEVICES
SIMULATION AND SYNTHESIS OF 32-BIT MULTIPLIER USING CONFIGURABLE DEVICES Dinesh Kumar 1 and Girish Chander Lall 2 ECE Deptt., MMEC, Mullana, India ECE Deptt., HCTM, Kaithal, India ABSTRACT Floating- point
More informationVLSI Implementation of Adders for High Speed ALU
VLSI Implementation of Adders for High Speed ALU Prashant Gurjar Rashmi Solanki Pooja Kansliwal Mahendra Vucha Asst. Prof., Dept. EC,, ABSTRACT This paper is primarily deals the construction of high speed
More informationComputer Arithmetic Floating Point
Computer Arithmetic Floating Point Chapter 3.6 EEC7 FQ 25 About Floating Point Arithmetic Arithmetic basic operations on floating point numbers are: Add, Subtract, Multiply, Divide Transcendental operations
More informationFloating-point Arithmetic. where you sum up the integer to the left of the decimal point and the fraction to the right.
Floating-point Arithmetic Reading: pp. 312-328 Floating-Point Representation Non-scientific floating point numbers: A non-integer can be represented as: 2 4 2 3 2 2 2 1 2 0.2-1 2-2 2-3 2-4 where you sum
More informationInternational Journal of Research in Computer and Communication Technology, Vol 4, Issue 11, November- 2015
Design of Dadda Algorithm based Floating Point Multiplier A. Bhanu Swetha. PG.Scholar: M.Tech(VLSISD), Department of ECE, BVCITS, Batlapalem. E.mail:swetha.appari@gmail.com V.Ramoji, Asst.Professor, Department
More informationSystem Verification of Hardware Optimization Based on Edge Detection
Circuits and Systems, 2013, 4, 293-298 http://dx.doi.org/10.4236/cs.2013.43040 Published Online July 2013 (http://www.scirp.org/journal/cs) System Verification of Hardware Optimization Based on Edge Detection
More informationPipelined Quadratic Equation based Novel Multiplication Method for Cryptographic Applications
, Vol 7(4S), 34 39, April 204 ISSN (Print): 0974-6846 ISSN (Online) : 0974-5645 Pipelined Quadratic Equation based Novel Multiplication Method for Cryptographic Applications B. Vignesh *, K. P. Sridhar
More informationCOMPUTER ARCHITECTURE AND ORGANIZATION. Operation Add Magnitudes Subtract Magnitudes (+A) + ( B) + (A B) (B A) + (A B)
Computer Arithmetic Data is manipulated by using the arithmetic instructions in digital computers. Data is manipulated to produce results necessary to give solution for the computation problems. The Addition,
More informationChapter 03: Computer Arithmetic. Lesson 09: Arithmetic using floating point numbers
Chapter 03: Computer Arithmetic Lesson 09: Arithmetic using floating point numbers Objective To understand arithmetic operations in case of floating point numbers 2 Multiplication of Floating Point Numbers
More informationDesigning an Improved 64 Bit Arithmetic and Logical Unit for Digital Signaling Processing Purposes
Available Online at- http://isroj.net/index.php/issue/current-issue ISROJ Index Copernicus Value for 2015: 49.25 Volume 02 Issue 01, 2017 e-issn- 2455 8818 Designing an Improved 64 Bit Arithmetic and Logical
More informationFPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors
2018 IJSRST Volume 4 Issue 2 Print ISSN: 2395-6011 Online ISSN: 2395-602X Themed Section: Science and Technology FPGA Implementation of Single Precision Floating Point Multiplier Using High Speed Compressors
More informationDesign and Implementation of Floating Point Multiplier for Better Timing Performance
Design and Implementation of Floating Point Multiplier for Better Timing Performance B.Sreenivasa Ganesh 1,J.E.N.Abhilash 2, G. Rajesh Kumar 3 SwarnandhraCollege of Engineering& Technology 1,2, Vishnu
More informationChapter 4. Operations on Data
Chapter 4 Operations on Data 1 OBJECTIVES After reading this chapter, the reader should be able to: List the three categories of operations performed on data. Perform unary and binary logic operations
More informationA comparative study of Floating Point Multipliers Using Ripple Carry Adder and Carry Look Ahead Adder
A comparative study of Floating Point Multipliers Using Ripple Carry Adder and Carry Look Ahead Adder 1 Jaidev Dalvi, 2 Shreya Mahajan, 3 Saya Mogra, 4 Akanksha Warrier, 5 Darshana Sankhe 1,2,3,4,5 Department
More information16 BIT IMPLEMENTATION OF ASYNCHRONOUS TWOS COMPLEMENT ARRAY MULTIPLIER USING MODIFIED BAUGH-WOOLEY ALGORITHM AND ARCHITECTURE.
16 BIT IMPLEMENTATION OF ASYNCHRONOUS TWOS COMPLEMENT ARRAY MULTIPLIER USING MODIFIED BAUGH-WOOLEY ALGORITHM AND ARCHITECTURE. AditiPandey* Electronics & Communication,University Institute of Technology,
More informationLogiCORE IP Floating-Point Operator v6.2
LogiCORE IP Floating-Point Operator v6.2 Product Guide Table of Contents SECTION I: SUMMARY IP Facts Chapter 1: Overview Unsupported Features..............................................................
More informationPERFORMANCE ANALYSIS OF HIGH EFFICIENCY LOW DENSITY PARITY-CHECK CODE DECODER FOR LOW POWER APPLICATIONS
American Journal of Applied Sciences 11 (4): 558-563, 2014 ISSN: 1546-9239 2014 Science Publication doi:10.3844/ajassp.2014.558.563 Published Online 11 (4) 2014 (http://www.thescipub.com/ajas.toc) PERFORMANCE
More informationFPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase
FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase Abhay Sharma M.Tech Student Department of ECE MNNIT Allahabad, India ABSTRACT Tree Multipliers are frequently
More informationISSN: X Impact factor: (Volume3, Issue2) Analyzing Two-Term Dot Product of Multiplier Using Floating Point and Booth Multiplier
ISSN: 2454-132X Impact factor: 4.295 (Volume3, Issue2) Analyzing Two-Term Dot Product of Multiplier Using Floating Point and Booth Multiplier 1 Mukesh Krishna Department Electrical and Electronics Engineering
More informationVTU NOTES QUESTION PAPERS NEWS RESULTS FORUMS Arithmetic (a) The four possible cases Carry (b) Truth table x y
Arithmetic A basic operation in all digital computers is the addition and subtraction of two numbers They are implemented, along with the basic logic functions such as AND,OR, NOT,EX- OR in the ALU subsystem
More informationAnalysis of High-performance Floating-point Arithmetic on FPGAs
Analysis of High-performance Floating-point Arithmetic on FPGAs Gokul Govindu, Ling Zhuo, Seonil Choi and Viktor Prasanna Dept. of Electrical Engineering University of Southern California Los Angeles,
More informationMeasuring Improvement When Using HUB Formats to Implement Floating-Point Systems under Round-to- Nearest
Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems under Round-to- Nearest Abstract: This paper analyzes the benefits of using half-unitbiased (HUB) formats to implement floatingpoint
More informationDESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTOR SUPPORT
DESIGN OF DOUBLE PRECISION FLOATING POINT MULTIPLICATION ALGORITHM WITH VECTOR SUPPORT T.Govinda Rao, P.Devi Pradeep, P.Kalyanchakravarthi Assistant Professor, Department of ECE, GMRIT, RAJAM, AP, INDIA
More informationFPGA IMPLEMENTATION OF FLOATING POINT ADDER AND MULTIPLIER UNDER ROUND TO NEAREST
FPGA IMPLEMENTATION OF FLOATING POINT ADDER AND MULTIPLIER UNDER ROUND TO NEAREST SAKTHIVEL Assistant Professor, Department of ECE, Coimbatore Institute of Engineering and Technology Abstract- FPGA is
More informationAn Efficient FPGA Implementation of the Advanced Encryption Standard (AES) Algorithm Using S-Box
Volume 5 Issue 2 June 2017 ISSN: 2320-9984 (Online) International Journal of Modern Engineering & Management Research Website: www.ijmemr.org An Efficient FPGA Implementation of the Advanced Encryption
More informationChapter 5 : Computer Arithmetic
Chapter 5 Computer Arithmetic Integer Representation: (Fixedpoint representation): An eight bit word can be represented the numbers from zero to 255 including = 1 = 1 11111111 = 255 In general if an nbit
More informationA Low Power Asynchronous FPGA with Autonomous Fine Grain Power Gating and LEDR Encoding
A Low Power Asynchronous FPGA with Autonomous Fine Grain Power Gating and LEDR Encoding N.Rajagopala krishnan, k.sivasuparamanyan, G.Ramadoss Abstract Field Programmable Gate Arrays (FPGAs) are widely
More informationFLOATING POINT NUMBERS
Exponential Notation FLOATING POINT NUMBERS Englander Ch. 5 The following are equivalent representations of 1,234 123,400.0 x 10-2 12,340.0 x 10-1 1,234.0 x 10 0 123.4 x 10 1 12.34 x 10 2 1.234 x 10 3
More informationVLSI DESIGN OF REDUCED INSTRUCTION SET COMPUTER PROCESSOR CORE USING VHDL
International Journal of Electronics, Communication & Instrumentation Engineering Research and Development (IJECIERD) ISSN 2249-684X Vol.2, Issue 3 (Spl.) Sep 2012 42-47 TJPRC Pvt. Ltd., VLSI DESIGN OF
More informationDigital Logic & Computer Design CS Professor Dan Moldovan Spring 2010
Digital Logic & Computer Design CS 434 Professor Dan Moldovan Spring 2 Copyright 27 Elsevier 5- Chapter 5 :: Digital Building Blocks Digital Design and Computer Architecture David Money Harris and Sarah
More informationFloating-Point Data Representation and Manipulation 198:231 Introduction to Computer Organization Lecture 3
Floating-Point Data Representation and Manipulation 198:231 Introduction to Computer Organization Instructor: Nicole Hynes nicole.hynes@rutgers.edu 1 Fixed Point Numbers Fixed point number: integer part
More informationModule 2: Computer Arithmetic
Module 2: Computer Arithmetic 1 B O O K : C O M P U T E R O R G A N I Z A T I O N A N D D E S I G N, 3 E D, D A V I D L. P A T T E R S O N A N D J O H N L. H A N N E S S Y, M O R G A N K A U F M A N N
More informationFPGA based Simulation of Clock Gated ALU Architecture with Multiplexed Logic Enable for Low Power Applications
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 04, 2015 ISSN (online): 2321-0613 FPGA based Simulation of Clock Gated ALU Architecture with Multiplexed Logic Enable for
More informationEE260: Logic Design, Spring n Integer multiplication. n Booth s algorithm. n Integer division. n Restoring, non-restoring
EE 260: Introduction to Digital Design Arithmetic II Yao Zheng Department of Electrical Engineering University of Hawaiʻi at Mānoa Overview n Integer multiplication n Booth s algorithm n Integer division
More informationVHDL for Synthesis. Course Description. Course Duration. Goals
VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes
More informationHigh speed Integrated Circuit Hardware Description Language), RTL (Register transfer level). Abstract:
based implementation of 8-bit ALU of a RISC processor using Booth algorithm written in VHDL language Paresh Kumar Pasayat, Manoranjan Pradhan, Bhupesh Kumar Pasayat Abstract: This paper explains the design
More informationFPGA based High Speed Double Precision Floating Point Divider
FPGA based High Speed Double Precision Floating Point Divider Addanki Purna Ramesh Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, India. Dhanalakshmi Balusu Department
More informationINTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY
INTERNATIONAL JOURNAL OF PURE AND APPLIED RESEARCH IN ENGINEERING AND TECHNOLOGY A PATH FOR HORIZING YOUR INNOVATIVE WORK DESIGN AND VERIFICATION OF FAST 32 BIT BINARY FLOATING POINT MULTIPLIER BY INCREASING
More informationDesign and Analysis of Inexact Floating Point Multipliers
Design and Analysis of Inexact Floating Point Multipliers Jogadenu Vedavathi 1 Mrs.T.Nagalaxmi 2 jogadenuvedavathi1993@gmail.com 1 tnagalaxmi@stanley.edu.in 2 1 PG Scholar, Dept of ECE, Stanley College
More informationThe Sign consists of a single bit. If this bit is '1', then the number is negative. If this bit is '0', then the number is positive.
IEEE 754 Standard - Overview Frozen Content Modified by on 13-Sep-2017 Before discussing the actual WB_FPU - Wishbone Floating Point Unit peripheral in detail, it is worth spending some time to look at
More informationVendor Agnostic, High Performance, Double Precision Floating Point Division for FPGAs
Vendor Agnostic, High Performance, Double Precision Floating Point Division for FPGAs Xin Fang and Miriam Leeser Dept of Electrical and Computer Eng Northeastern University Boston, Massachusetts 02115
More informationVLSI DESIGN OF FLOATING POINT ARITHMETIC & LOGIC UNIT
VLSI DESIGN OF FLOATING POINT ARITHMETIC & LOGIC UNIT 1 DHANABAL R, 2 BHARATHI V, 3 G.SRI CHANDRAKIRAN, 4 BHARATH BHUSHAN REDDY.M 1 Assistant Professor (Senior Grade), VLSI division, SENSE, VIT University,
More informationImplementation of Double Precision Floating Point Adder with Residue for High Accuracy Using FPGA
1008 Implementation of Double Precision Floating Point Adder with Residue for High Accuracy Using FPGA P.V.V.S. Narayana 1, N.V.N. Prasanna Kumar 2 1 (M.Tech Student, Department of ECE, Sri Vasavi Engineering
More informationTHE INTERNATIONAL JOURNAL OF SCIENCE & TECHNOLEDGE
THE INTERNATIONAL JOURNAL OF SCIENCE & TECHNOLEDGE Design and Implementation of Optimized Floating Point Matrix Multiplier Based on FPGA Maruti L. Doddamani IV Semester, M.Tech (Digital Electronics), Department
More informationFloating-Point Matrix Product on FPGA
Floating-Point Matrix Product on FPGA Faycal Bensaali University of Hertfordshire f.bensaali@herts.ac.uk Abbes Amira Brunel University abbes.amira@brunel.ac.uk Reza Sotudeh University of Hertfordshire
More information