Designing an Improved 64 Bit Arithmetic and Logical Unit for Digital Signaling Processing Purposes

Size: px

Start display at page:

Download "Designing an Improved 64 Bit Arithmetic and Logical Unit for Digital Signaling Processing Purposes"

Donald Greer
6 years ago
Views:

1 Available Online at- ISROJ Index Copernicus Value for 2015: Volume 02 Issue 01, 2017 e-issn Designing an Improved 64 Bit Arithmetic and Logical Unit for Digital Signaling Processing Purposes Shubhankar Thapliyal 1, Kartik Sehgal 2, Utkarsh Sundaram 3, Akshay Sharma 4, *B Khaleelu Rehman 5 1, 2, 3,4 Students of University of Petroleum and Energy Studies, Bidholi, Via Premnagar, Dehradun, India, Assistant Professor, Department of Electronics, Instrumentation and Control, of University of Petroleum and Energy Studies, Bidholi, Via Premnagar, Dehradun, India, Abstract: - In the present-day technology, there is a massive need of developing suitable data communication interfaces for real time embedded systems. Field Programmable Gate Array (FPGA) offers various resources, which can be programmed for building up an efficient embedded system. A Field-programmable Gate Array (FPGA) is an integrated circuit designed to be configured by the de-signer after manufacturing hence it is named as "field-programmable". The FPGA configuration is generally specified using a hardware description language. VHDL (VHSIC hardware description language) is a hardware description language which can be used in electronic design automation to describe digital signal systems such as field- programmable gate arrays and integrated circuits. It became IEEE standard 1076 in The VHDL standard IEEE was published in January This report proposes a technique to design and implement a 64 bit ALU which is a digital circuit that performs arithmetic and logical operations on Xilinx ISE using VHDL. Keywords: - VHDL, Xilinx, ALU, FPGA, Model Sim Introduction Arithmetic Logic Unit is a digital circuit that performs arithmetic, logical and shift operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer. [1] The project is to design low power 64 bit ALU. Here ALU is designed with the help of multiplexers and full adder. The main component in the ALU is full adder. In CMOS method eight transistor full adder and CMOS based multiplexers are used. In PTL method six transistor full adder and PTL based multiplexers are used. To reduce area, ripple carry adder is used in ALU. [2] In this project, the aim is to design a high speed, less area 64-bit Arithmetic and Logic Unit by efficient techniques using VHDL language. The optimization of the proposed design will be done by using the different techniques. The parameters speed and area of the design will be improved by using Carry Look Ahead Technique. It also reduces the circuit complexity. [3] In this paper, VHDL implementation of 64-bit arithmetic logic unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 9.1 and targeted for Spartan device. ALU was designed to perform arithmetic operation and logical operations such as addition, subtraction using 64-bit fast adder, logical operations such as AND, OR, XOR and NOT operations, 1 scomplement, rotate operations and compare. [4] This paper presents the behavioral Design and synthesis of a 64 bit ALU. 64 bit ALU is basically a multiplexer that operates mainly 16 operations as per select line Bit-permutation. Flags are other important indicators used for specific purpose. [5] The proposed project deals with design and simulation of 64 bit ALU using VHDL with the help of Xilinx ISE software. The processors found inside modern CPUs and graphics processing units (GPUs) can accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. Mathematician John von Neumann proposed the ALU concept in 1945, for which he wrote a report on the foundations for a new computer called the EDVAC. Research into ALUs remains an important part of computer science. Here, ALU is designed using VHDL which is a hardware description language used in electronic design automation to describe digital signal systems such as fieldprogrammable gate arrays and integrated circuits. Mixed Modeling Style is used while designing the ALU. Arithmetic and Logical Unit The ALU is a building block of any microprocessor or DSP that performs many arithmetic functions based on the control input selection. The ALU is the heart of a microprocessor and performs all the basic operations. Besides the main ALU there are separate units which work independent of the main ALU for performing secondary operations such as address computation. Such units are present in pipelined microprocessors wherein the extra hardware requirement is for achieving greater speed of operation. Most of the presentday microprocessors are based on pipelining. The ALU can perform basic arithmetic functions such as addition, subtraction etc and logic functions including add, subtract, logic AND, logic OR, and logic XOR. These various functions of the ALU are implemented using a set of functional units each implementing a function, these may also be done using sharing of same hardware with use of certain additional units like multiplexers. The ALU has 3 set of inputs signals and one output signal. Operands A and B are Corresponding Author*- B. Khaleelu Rehman 1

2 both 64 bits each. These are fed to these functional units along with select lines which decide the operation to be per-formed. Each combination of the select lines corresponds to one particular function. There are also some other output signals in the ALU, such as overflow, zero and negative. For executing an instruction in a microprocessor, the instruction is fetched in the first clock cycle using the instruction pointer and decoded. The control unit then calculates the memory addresses of the operands using ALU (or the additional unit as in pipe-lined architecture) using the offset obtained from the instruction, loads the address onto the address buses of the CPU and fetches the operands from their locations in memory (or registers or from instruction itself as in case of immediate addressing) and feeds them as inputs to the ALU through the system buses. Also, the control unit sets the select lines of the ALU depending on the operation to be performed; this information is obtained from the instruction itself. During the next clock cycle the ALU operates on the operands which it receives on the data buses of the CPU and produce the result. Also, depending on the result of the operation the flag register is set by the ALU. Next the result of operation is either stored to a register or written to the memory. Finally, the address of next instruction is calculated and execution proceeds in a similar manner as above. Implementation The design consists of four components such as basic ALU to perform logical and arithmetic operation, multiplication component to perform multiply operation, division component to perform division operation and multiplexer to select output of specific component to obtain final output. The top-level entity of design consists of two 64 Bit inputs A & B, 4 bit select lines to perform particular function on inputs to generate the final output. It also consists of clock, carry, enable and reset input. The final output is 128 bit. VHDL code for all the modules is written, simulated and synthesized using Xilinx ISE 10.1v. The target device chosen for the same is Spartan XC-3S The respective results of all the modules are shown below. The simulation result of basic ALU module is shown below. Simulation results for Increment, add With Carry (ADC) and SBB operation shown below: Fig. 1 Simulation result of Increment, DC and SSB operation Corresponding Author*- B. Khaleelu Rehman 2

2 Simulation result of DEC, AND and OR operation Fig.

3 The Simulation results for DEC, AND & OR operation is The Simulation results for XOR, NOT & Shift right operation is Fig. 2 Simulation result of DEC, AND and OR operation Fig. 3 Simulation result of XOR, NOT & Shift right operation Corresponding Author*- B. Khaleelu Rehman 3

4 Simulation result of shift left, shift right & rotate left Operation Fig.

4 The Simulation results for shift left, shift right & rotate left Operation is The simulation result of multiplication module is Fig. 4 Simulation result of shift left, shift right & rotate left Operation Fig. 5 Simulation result of multiplication module Operation Corresponding Author*- B. Khaleelu Rehman 4

The simulation result of division module is Fig. 6 Simulation result of division Operation After verification of all the modules, they are integrated in top level module using structural modelling.

5 The simulation result of division module is Fig. 6 Simulation result of division Operation After verification of all the modules, they are integrated in top level module using structural modelling. Then top level module is simulated & synthesized using Xilinx ISE tool. The final results of top level module for rotate left & multiplication operation is Fig. 7 Simulation result of top level module The device utilization summary of proposed ALU is shown in Table II. It shows efficient utilization of slices, slice flip-flops, IOBs, GCLKs and LUTs for implementation of ALU on FPGA device. Fig. 8 Device utilization summary Corresponding Author*- B. Khaleelu Rehman 5

C is the output, with N, Y, Z are the outputs as well. G is also the output.

6 Results Here, the image shows the RTL view of the ALU where S is the selection is the selection lines, A, B and C are 64 bit inputs. C is the output, with N, Y, Z are the outputs as well. G is also the output. The images are shown below- Fig. 9 RTL View Image Fig. 10 RTL View Image Expanded Corresponding Author*- B. Khaleelu Rehman 6

The wave form found for the ALU is: International Scientific Research Organization Journal Fig. 11 Output Waveform Conclusion The basic structure, and design procedure of VHDL are studied.

7 The wave form found for the ALU is: International Scientific Research Organization Journal Fig. 11 Output Waveform Conclusion The basic structure, and design procedure of VHDL are studied. Behavioral modelling & structural modelling are used for the implementation of 64 bit ALU. Logical operations are bit by bit operations & are implemented using simple gates which operate independent of each other. All the mathematical operations in the ALU are performed by means of repeated additions. Along with the basic operations of ALU multiplication and division are incorporated and designed as a single unit. [8] Digital Systems Design Using Table by Charles H. Roth Jr. [9] FPGA Prototyping with VHDL Examples by Pong. P chu. [10] Circuit Design With VHDL by Volnei A.Pedroni [11] Computer Organisation and Design by David A.Patterson and John L. References [1] VHDL Implementation Of 64-bit ALU by P Bhanusree, G Bhargav Sai, Y Ashwanth Kumar, K Sravan Kumar [2] Behavioral Design and Synthesis of 64 BIT ALU using Xilinx ISE by Rajib Chetia, Kaushik Chandra Deva Sarma, Gaurab Baruah [3] Design and Simulation of 64 bit ALU by Mukesh P. Mahajan, P. G. Salunke, Y. M. Gaikwad, V. P. Jagtap [4] Design of 64 Bit Low Power ALU For DSP Applications by Rajesh Pidugu, P. Ma-hesh Kannan [5] Design and Simulation of High Speed, less area 64- Bit ALU using Efficient Technique by Prof. Rajendra M. Rewatkar, Apurva V Khode, Ashwini S. Kalinkar, Padmaja S. Bangde, Shreya D. Potey [6] VHDL Programming by Douglas L Perry [7] Digital Logic and Microprocessor Design with VHDL by Enoch O. Hwang Corresponding Author*- B. Khaleelu Rehman 7

FPGA based Simulation of Clock Gated ALU Architecture with Multiplexed Logic Enable for Low Power Applications

IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 04, 2015 ISSN (online): 2321-0613 FPGA based Simulation of Clock Gated ALU Architecture with Multiplexed Logic Enable for