Table-based division by small integer constants

Transcription

1 Table-base ivision by small integer constants Florent e Dinechin, Laurent-Stéphane Diier LIP, Université e Lyon (ENS-Lyon/CNRS/INRIA/UCBL) 46, allée Italie, Lyon Ceex 07 Florent.e.Dinechin@ens-lyon.fr LIP6, Université Pierre et Marie Curie (UPMC/CNRS) 4 place Jussieu, Paris Ceex 05 Laurent-Stephane.Diier@upmc.fr Abstract. Computing cores to be implemente on FPGAs may involve ivisions by small integer constants in fixe or floating point. This article presents a family of architectures aressing this nee. They are erive from a simple recurrence whose boy can be implemente very efficiently as a look-up table that matches the harware resources of the target FPGA. For instance, ivision of a 32-bit integer by the constant 3 may be implemente by a combinatorial circuit of 48 LUT6 on a Virtex- 5. Other options are stuie, incluing iterative implementations, an architectures base on embee memory blocks. This technique also computes the remainer. An efficient implementation of the correctly roune ivision of a floating-point constant by such a small integer is also presente. 1 Introuction When porting applications to FPGAs, arithmetic operations shoul be optimize in an application-specific way whenever possible. This is the goal of the FloPoCo project [1]. This article consiers ivision by a small integer constant, an emonstrates operators for it that are more efficient than approaches base on stanar ivision [2] or on multiplication by the inverse [3, 4]. Division by a small integer constant is an operation that occurs often enough to justify investigating a specific operator for it. This work, for instance, was motivate by the Jacobi stencil algorithm, whose core computes the average of 3 values: this involves a ivision by 3. Small integer constants are quite common in such situations. Division by 5 also occurs in ecimal / binary conversions. The propose approach coul also be use to interleave memory banks in numbers that are not powers of two: if we have memory banks, an aress A must be translate to aress A/ in bank A mo. Division by a constant in a harware context has actually been stuie quite extensively [3, 5, 4], with goo surveys in [6, 7]. There are two main families of techniques: those base on aitions an subtractions, an those base on multiplication by the inverse. In this article we introuce a technique that has, to our knowlege, only been escribe in lecture notes as a general combinational

2 circuit example [8]. It is in essence a straightforwar aaptation of the paperan-pencil ivision algorithm in the case of small ivisors. The reason why this technique is not mentione in the literature is probably that the core of its iteration itself computes a (smaller) ivision: it oesn t reuce to either aitions, or multiplications. However, it is very well suite to FPGAs, whose logic is base on look-up tables (LUTs): they may implement such complex operations very efficiently, provie the size in bits of the input numbers matches the number of inputs to the harware LUTs. Let us introuce this technique with the help of usual ecimal arithmetic. Suppose we want to ivie an arbitrary number, say 776, by 3. Figure 1 escribes the paper-an-pencil algorithm in this case We first computes the Eucliean ivision of 7 by 3. This gives the first igit of the quotient, here 2, an the remainer is 1. We now have to ivie 176 by 3. In the secon iteration, we ivie 17 by 3: the secon quotient igit is 5, an the remainer is 2. The thir iteration ivies 26 by 3: the thir quotient igit is 8 an the remainer is 2, an this is also the remainer of the ivision of 776 by 3. Fig. 1. Division by 3 in ecimal The key observation is that in this example, the iteration boy consists in the Eucliean ivision of a 2-igit ecimal number by 3. The first of these two igits is a remainer from previous iteration: its value is 0, 1 or 2. We may therefore implement this iteration with a look-up table that, for each value from 00 to 29, gives the quotient an the remainer of its ivision by 3. This small look-up table will allow us to ivie by 3 numbers of arbitrary size. In Section 2 we aapt this raix-10 algorithm to a raix that is a power of two, then chose this raix so that the look-up table matches well the fine structure of the target FPGA. We stuy the case of floating-point inputs in Section 3: it is possible to ensure correct rouning to the nearest for free. Section 4 provies a few results an comparisons. 2 Eucliean ivision of an integer by a small constant 2.1 Notations Let be the constant ivisor, an let α be a small integer. We will use the representation of x in raix β = 2 α, which may also be consiere as breaking own the binary ecomposition of x into k chunks of α bits (see Figure 3): x = k 1 x i.2 αi where x i {0,..., 2 α 1} i=0 2

3 In all this section, we assume that is not a multiple of 2, as ivision by 2 resumes to a constant shift which is for free in FPGAs. 2.2 Algorithm The following algorithm computes the quotient q an the remainer r 0 of the high raix eucliean ivision of x by the constant. At each step of this algorithm, the partial ivien y i, the partial remainer r i an one raix-2 α igit of the quotient are compute. Algorithm 1 LUT-base computation of x/ 1: proceure ConstantDiv(x, ) 2: r k 0 3: for i = k 1 own to 0 o 4: y i x i + 2 α r i+1 (this + is a concatenation) 5: (q i, r i) ( y i/, y i mo ) (rea from a table) 6: en for 7: return q = k i=0 qi.2 αi, r 0 8: en proceure Theorem 1. Algorithm 1 computes the Eucliean ivision of x by. It outputs the quotient q = k i=0 q i.2 αi an the remainer r 0 so that x = q + r 0. The raix-2 α representation of the quotient q is also a binary representation, each iteration proucing α bits of this quotient. The proof of this theorem is in the appenix. The line y i x i + 2 α r i+1 is simply the concatenation of a remainer an a raix-2 α igit. Let us efine γ as the size in bits of the largest possible remainer: γ = log 2 ( 1) this is also the size of as is not a power of two. Then, y i is of size α + γ bits. The secon line of the loop boy, (q i, r i ) ( y i /, y i mo ), computes a raix-2 α igit an a remainer: it may be implemente as a look-up table with α + γ bits of input an α + γ bits of output (Fig. 2). Here, α is a parameter which may be chosen to match the target FPGA architecture, as we show below. The algorithm computes α bits of the quotient in one iteration: the larger α, the fewer iterations are neee for a given input number size n. The iteration may be implemente sequentially as epicte in Fig. 2, although in all the following we will focus on the fully unrolle architecture epicte in Fig. 3, which enables high-throughput pipeline implementations. It shoul be note that, for a given, the architecture grows linearly with the input size n, where general ivision or multiplication architectures grow quaratically. 3

4 reset r i+1 γ x i α LUT α q i clk r i γ Fig. 2. LUT-base sequential ivision by a constant of a raix-2 α igit extene by a remainer. r 4 = x 3 x 2 x 1 x 0 r 3 r 2 r 1 LUT LUT LUT LUT r 0 = r q 3 4 q 2 4 q 1 4 q 0 Fig. 3. LUT-base ivision by 3 of a 16-bit number written in raix 2 4 (α = 4, γ = 2) 2.3 Memory structures in current FPGAs Current FPGAs offer two main memory structures. The first is the 4- to 6- input LUT use in the logic fabric. In the following we note LUTk a k-bit input, 1-bit output LUT. In each FPGA family, there are restrictions on LUT utilization. Let us review recent FPGAs with the motivation to buil k-input, k-output LUTs. The Altera Stratix IV Aaptive Logic Moule (ALM) can be use as two arbitrary LUT4, but may also implement two LUT5 or two LUT6 uner the conition that they share some of their inputs. This is the case for our architectures: a 6-input, 6-output LUT may be built as 3 ALMs. In Xilinx Virtex-5 an Virtex-6, the logic slice inclues 4 registers an 4 LUT6, each of which is fractionable as two LUT5 with inepenent outputs. The sweet spot here is therefore to buil 5-input tables, unless we nee to register all the outputs, in which case 6-input tables shoul be preferre. We may use, for instance, 6-input LUTs to implement ivision by 3 (γ = 2) in raix 16 (α = 4). Implementing the core loop costs 6 LUTs (for a 6 bits in, 6 bits out table). The cost for a fully combinatorial (or unrolle) ivier by 3 on n bits is n/4 6 LUT6s, for instance 36 LUT6s for 24 bits (single precision), or 78 LUTs for 53 bits (ouble precision). The best shift-an-a algorithm to ate nees respectively 118 an 317 full-aers (FA), each FA consuming one LUT both in Xilinx an in Altera evices. The approach propose here is four times as efficient on ivision by 3. The larger, the more inefficient this approach becomes, as we nee more bits to represent the r i. For larger constants, a secon option is the embee memory block, from 9Kbits to 144 Kbits epening on the architecture. We will use them as

5 (9Kbits), (18Kbits or 36KBits) or (144 KBits). For ivision by 3, we may now use α = 7 to α = 11, but these larger memories also push the relevance of this technique to larger constants. These memories are not combinatorial, their inputs must be registere: they are best suite to either sequential, or unrolle but pipeline implementation. In the latter case, we may exploit the fact that all these embee memories are ual-porte: two iterations may be unrolle in one single memory block as epicte in Figure 4. Again for ivision by 3, exploiting the M9K blocks of a Stratix IV (using α = 7), a fully pipeline single-precision ivier by 3 coul be impemente in 2 M9K only (2*2*7=28 bits) an run in 4 cycles at the maximal practical spee supporte by these evices. We have no experimental ata to support these claims as we implemente only the logic-base iviers so far. Inee, results in Section 4 suggest that architectures base on embee RAMs woul not be very competitive. x 3 x 2 x 1 x 0 LUT LUT LUT LUT q 3 q 2 q 1 q 0 r Fig. 4. A pipeline ivier using two ual-porte embee RAMs 3 Division of a floating-point number by a small integer constant A floating-point input X is given by its mantissa m an exponent e: x = 2 e m with m [1, 2). Similarly, the floating-point representation of our integer ivisor is: = 2 s with [1, 2) with s = γ 1 if is not a power of two. As the mantissa has a fixe number of bits, its normalization an rouning have to be performe for almost each floating-point operation [9]. 5

6 3.1 Normalization Let us write the ivision x = m.2e = 2s m 2e s. As 2s m = m [0.5, 2), this is almost the normalize mantissa of the floatingpoint representation of the result: if m, then m [1, 2), the mantissa is correctly normalize an the floating-point number to be returne is ( 2 s ) m y = 2 e s where (z) enotes the IEEE-stanar rouning to nearest even of a real z. if m <, then m [0.5, 1), the mantissa has to be shifte left by one. Thus, the floating-point number to be returne is ( 2 s+1 ) m y = 2 e s 1. It can be observe that the comparison between m an is extremely cheap for small integers because has only γ non-zero bits. Thus, the comparison is reuce to the comparison of these γ bits to the leaing γ bits of m. As both m an have a leaing one, we nee a comparator on γ 1 bits. In terms of latency, this is a very small elay using fast-carry propagation. 3.2 Rouning Let us now aress the issue of correctly rouning the mantissa fraction. If we ignore the remainer, the obtaine result is the rouning towars zero of the floating-point ivision. To obtain correct rouning to the nearest, a first iea is to consier the final remainer. If it is larger than /2, we shoul roun up, i.e. increment the mantissa. The comparison to /2 woul cost nothing (actually the last table woul hol the result of this comparison instea of the remainer value), but this woul mean an aition of the full mantissa size, which woul consume some logic an have a latency comparable to the ivision itself, ue to carry propagation. A better iea is to use the ientity (z) = z + 1 2, which in our case becomes ( 2 s+ɛ ) m 2 s+ɛ m = s+ɛ m + /2 = 2 with ɛ being 0 if m, an 1 otherwise. In the floating-point context we may assume that is o, since powers of two are manage as exponents. Let us write = 2h + 1. We obtain ( 2 s+ɛ ) m 2 s+ɛ m + h = s+ɛ m + h = 2 6

7 so instea of aing a roun bit to the result, we may a h to the ivien before its input into the integer ivisor. It seems we haven t won much, but this pre-aition is actually for free: the aen h = 1 2 is an s-bit number, an we have to a it to the mantissa of x that is shifte left by s + ɛ bits, so it is a mere concatenation. Thus, we save the aer area an the carry propagation latency. ξ e m 1 m <? s s ftz Exn s 1 ov +1 h iv by ξ e m Fig. 5. Floating-point ivision by a small constant. To sum up, the management of a floating-point input as to the area an latency of the mantissa ivier those of one (small) exponent aer, an of one (large) mantissa multiplexer, as illustrate by Figure 5. On this figure, ξ is a 2-bit exception vector use to represent 0, ± an NaN (Not a Number). The implementation in FloPoCo manages ivisions by small integer constants an all their powers of two. The only aitional issues are in the overflow/unerflow logic (the Exn box on Figure 5), but they are too straightforwar to be etaile here. 4 Results an comparison All the results in this section are obtaine for architectures generate by FloPoCo 2.3.0, using ISE 12.1 for an FPGA with 6-input LUTs (Virtex-5). These are synthesis results before place an route, which is perfectly meaningful for such tiny operators. Table 1 provies some results for Eucliean ivision (integer ivision with remainer). We only report the architecture obtaine with the optimal value of α. 7

8 n = 32 bits n = 64 bits constant LUT6 (preicte) latency LUT6 (preicte) latency = 3 (α = 4, γ = 2) 47 (6*8=48) 7.14ns 95 (6*16=96) 14.8ns = 5 (α = 3, γ = 3) 60 (6*11=66) 6.79ns 125 (6*22=132) 13.8ns = 7 (α = 3, γ = 3) 60 (6*11=66) 7.30ns 125 (6*22=132) 15.0ns Table 1. Synthesis results for combinatorial Eucliean ivision on Virtex Integer ivision One woul believe that for such simple architectures, we can preict the synthesis results, at least with respect to LUT count. However, there are still some surprises, which we are currently investigating. The first surprise is that the synthesis tools perform further optimization out of our esigns: the LUT numbers are not always those preicte (they are always better). For instance, for the 64-bit ivier by 3, we preict simply 96 LUT6, but the tool reports 15 LUT3, 18 LUT4, 16 LUT5, an only 45 LUT6, then merges that into 95 LUTs. One of the reasons coul be that some remainer values never occur, which means that there are on t care in the logic tables that enable further optimizations. This woul explain that the results are better for ivision by 5 than for ivision by 7 although they have the same α an β: there are more on t care in the table for 5. Such improvements shoul be stuie systematically. Also, we have mentione earlier that the sweet spot on Virtex-5 shoul be to use 5-input LUTs, but the synthesis tools seem to ecie otherwise: architectures esigne for 5-input LUTs actually consume more than those esigne for 6-input LUTs. This coul come from a coing style issue, or from a misunerstaning of the intricate etails of the Virtex-5 logic block. Table 2 provies some synthesis results for pipeline iviers by 3. Each line is a ifferent frequency/area traeoff (incientally, thanks to FloPoCo s pipelining framework [1], this flexible pipeline took less than ten minutes to implement out of the combinatorial esign). Here we have to investigate why the LUT number is larger than the preicte size. n = 32 bits n = 64 bits FF + LUT6 performance FF + LUT6 performance 33 Reg + 47 LUT MHz 122 Reg LUT MHz 58 Reg + 62 LUT MHz 168 Reg LUT MHz 68 Reg + 72 LUT MHz 172 Reg LUT MHz Table 2. Synthesis results for pipeline Eucliean ivision by 3 on Virtex-5 8

9 4.2 Floating-point ivision Table 3 shows results for floating-point ivision by 3. The behaviour of these operators, incluing the fact that they return correctly roune results, has been verifie by simulation against millions of test vectors generate by an inepenent floating-point ivision by 3 [1]. single precision ouble precision FF + LUT6 performance FF + LUT6 performance 35 Reg + 69 LUT MHz 122 Reg LUT MHz 105 Reg + 83 LUT MHz 245 Reg LUT MHz Table 3. Synthesis results for pipeline floating-point ivision by 3 on Virtex-5 For comparison, a single precision stanar (non-constant) floating-point ivier consumes 1122 reg an 945 LUT an nees MHz. 4.3 Comparison with previous work A review of several algorithms for ivision by a constant is available in [6]. Many of these algorithms require the ivision to be exact (null remainer) an return wrong results otherwise. We will not consier them. Among the remaining techniques, the most relevant is metho 6 in [6]. In this metho, the ivisor has the form 2 t ± 1, which correspons to most of the small ivisors we are targeting. The quotient an the remainer are obtaine through n γ 1 aitions an substractions involving n-bit numbers. Table 4 summarizes the comparison of the size of our implementation an an estimation of the area of an FPGA implementation of this previous technique. It can be observe that in this implementation, the larger, the fewer require aitions, therefore the smaller the implementation. This means that this metho is increasingly relevant for larger constants 2 t ±1, an this is a metho to investigate in the future. Our proposition remains very significally smaller for the small ivisors that it targets. Besies, it oesn t involve any carry propagation, so its latency shoul also be better, but this remains to be quantifie experimentally. n = 16 bits n = 32 bits n = 64 bits Constant Our [6] Our [6] Our [6] Table 4. Comparison of the size in LUT between the implementation of our ivier an [6] on Virtex 5 9

10 The presente floating-point ivision by a small constant also largely outperforms the best technique use so far, which are base on multiplication by the constant 1/ using shift-an-a algorithm [4]. For instance, using this technique, a ouble-precision multiplication by 1/3, in the conitions of Table 3, consumes 282 reg LUT an runs in MHz. 5 Conclusion This article as ivision by a small integer constant such as 3 or 10 to the bestiary of arithmetic operators that C-to-harware compilers can use when they target FPGAs. This operation can be implemente very efficiently, be it for integer inputs, or for floating-point inputs. It is now part of the open-source FloPoCo generator. Some synthesis results suggest that a careful stuy of the tables coul lea to further optimizations. In aition, we shoul try to reformulate our tables so that the propagation of the r i uses the fast-carry lines available on all moern FPGAs: this woul reuce the latency ramatically. Another issue worth of interest is the case of larger constants that are prouct of smaller constants, for which a cascae implementation coul be stuie. Due to routing pressure, the number of inputs to the FPGA LUTs keeps increasing as technology progresses. This shoul make this technique increasingly relevant in the future. References 1. F. e Dinechin an B. Pasca, Designing custom arithmetic ata paths with FloPoCo, IEEE Design & Test of Computers, vol. 28, no. 4, Aug M. D. Ercegovac an T. Lang, Digital Arithmetic. Morgan Kaufmann, E. Artzy, J. A. Hins, an H. J. Saal, A fast ivision technique for constant ivisors, Communications of the ACM, vol. 19, pp , Feb F. e Dinechin, Multiplication by rational constants, IEEE Transactions on Circuits an Systems, II, 2012, to appear. 5. S.-Y. R. Li, Fast constant ivision routines, IEEE Transactions on Computers, vol. C-34, no. 9, pp , Sep P. Srinivasan an F. Petry, Constant-ivision algorithms, IEE Proc. Computers an Digital Techniques, vol. 141, no. 6, pp , Nov R. W. Doran, Special cases of ivision, Journal of Universal Computer Science, vol. 1, no. 3, pp , A. Paplinski, CSE2306/1308 Digital Logic Lecture Note, Lecture 8, Clayton School of Information Technology Monash University, Australia, J.-M. Muller, N. Brisebarre, F. e Dinechin, C.-P. Jeannero, V. Lefèvre, G. Melquion, N. Revol, D. Stehlé, an S. Torres, Hanbook of Floating-Point Arithmetic. Birkhauser Boston,

11 A Proof of correctness of Algorithm 1 The proof procees in two steps. First, we establish that x = k i=0 q i.2 αi +r 0 in lemma 1 below. This shows tha we compute some kin of Eucliean ivision, but it is not enough: we also nee to show that the q i form a binary representation of the result. For this it is enough to show that they are raix-2 α igits, which is establishe thanks to lemma 2 below. Lemma 1. k x = q i.2 αi + r 0 i=0 Proof. To show this lemma, we use the efinition of the Eucliean ivision of y i by : y i = q i + r i. x = k 1 i=0 x i.2 αi = k 1 i=0 (x i + 2 α r i+1 ).2 αi k 1 i=0 (2α r i+1 ).2 αi = k 1 i=0 (q i + r i ).2 αi k i=1 r i.2 αi = k 1 i=0 q i.2 αi + r 0 r k.2 αk Lemma 2. i 0 y i 2 α 1 an r k = 0. Proof. The igit x i verifies by efinition 0 x i 2 α 1; r i+1 is either 0 (initialization) or the remainer of a ivision by, therefore 0 r i 1. Therefore y i = x i +2 α r i+1 verifies 0 y i 2 α 1+2 α ( 1), or 0 y i 2 α 1. We euce from the previous lemma an the efinition of q i as quotient of y i by that i 0 q i 2 α 1 which shows that the q i are inee raix-2 α igits. Thanks to Lemma 1, they are the igits of the quotient. 11