Computer Organization

Transcription

1 Computer Organization Douglas Comer Computer Science Department Purue University 250 N. University Street West Lafayette, IN Copyright All rights reserve. This ocument may not be reprouce by any means without written consent of the author.

2 V Processor Types An Instruction Sets CS Chapt

3 What Instructions Shoul A Processor Offer? Minimum set is sufficient, but inconvenient Extremely large set is convenient, but inefficient Architect must consier aitional factors Physical size of processor Expecte use Power consumption CS Chapt

4 The Point About Instruction Sets The set of operations a processor provies represents a traeoff among the cost of the harware, the convenience for a programmer, an engineering consierations such as power consumption. CS Chapt

5 Representation Architect must choose Set of instructions Exact representation harware uses for each instruction (instruction format) Precise meaning when instruction execute Above items efine the instruction set CS Chapt

6 Parts Of An Instruction Opcoe specifies instruction to be performe Operans specify ata values on which to operate Result location specifies where result will be place CS Chapt

7 Instruction Format Instruction represente as binary string Typically Opcoe at beginning of instruction Operans follow opcoe CS Chapt

8 Illustration Of Typical Instruction Format opcoe operan 1 operan 2... CS Chapt

9 Instruction Length Fixe-length Every instruction is same size Harware is less complex Harware can run faster Variable-length Some instructions shorter than others Appeals to programmers More efficient use of memory CS Chapt

10 The Point About Fixe-Length Instructions When a fixe-length instruction set is employe, some instructions contain extra fiels that the harware ignores. The unuse fiels shoul be viewe as part of a harware optimization, not as an inication of a poor esign. CS Chapt

11 General-Purpose Registers High-spee storage evice Typically part of the processor Each register small size (typically, each register can accommoate an integer) Basic operations are fetch an store Numbere from 0 through N 1 Many processors require operans for arithmetic operations to be place in general-purpose registers CS Chapt

12 Floating Point Registers Usually separate from general-purpose registers Each hols one floating-point value Many processors require operans for floating point operations to be place in floating point registers CS Chapt

13 Example Of Programming With Registers A X an Y, an place result in Z Steps Loa a copy of X into register 3 Loa a copy of Y into register 4 A the value in register 3 to the value in register 4, an irect the result to register 5 Store a copy of the value in register 5 in Z Note: assumes registers 3, 4, an 5 are free CS Chapt

14 Terminology Register spilling Refers to placing current contents of registers in memory for later recall Occurs when registers neee for other computation Register allocation Choose which values to keep in registers at any time Programmer or compiler ecies CS Chapt

15 Double Precision Refers to value that is twice as large as usual Harware often uses a contiguous pair of registers to hol a ouble precision value CS Chapt

16 Register Banks Registers partitione into isjoint sets calle banks Aitional harware etail Optimizes performance Complicates programming CS Chapt

17 Register Banks Registers partitione into isjoint sets calle banks Aitional harware etail Optimizes performance Complicates programming CS Chapt

18 Typical Register Bank Scheme Registers ivie into two banks ALU instruction that takes two operans must have one operan from each bank Programmer s responsibility CS Chapt

19 Illustration Of Register Banks Bank A Bank B separate harware units use to access the register banks Processor Both banks can be accesse simultaneously CS Chapt

20 Consequence For Programmers Operans must be assigne to banks Even trivial programs cause problems Example R X + Y S Z - X T Y + Z CS Chapt

21 Register Conflicts Occur when operans specify same register bank Reporte by compiler / assembler Can require programmer to copy values to opposite register bank CS Chapt

22 Types Of Instruction Sets Two basic forms Complex Instruction Set Computer (CISC) Reuce Instruction Set Computer (RISC) CS Chapt

23 CISC Instruction Set Many instructions (often hunres) Given instruction can require arbitrary time to compute Examples of CISC instructions Move graphical item on bitmappe isplay Memory copy or clear Floating point computation CS Chapt

24 RISC Instruction Set Few instructions (typically 32 or 64) Each instruction executes in one clock cycle Example: MIPS instruction set CS Chapt

25 Summary Of Instruction Sets A processor is classifie as CISC if the instruction set contains instructions that perform complex computations that can require long times; a processor is classifie as RISC if it contains a small number of instructions that can each execute in one clock cycle. CS Chapt

26 Execution Pipeline Harware optimization technique Allows processor to complete instructions faster Typically use with RISC instruction set CS Chapt

27 Typical Instruction Cycle Fetch the next instruction Examine the opcoe to etermine how many operans are neee Fetch each of the operans (e.g., extract values from registers) Perform the operation specifie by the opcoe Store the result in the location specifie (e.g., a register) CS Chapt

28 To Optimize Instruction Cycle Buil separate harware block for each step Arrange to pass instruction through sequence of harware blocks CS Chapt

29 Illustration Of Execution Pipeline stage 1 stage 2 stage 3 stage 4 stage 5 fetch instruction examine opcoe fetch operans perform operation store result Example pipeline has five stages CS Chapt

30 Pipeline Spee All stages operate in parallel Given stage can start to process a new instruction as soon as current instruction finishes Effect: N-stage pipeline can operate on N instructions simultaneously CS Chapt

31 Illustration Of Instructions In A Pipeline clock stage 1 stage 2 stage 3 stage 4 stage 5 Time 1 2 inst. 1 inst. 2 - inst inst. 3 inst. 2 inst inst. 4 inst. 3 inst. 2 inst. 1-5 inst. 5 inst. 4 inst. 3 inst. 2 inst. 1 6 inst. 6 inst. 5 inst. 4 inst. 3 inst. 2 7 inst. 7 inst. 6 inst. 5 inst. 4 inst. 3 8 inst. 8 inst. 7 inst. 6 inst. 5 inst. 4 CS Chapt

32 RISC Processors An Pipelines Although a RISC processor cannot perform all steps of the fetch-execute cycle in a single clock cycle, an instruction pipeline with parallel harware provies approximately the same performance: once the pipeline is full, one instruction completes on every clock cycle. CS Chapt

33 Using A Pipeline Pipeline is transparent to programmer Disavantage: programmer who oes not unerstan pipeline can prouce inefficient coe Reason: harware automatically stalls pipeline if items are not available CS Chapt

34 Example Of Instruction Stalls Assume Nee to perform aition an subtraction operations Operans an results in registers A through E Coe is: Instruction K: Instruction K+1: C a A B D subtract E C Secon instruction stalls to wait for operan C CS Chapt

35 Effect Of Stall On Pipeline clock stage 1 stage 2 stage 3 stage 4 stage 5 Time 1 2 inst. K inst. K+1 inst. K-1 inst. K inst. K-2 inst. K-1 inst. K-3 inst. K-2 inst. K-4 inst. K-3 3 inst. K+2 inst. K+1 inst. K inst. K-1 inst. K-2 4 inst. K+3 inst. K+2 (inst. K+1) inst. K inst. K (inst. K+1) - inst. K inst. K inst. K+4 inst. K+3 inst. K+2 inst. K+1-8 inst. K+5 inst. K+4 inst. K+3 inst. K+2 inst. K+1 Bubble passes through pipeline CS Chapt

36 Potential Causes Of A Pipeline Stall Access external storage Invoke a coprocessor Branch to a new location Call a subroutine CS Chapt

37 Achieving Maximum Spee Program must be written to accommoate instruction pipeline To minimize stalls Avoi introucing unnecessary branches Delay references to result register(s) CS Chapt

38 Example Of Avoiing Stalls C a A B C a A B D subtract E C F a G H F a G H M a K L J subtract I F D subtract E C M a K L J subtract I F P subtract M N P subtract M N (a) (b) Stalls eliminate by rearranging (a) to (b) CS Chapt

39 A Note About Pipelines Although harware that uses an instruction pipeline will not run at full spee unless programs are written to accommoate the pipeline, a programmer can choose to ignore pipelining an assume the harware will automatically increase spee whenever possible. CS Chapt

40 No-Op Instructions Have no effect on Registers Memory Program counter Computation Can be inserte to avoi instruction stalls Often use by a compiler CS Chapt

41 Use Of No-OP Example Instruction K: C a A B Instruction L+1: no-op Instruction K+2: D subtract E C No-op allows time for result from register C to be fetche for subtract operation CS Chapt

42 Forwaring Harware optimization to avoi stall Allows ALU to reference result in next instruction Example Instruction K: C a A B Instruction K+1: D subtract E C Forwaring harware passes result of a operation irectly to next instruction CS Chapt

43 Types Of Operations One possible categorization Arithmetic instructions (integer arithmetic) Logical instructions (also calle Boolean) Data access an transfer instructions Conitional an unconitional branch instructions Floating point instructions Processor control instructions CS Chapt

44 Program Counter Harware register Use uring fetch-execute cycle Gives aress of next instruction to execute Also known as instruction pointer CS Chapt

45 Fetch-Execute Algorithm Details Assign the program counter an initial program aress. Repeat forever { Fetch: access the next step of the program from the location given by the program counter. Set an internal aress register, A, to the aress beyon the instruction that was just fetche. Execute: Perform the step of the program. Copy the contents of aress register A to the program counter. } CS Chapt

46 Branches An Fetch Execute Absolute branch Typically name jump Operan is an aress Assigns operan to internal register A Relative branch Typically name br Operan is a signe value Operan is ae to internal register A CS Chapt

47 Subroutine Call Jump subroutine (jsr instruction) Similar to a jump Saves value of internal register A Replaces A with operan aress Return from subroutine (ret instruction) Retrieves value save uring jsr Replaces A with save value CS Chapt

48 Passing Arguments Multiple methos have been use Examples Store arguments in memory Store arguments in special-purpose harware registers Store arguments in general-purpose registers Many techniques also use to return result from function CS Chapt

49 Register Winow Harware optimization for argument passing Processor contains many general-purpose registers Small subset of registers visible at any time Caller places arguments in reserve registers During proceure call, register winow moves CS Chapt

50 Illustration Of Register Winows current registers 0-7 when subroutine runs x 1 x 2 x 3 x 4 A B C D l 1 l 2 l 3 l 4 registers 0-7 when program runs CS Chapt

51 Example Instruction Set Known as MIPS instruction set Early RISC esign Minimalistic CS Chapt

52 MIPS Instruction Set (Part 1) Instruction Meaning Arithmetic a integer aition subtract integer subtraction a immeiate integer aition (register + constant) a unsigne unsigne integer aition subtract unsigne unsigne integer subtraction a immeiate unsigne unsigne aition with a constant move from coprocessor access coprocessor register multiply integer multiplication multiply unsigne unsigne integer multiplication ivie integer ivision ivie unsigne unsigne integer ivision move from Hi access high-orer register move from Lo access low-orer register Logical (Boolean) an logical an (two registers) or logical or (two registers) an immeiate an of register an constant or immeiate or of register an constant shift left logical Shift register left N bits shift right logical Shift register right N bits CS Chapt

53 MIPS Instruction Set (Part 2) Instruction Meaning Data Transfer loa wor loa register from memory store wor store register into memory loa upper immeiate place constant in upper sixteen bits of register move from coproc. register obtain a value from a coprocessor Conitional Branch branch equal branch if two registers equal branch not equal branch if two registers unequal set on less than compare two registers set less than immeiate compare register an constant set less than unsigne compare unsigne registers set less than immeiate compare unsigne register an constant Unconitional Branch jump go to target aress jump register go to aress in register jump an link proceure call CS Chapt

54 MIPS Floating Point Instructions Instruction Meaning Arithmetic FP a FP subtract FP multiply FP ivie FP a ouble FP subtract ouble FP multiply ouble FP ivie ouble floating point aition floating point subtraction floating point multiplication floating point ivision ouble-precision aition ouble-precision subtraction ouble-precision multiplication ouble-precision ivision Data Transfer loa wor coprocessor store wor coprocessor loa value into FP register store FP register to memory Conitional Branch branch FP true branch FP false FP compare single FP compare ouble branch if FP conition is true branch if FP conition is false compare two FP registers compare two ouble precision values CS Chapt

55 Aesthetic Aspects Of Instruction Sets Elegance Balance No frivolous or useless instructions Orthogonality No unnecessary uplication No overlap among instructions CS Chapt

56 Principle Of Orthogonality The principle of orthogonality specifies that each instruction shoul perform a unique task without uplicating or overlapping the functionality of other instructions. CS Chapt

57 Conition Coes Harware bits Set by ALU Teste in conitional branch instruction CS Chapt

58 Example Of Conition Coe cmp r4, r5 # compare regs. 4 & 5, an set conition coe be lab1 # branch to lab1 if con. coe specifies equal mov r3, 0 # place a zero in register 3 lab1:...program continues at this point CS Chapt

59 Questions?