Advanced Microprocessors

Transcription

1 Advanced Microprocessors Notes #2 Software Architecture & Instruction Set Architecture Part 1 EE 467/567 Winter 2012 by Avinash Kodi SWA.1 Background Materials Textbook: 2.1, 2.2, 3.1 Other: IA-32 Intel Architecture Software Developer s Manual Volume 1: Basic Architecture Sections 3.4.1, 3.4.2, 3.4.3, 3.5 IA-32 Intel Architecture Software Developer s Manual Volume 3A: System Programming Guide Sections 3.1, 3.2, 3.3, 3.4, SWA.2 1

2 Computer Architecture Software Application Operating System Compiler & Assembler Control Unit Program Storage Data Storage Memory Hardware Datapath Input Output Micro Processor Unit (MPU) Input/Output (I/O) SWA.3 Software Architecture Basic Hardware Knowledge the User (Programmer) Needs to Program Assembly Registers, Instruction Set Architecture, Addressing Modes, SWA.4 2

3 Datapath Address Bus 20 General Registers AH BH CH DH SP AL BL CL DL Registers CS Data Bus 16 BP DI SS SI ES ALU Data Bus 16 IP Internal Communications Registers Bus Control Logic 8086 Bus Temporary Registers Control Unit ALU EU Control System Q Bus Flags Execution Unit (EU) Bus Interface Unit (BIU) Intel 8086 SWA.5 Intel Evolution Internal Data Bus Pentium P Pro P II P III Year Introduced Clock rate (Hz) # Transistors Physical Memory Internal Data Bus External Data Bus Address Bus Data type (bits) G 4.5k 6.5k 29k 29k 130k 275k 1.2M 3.1M 5.5M 7.5M 8.2M 64k 64k 1M 1M 16M 4G 4G 4G 64G 64G 64G ,16 8,16 8,16 8,16,32 8,16,32 8,16,32 8,16,32 8,16,32 8,16,32 SWA.6 3

4 Software Architecture Register Width IA-16 & IA bits 32-bits AH AL AX AH AL EAX General Purpose Registers (GP) Segment Registers BH BL CH CL DH DL SP BP DI SI CS SS ES IP FLAGS BX CX DX code segment data segment stack segment extra segment BH CH DH EIP EFLAGS SP BP DI SI CS SS ES FS GS BL CL DL EBX ECX EDX ESP EBP EDI ESI Pentium Pentium Pro Pentium II Pentium III Pentium 4 Pentium 4 HT Pentium M Pentium D Core Core 2 16-bit Architectures 32-bit Architectures SWA.7 SWA.8 4

5 Software Architecture Register Width IA-64 (EMT*) 64-bits EAX RAX EBX RBX ECX RCX General Purpose Registers (GP) R8 R9 EDX ESP EBP EDI ESI RDX RSP RBP RDI RSI R14 R15 RIP EFLAGS Xeon Extreme Edition Pentium 4 Core 2 *EMT = Extended memory 64 Technology SWA.9 Software Architecture Register Width IA-64 (Itanium) 64-bits General Registers GR0 GR1 GR2 GR3 GR4 GR5 GR6 GR7 GR126 GR127 Instruction Bundle Itanium 128-bits SWA.10 5

6 Software Architecture Register Width AMD64 64-bits EAX RAX EBX RBX ECX RCX General Purpose Registers R8 R9 EDX ESP EBP EDI ESI RDX RSP RBP RDI RSI R14 R15 RIP EFLAGS AMD64 SWA.11 Instruction Pointer Contains the address of the next word/byte of instruction code to be fetched from the current code segment of memory, SWA.12 6

7 Intel Evolution Internal Data Bus Pentium P Pro P II P III Year Introduced Clock rate (Hz) # Transistors Physical Memory Internal Data Bus External Data Bus Address Bus Data type (bits) G 4.5k 6.5k 29k 29k 130k 275k 1.2M 3.1M 5.5M 7.5M 8.2M 64k 64k 1M 1M 16M 4G 4G 4G 64G 64G 64G ,16 8,16 8,16 8,16,32 8,16,32 8,16,32 8,16,32 8,16,32 8,16,32 SWA.13 Software Architecture Address Space Address Bus CPU For example: For example: 80x86 20 bit wide address bus 2 20 = 1MBytes Pentium II 36 bit wide address bus 2 36 = 64GBytes The physical address space is defined as the range of addresses that the processor can generate on its address bus. SWA.14 7

8 Software Architecture Example AX BX CX DX IP CS SS ES AH AL BH BL CH CL DH DL SP BP SI DI FLAGS FFFFF 16 External memory Address space Code segment (64 k) Data segment (64 k) Stack segment (64 k) Extra segment (64 k) IP = Instruction Pointer SP = Stack Pointer BP = Base Pointer SI = Source Index DI = Data Index SR = Status Register Memory Address Space: FFFFF = 1,048,576 bytes (1 Mbyte) Input / Output address space FFFF SWA.15 Data Storage Address Memory (Binary) Memory (Hexadecimal) 0062A Nibble Byte Word Double word 4 bits 8 bits 16 bits (2 bytes) 32 bits (4 bytes) Memory (Hexadecimal) Word { Most significant byte Least significant byte } Word: Word: two consecutive bytes Word { 47 3F Most significant byte Least significant byte } Word: 473F 16 Decreasing addresses (same for double words) SWA.16 8

9 Data Storage Endians Big Endian: Least Significant higher address Most Significant lower address Little Endian: Least Significant lower address Most Significant higher address Little Endian processors: Intel 80x86, Pentium II/III/IV, VAX, Alpha Big Endian processors: 680x0, Sun SPARC PowerPC: Alter the Endian-ness using instructions SWA.17 Aligned and Misaligned Data Data words: Data double words: Aligned Words Misaligned Words Aligned Double Words Byte Byte F E D C B A 1 6 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Word 6 Word 4 Word 2 Word 0 Word 5 Word 3 Word 1 Aligned byte: Least Significant Byte at an even address Misaligned byte: Least Significant Byte at an odd address 0062F E D C B A Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 Double Word 4 Double Word 0 Double Word 5 Double Word 1 Double Word 2 Misaligned Double Words Double Word 3 SWA.18 9

10 Examples Address Memory (Hexadecimal) Instruction 1: read a address A A A7 C E Instruction 2: read a double address D Instruction 3: read a address SWA.19 Memory Management Addressing Methodologies Real Mode Logical Address Physical Address Space Segment register Offset (4 nibbles) 0 0 nibble + Segment Physical Address Segment Base Address Segment Register : Offset SWA.20 10

11 Real Mode Addresses Example: The Old 8086 Physical address: 20-bit value (remember: 20-bit address bus) Logical address: 16-bit base pointer (CS,SS,,ES) + an offset (IP, SP, BP, SI, DI) How do we obtain a physical address from the logical address: Notation: segment register : offset Offset value* 0 Segment Register Example: = 123A 16 = 123AH BX = = 2234H Logical Address: :BX Adder bit Physical memory Address Physical address: :BX = 123AH:2234H = 123A0H H = 145D4H *a.k.a. displacement SWA.21 Memory Management Segments 8086/8088 Segments are 2 16 = 64kbytes Note that segment can be contiguous, adjacent, disjointed, and overlapping. Fully Overlapped Partially Overlapped Contiguous Segment D Segment C Disjoint Logical segments Segment A Segment B Segment E Physical memory SWA.22 11

12 Logical Address Segment Selector Offset (8 nibbles) Memory Management Segmentation IA-32 Linear Address Space + Segment Linear Address Segment Base Address Segment Table (Global or Local Descriptor Table) (located in memory) SWA.23 Memory Management Protected-Mode Protected-Mode operation allows memory above the first 1Mbytes to be accessed by the through the latest Pentium, Protected-mode introduces protection: 8088/86 is unable to block general functions from accessing the kernel of the operating system (a program can go from any code segment to any other code segment). In protected mode the OS is given a mechanism to prevent the user from accidentally taking over the core of the OS and thus crashing your computer. SWA.24 12

13 Memory Management Paging Linear Address Directory Table Offset Page Tables + Physical Address Space Page Page Directory Phys. Address Entry Entry Page Directory Base Address (from CR3) SWA.25 Memory Management Segmentation & Paging IA-32 Logical Address Linear Address Selector Offset Directory Table Offset Physical Address Space + Page Tables + Page Page Directory Phys. Address Entry Entry Segment Table (Global or Local Descriptor Table) (located in memory) Page Directory Base Address (from CR3) Segmentation Paging SWA.26 13

14 Instruction Set Architecture SWA.27 Programming Languages Source Code: High-level Language (C, C++, Pascal, BASIC,FORTRAN) Assembly Language Compile & Link Assemble Tool: Compiler & Linker Tool: Assembler Machine Code (Bytes stored in memory) Machine Code (Bytes stored in memory) A mix of assembly and a high-level language can be used: inline-assembly SWA.28 14

15 Assembly Language Assembly Statements Mnemonic Label Argument Comments START: MOV AX,34EH ; Move 34EH into the AX register MOV DX,[1234H] ; Move the contents of the memory location ; with offset 1234H into the DX register ADD DX,AX ; Add AX to DX and store the result into DX END MOV AX, 34EH Destination Source SWA.29 Register Transfer Language (RTL) Intro RTL is machine independent!!!! ( ) = Contents of = Move operand on right-hand-side source to the left-hand-side destination & = AND = OR ^ = Exclusive-OR + = Addition - = Subtraction * = Multiplication / = Division VHDL and Verilog are also machine independent description languages but they differ from RTL SWA.30 15

16 Assembly Language Assembly Statements - RTL START: MOV AX, 34EH AX 34Eh MOV DX, [1234H] DX (1234h) Effective Address 1234h ADD DX, AX DX (DX) + (AX) SWA.31 Machine Code Listing Address Program bytes in memory 00C00 B8 4E 03 START: MOV AX,34EH 00C03 8B MOV DX,[1234H] 00C07 01 C2 ADD DX,AX END Byte located at memory location (ML) 00C05 16 Generated automatically by the Assembler or manually using the instruction information sheets as can be found in Volumes 2a and 2b. SWA.32 16

17 Machine Code In Memory Assembly will be converted to machine code for machine interpretation. As a result the program consists of a bunch of bytes in memory! A x86 Assembly RTL mov ax,[1234] ax ( ) D E mov bx,[0456] bx ( ) A B B D8 16 inc ax ax (ax) + 1 dec bx bx (bx) - 1 add ax,bx ax (ax) + (bx) 0063C D E OF 16 OF 16 and ax,0f0f ax (ax) & 0F0F 16 SWA.33 Instruction Set Architecture IA-32 General purpose Arithmetic, Logic, Shift Control and Branch, Data movement. FPU MMX SSE extensions SSE2 extensions SSE3 extensions SSE4 extensions System instructions IA-32 Intel Architecture Software Developer s Manual Volumes 2a & 2b SWA.34 17

18 The Elements of an Instruction Operation code (opcode): Binary code that specifies the operation to be performed. Operands Source operand reference: Operand that is the input for the operation Result (destination) operand reference: Operand that is the result for the operation Next instruction reference: Tells the CPU where to fetch the next instruction SWA.35 The Elements of an Instruction MOV CX, [013AH] Mnemonic Destination Source RTL: CX (0123A) or Text: Move the contents of address :013A to register CX SWA.36 18

19 IA-32 Intel Architecture Software Developer s Manual, Volume 2a, pp SWA.37 The operands can be: Addresses Register contents Numbers Integer or fixed-point Floating point Decimal Characters ASCII etc. Logical data The Operand SWA.38 19

20 Operands IA-32 Intel Architecture Software Developer s Manual, Volume 2a, pp SWA.39 Addressing Modes Memory Addressing Modes Immediate Register Direct Register Indirect Based Indexed Based-Indexed Scaled Based-Indexed SWA.40 20

21 Instructions Immediate & Register Addressing Immediate Addressing The source or destination field is the operand Examples: MOV AX,88 AX 88 Note: CS cannot be used as the destination Register* Addressing The source or destination field is a register Examples: MOV AX,88 (Intel) AX 88 *Also register direct addressing SWA.41 Instructions Register Indirect & Direct Addressing Register Indirect Addressing The source or destination address is stored in a register. Examples: MOV [BX],CL (Intel) :(BX) (CL) Direct* Addressing The source or destination address is explicitly given Examples: MOV [124A],CL (Intel) :124A (CL) *Also displacement addressing SWA.42 21

22 Instructions Based & Indexed Addressing* Based Addressing The source or destination address is determined by the contents of a base register plus an absolute displacement Examples: MOV [BX]+0123H,CL :(BX)+0123H (CL) Indexed Addressing The source or destination address is determined by the contents of a index register plus an absolute displacement Examples: MOV [DI]+0123H,CL :(DI)+0123H (CL) *these are forms of so-called relative addressing SWA.43 Instructions Based - Indexed Addressing* Based Indexed Addressing The source or destination address is determined by the contents of a base register plus the contents of an index register plus an absolute displacement Examples: MOV [BX][SI]+0123H,CL :(BX)+(SI)+0123H (CL) *these are forms of so-called relative addressing SWA.44 22

23 Addressing Effective Address Effective Address: Offset within a segment Example 1: MOV AX, [BX]+123H -> (BX)+123H is the effective address or offset within the data segment (). Example 2: ADD CX, [BP][SI]+12H -> (BP+SI)+12H is the effective address or offset within the stack segment (SS). One can override the default segment by explicitly indicating the segment within which the data can be found. Example 3: MOV AX, ES:[BX]+123H -> (BX)+123H is the effective address or offset within the extra segment (ES). SWA.45 Addressing Effective Address/Offset Segment Base Index Displacement CS SS ES : none BP SI 8- bits BX DI 16 - bits (a) 16-bit x86 Architectures Segment Base ( Index * Scale) Displacement CS SS ES FS GS ( E) AX ( E) AX ( E) CX ( E) CX ( E) DX 1 none ( E) DX ( E) BX 2 8 bits : ( E) BX * ( E) SP 4 16 bits ( E) BP ( E) BP 8 32 bits ( E) SI ( E) SI ( E) DI ( E) DI (a) 32-bit x86 Architectures Note 1: Right-hand side of the colon is referred to as the effective address Note 2: Each component can be positive or negative (2s complement). SWA.46 23

24 Constructing Addresses Default combinations 16-bit segment and offsets (Table 2-3 in textbook) Segment Offset Special Purpose CS IP Instruction address SS SP and BP Stack address BX, DI, SI, 8-bit number, 16-bit number Data address ES DI String destination address 32-bit segment and offsets (Table 2-4 in textbook) Segment Offset Special Purpose CS EIP Instruction address SS ESP and EBP Stack address EAX, EBX, ECX, EDX, ESI, EDI, 8-bit number, 32-bit number Data address ES EDI String destination address FS No default General address GS No default General address SWA.47 Instruction Format Machine Code SWA.48 24

25 Operands Volumes 2a & 2b IA-32 Intel Architecture Software Developer s Manual, Volume 2a, pp SWA.49 Operands SWA.50 25

26 Operands SWA.51 Operands SWA.52 26

27 SWA.53 SWA.54 27

28 SWA.55 Example 1 Ex 1 (286): MOV AX, [BP] H r16 m16 MOV r16, m16 Volume 2a pp (631) SWA.56 28

29 SWA.57 Example 1 Ex 1 MOV AX, [BP] H 8B Displacement: low-byte first SWA.58 29

30 Example 2 Ex 2 (286): ADD [BP][DI]+1234H, CX Machine Code: 01 8B SWA.59 SWA.60 30

31 Example 3 Ex 5 (Pentium/Core): MOV EAX,[EBX+4*ECX] Result: 8B 04 8B H SWA.61 SWA.62 31

32 SWA.63 Others Ex 4 : SUB BX, 03EFH Result: 81 EB EF 03 H Ex 5 : MOV [1234H], Result: 8C 1E H SWA.64 32

33 Operand Table Examples MOV r/m32, r32 Destination Source MOV [ H], EAX Memory direct Register direct MOV EDX, EAX Register direct Register direct MOV [EBP],ECX Based Register direct MOV r/m16, imm16 Destination Source MOV [ H], A432H Memory direct Immediate MOV DX, A432H Register direct Immediate MOV [EBP], A432H Based Immediate SWA.65 Utilization of registers or displacements Type Base Index Scale Displacement Register Operand Immediate Operand Addressing Modes IA-16 & IA32 No memory address required No memory address required Direct X Register indirect X or X - - Based X - - X Index X - X Based-Index X X - X Scaled-Index 1 - X X X Based Scaled-Index 1 X X X X 1 Only available in the through Pentium 2 Or displacement addressing SWA.66 33

34 Addressing Modes Notation Type Register Operand Immediate Operand Direct Register indirect Based Indexed Based-Indexed Scaled-Indexed Based Scaled-Indexed Instruction MOV AX,BX MOV CH, 3AH MOV [1234H],AX MOV [BX],CL MOV [BX]+10ABH,AL MOV CH, [SI]+88H MOV AX, [BP][DP]+2001H MOV [SI]*2+234H,AX MOV [BX][SI]*4,AH SWA.67 Register Operand Addressing Mode MOV AX,BX IP 008A IP 008C CS SS ES AX BX CX DX 00A0 AB CD 00A8AH 00A8BH 00A8CH 00A8DH 8B C3 CS SS ES AX BX CX DX 00A0 AB CD AB CD 00A8AH 00A8BH 00A8CH 00A8DH 8B C3 SP BP SI DI SP BP SI DI (a) Before execution of instruction (b) After execution of instruction SWA.68 34

35 Immediate Operand Addressing Mode MOV AL,2AH IP 008A IP 008C CS SS ES AX BX CX DX 00A0 00A8AH 00A8BH 00A8CH 00A8DH B0 2A CS SS ES AX BX CX DX 00A0 2A 00A8AH 00A8BH 00A8CH 00A8DH B0 2A SP BP SI DI SP BP SI DI (a) Before execution of instruction (b) After execution of instruction SWA.69 Direct Addressing Mode MOV CX,[10ABH] IP 008A IP 008E CS SS ES AX BX CX DX 00A0 01C0 00A8AH 00A8BH 00A8CH 00A8DH 8B 0E AB 10 CS SS ES AX BX CX DX 00A0 01C0 DA 23 00A8AH 00A8BH 00A8CH 00A8DH 00A8EH 8B 0E AB 10 SP BP SI DI 02CABH 02CACH 23 DA SP BP SI DI 02CABH 02CACH 23 DA (a) Before execution of instruction (b) After execution of instruction SWA.70 35

36 Register Indirect Addressing Mode MOV AX,[SI] IP 008A IP 008C CS SS ES AX BX CX DX 00A0 01C0 00A8AH 00A8BH 00A8CH 00A8DH 8B 04 CS SS ES AX BX CX DX 00A0 01C0 DA 23 00A8AH 00A8BH 00A8CH 00A8DH 8B 04 SP BP SI DI 10AB 02CABH 02CACH 23 DA SP BP SI DI 10AB 02CABH 02CACH 23 DA (a) Before execution of instruction (b) After execution of instruction SWA.71 Based Addressing Mode MOV [BX]+00ACH, AL IP 008A IP 008E CS SS ES AX BX CX DX 00A0 01C0 10 A A8AH 00A8BH 00A8CH 00A8DH 00A8EH AC 00 CS SS ES AX BX CX DX 00A0 01C0 10 A A8AH 00A8BH 00A8CH 00A8DH 00A8EH AC 00 SP BP SI DI 02CABH 02CACH SP BP SI DI 02CABH 02CACH A8 (a) Before fetch and execution of instruction (b) After execution of instruction SWA.72 36

37 Indexed Addressing Mode MOV AL,[SI]+1000H IP 008A IP 008E CS SS ES 00A0 01C0 00A8AH 00A8BH 00A8CH 00A8DH 8A CS SS ES 00A0 01C0 00A8AH 00A8BH 00A8CH 00A8DH 8A AX BX CX DX 00A8EH AX BX CX DX 88 00A8EH SP BP SI DI 00AB 02CABH 02CACH SP BP SI DI 00AB 02CABH 02CACH (a) Before fetch and execution of instruction (b) After execution of instruction SWA.73 Other Examples XOR EAX, [ECX+8*ESI]+1234H PUSH [1426H] ADD BP,[1234H] SUB EAX,[BP] INC [BP]+68H SWA.74 37