Register Files. Single Bus Architecture. Register Files. Single Bus Processor. Term Project: using VHDL. Accumulator based architecture

Transcription

1 Register Files DR 3 SelS Design and simulate the LC-3 processor using VHDL Term Project: Single Processor Decoder... R R3 R mux mux S S SelDR 3 DRin Clock 3 SelS LC-3 Architecture 3 Register File consists of 8 registers: Two -bit output busses: S and S One -bit input bus: DR Register is selected by: SelS selects the register to put on S SelS SelS selects the register to put on S SelDR selects the register to be written via DR when DRin is Behaves as a combinational logic block: SelS or SelS valid => S or S valid after access time. SelS SelDR DR Register Files 3 SelS 3 S SelS 3 SelDR S DR CLK DRin S S Accumulator based architecture R R3 R6 SelS ALUop Single Architecture SelS LC-3 Architecture 2 LC-3 Architecture 4

2 Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? register set how many? what size? how are they used? instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language). Opcodes 5 opcodes Operate instructions:, AND, NOT Instruction Set Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI instructions: BR, JSR, JMP, RET, TRAP some opcodes set/clear condition codes, based on result: N = negative, Z = zero, C = carry Data Types -bit 2 s complement integer Addressing Modes How is the location of an operand specified? non-memory addresses: immediate, register memory addresses: -relative, indirect, base+offset LC-3 Architecture 5 LC-3 Architecture 7 and Registers address space: 2 locations (-bit addresses) addressability: bits Registers temporary storage, accessed in a single machine cycle accessing memory generally takes longer than a single cycle eight general-purpose registers: R - each bits wide is used to store the return address in subroutine jump how many bits to uniquely identify a register? other registers not directly addressable, but used by (and affected by) instructions (program counter), (condition codes), (memory address register), (memory data register) Data Processing Instructions Only three operations:, AND, NOT Source and destination operands are registers These instructions do not reference memory. and AND can use immediate mode, where one operand is hard-wired into the instruction. LC-3 Architecture 6 LC-3 Architecture 8

3 Data Movement Instructions Load -- read data from memory to register LD: -relative mode LDR: base+offset mode LDI: indirect mode Store -- write data from register to memory ST: -relative mode STR: base+offset mode STI: indirect mode Load effective address -- compute address, save in register LEA: immediate mode does not access memory Branch specifies one or more condition codes. If the set bit is specified, the branch is taken. -relative addressing: target address is made by adding signed offset ([8:]) to current. Note: has already been incremented by FETCH stage. Note: Target must be within 256 words of BR instruction. If the branch is not taken, the next sequential instruction is executed. Branch I nstruction x3 R3 2 YES =? NO M[] R3 R LC-3 Architecture 9 LC-3 Architecture Instructions Used to alter the sequence of instructions (by changing the Program Counter) Conditional Branch : BR[nzc] branch is taken if a specified condition is true signed offset is added to to yield new else, the branch is not taken is not changed, points to the next sequential instruction Unconditional Branch : JMP, JSR, RET always changes the LC-3 has three condition code registers: N -- negative Z -- zero C -- carry Condition Codes Set by any instruction that writes a value to a register (, AND, NOT, LD, LDR, LDI, LEA) Exactly one will be set at all times Based on the last instruction that altered a register TRAP changes to the address of an OS service routine routine will return control to the next instruction (after TRAP) LC-3 Architecture LC-3 Architecture 2

4 Instruction Format Immediate Addressing Mode Immediate field is sign-extended opcode reg reg reg opcode reg reg offset5 opcode reg reg offset6 opcode reg offset9,, # SEXT R R3 R6 opcode reg opcode offset opcode offset8 LC-3 Architecture 3 LC-3 Architecture 5 NOT R3, Register Addressing Modes NOT R3 R R3 R6 -Relative Addressing Mode Want to specify address directly in the instruction But an address is bits, and so is an instruction! After subtracting 4 bits for opcode and 3 bits for register, we have 9 bitsavailable for address. Solution: Use the 9 bits as a signed offset from the current. NOT 9 bits: 256 offset Can form any address X, such that: 256 X Remember that is incremented as part of the FETCH phase; This is done before the EVALUATE RESS stage. LC-3 Architecture 4 LC-3 Architecture

5 LD, xaf -Relative Addressing Mode Base + Offset Addressing Mode LDR,, xd LD xaf 9 SEXT R R3 R6 R LDR xd 6 SEXT R3 R6 LC-3 Architecture 7 LC-3 Architecture 9 Base + Offset Addressing Mode With -relative mode, can only address data within 256 words of the instruction. What about the rest of memory? Solution #2: Use a register to generate a full -bit address. 4 bits for opcode, 3 for src/dest register,3 bits for base register -- remaining 6 bits are used as a signed offset. Offset is sign-extended before adding to base register. Indirect Addressing Mode With -relative mode, can only address data within 256 words of the instruction. What about the rest of memory? Solution #: Read address from memory location, then load/store to that address. First address is generated from and (just like relative addressing), then content of that address is used as target for load/store. LC-3 Architecture 8 LC-3 Architecture 2

6 LDI R3, x Indirect Addressing Mode LDI R3 x 9 SEXT R R6 Instruction Set Operation opcode Example Macro-operation Addressing mode Data Processing Data Movement NOT, ~ Register AND,, R3 & R3 Register AND,, #x2 & x2 Immeadate,, R3 + R3 Register,, #x2 + x2 Immeadate LD, x23 M[+x23] Relative LDR,, x2 M[+x2] Base-Offset LDI, x23 M[ M[+x23] ] Indirect LEA, x23 + x23 Relative ST, x23 M[+x23] Relative STR,, x2 M[+x2] Base-Offset STI, x23 M[ M[+x23] ] Indirect Program BR[nzc] x23 If [nzc] + x23 Relative JMP Register JSR ; Register JSR x23 ; + x23 Relative RET Implicit LC-3 Architecture 2 LC-3 Architecture 23 BR N Z C offset9 -Relative DR SR S Register DR S Imm5 Immediate LD DR offset9 -Relative ST Rs offset9 -Relative JSR Base Base register offset -Relative AND DR SR S Register DR S Imm5 Immediate LDR DR Base offset6 Base+offset STR Rs Base offset6 Base+offset NOT DR Rs Register LDI DR offset9 Indirect STI Rs offset9 Indirect JMP Base Base register RET register LEA DR offset9 -Relative TRAP TrapVector8 Psudo-Direct Instruction Set Sample Program Address Instruction Comments x3 x3 (+xff) x3 R3 x32 x33 2 If Z, goto x3a x34 (+5) x35 Load next value to x36 Add to R3 x37 Increment (pointer) Decrement X38 (counter) x39 Goto x34 (-6) LC-3 Architecture 22 LC-3 Architecture 24

7 Program ( of 2) Address Instruction Comments x3 (counter) x3 R3 M[x32] (ptr) x32 Input to R (TRAP x23) x33 M[R3] x34 4 (EOT) Accumulator based architecture R R3 R6 SelS Single Architecture SelS x35 If Z, goto x3e x36 NOT x37 + X38 + R ALUop x39 If N or C, goto x3b LC-3 Architecture 25 LC-3 Architecture 27 Program (2 of 2) Address Instruction Comments x3a + x3b R3 R3 + x3c x3d x3e x3f M[R3] Goto x34 R M[x33] R R + x3 Print R (TRAP x2) x3 HALT (TRAP x25) X32 Starting Address of File x33 ASCII x3 ( ) LC-3 Architecture 26 Basic Single Architecture in R in R6 SelS SelS out in Sel in LC-3 Architecture 28 out bus

8 Register Transfer Logic Register Transfer Logic [5:2] M[] NOT DR ~SR Set BR [:9]&NZC False True +([8:]) AND [5] DR S&S Set DR S&([4:]) Set JMP Base JSR [] Base +([:]) [5] DR S+S Set DR S+([4:]) Set RET TRAP ZExt[[7:]] M[] LC-3 Architecture 29 LC-3 Architecture 3 Register Transfer Logic Instruction Cycle LD +([8:]) M[] DR Set LDI +([8:]) M[] LDR LEA ST STI Base+([5:]) DR +([8:]) Set M[] M[] DR Set DR Set +([8:]) SR M[] +([8:]) M[] Fetch cycle + M[] Execute cycle Execute, AND, NOT, LD, LDI, LDR, LEA, ST, STI, STR, BR JMP, JSR/JSRR, RET, TRAP STR SR M[] Base+([5:]) SR M[] [5:2] LC-3 Architecture 3 LC-3 Architecture 32

9 Architecture NOT (Register) Architecture R in Sel in R6 SelS SelS out R in Sel in R6 SelS SelS out in Sel in out bus DR SR in NOT in Sel in out bus LC-3 Architecture 33 LC-3 Architecture 35 NOT Dst Src NOT (Register) [5:2] NOT DR ~SR Set Dst Src AND Dst Src / AND (Register) this zero means register mode [5:2] [5]= AND DR S&S DR S+S Set Note: Src and Dst could be the same register. LC-3 Architecture 34 LC-3 Architecture 36

10 / AND (Register) Architecture R in Sel in R6 x DR SR S in SelS /AND in SelS out in Sel out bus / AND (Immediate) Architecture R in Sel in R6 x DR S Imm5 in SelS Sel /AND in SelS out Sel in Sel out bus LC-3 Architecture 37 LC-3 Architecture Dst Scr Imm AND Dst Src Imm5 Note: Immediate field is sign-extended. / AND (Immediate) this zero means immediate mode [5:2] [5]= AND DR S&([4:]) DR S+([4:]) Set LD Dst offset9 LD (-Relative) LD [5:2] +([8:]) M[] DR Set LC-3 Architecture 38 LC-3 Architecture 4

11 LD (-Relative) Architecture R in Sel in R6 DR offset9 in SelS Sel in SelS out Sel in Sel LC-3 Architecture 4 out bus LDI (Indirect) Architecture R in Sel in R6 DR offset9 in SelS Sel NOT AND Tr in SelS out Sel in Sel LC-3 Architecture 43 out bus LDI (Indirect) LDR (Base+Offset) LDI Dst offset9 LDR Dst Base offset6 [5:2] [5:2] LDI LDR +([8:]) Base+([5:]) M[] M[] DR Set M[] DR Set LC-3 Architecture 42 LC-3 Architecture 44

12 LDR (Base+Offset) Architecture R in Sel in R6 DR BR Offset6 in SelS Sel NOT AND Tr in SelS out Sel in Sel LC-3 Architecture 45 out bus LEA (-Relative) Architecture R in Sel in R6 DR offset9 in SelS Sel NOT AND Tr in SelS out Sel in Sel LC-3 Architecture 47 out bus LEA (-Relative) ST (-Relative) LEA Dst offset ST Scr offset9 [5:2] [5:2] LEA ST DR +([8:]) Set +([8:]) SR M[] LC-3 Architecture 46 LC-3 Architecture 48

13 ST (-Relative) Architecture R in Sel in R6 SR offset9 in SelS Sel in SelS out Sel in Sel LC-3 Architecture 49 out bus STI (Indirect) Architecture R in Sel in R6 SR offset9 in SelS Sel in SelS out Sel in Sel LC-3 Architecture 5 out bus STI (Indirect) STR (Base+Offset) STI Src offset9 STR Src Base offset6 [5:2] [5:2] STI STR +([8:]) Base+([5:]) M[] SR M[] SR M[] LC-3 Architecture 5 LC-3 Architecture 52

14 STR (Base+Offset) Architecture R in Sel in R6 SR BR Offset6 in SelS Sel in SelS out Sel in Sel LC-3 Architecture 53 out bus BR (-Relative) Architecture R in Sel in R6 NZC offset9 in SelS Sel in SelS out Sel in Sel LC-3 Architecture 55 out bus BR (-Relative) JMP (Register) BR N Z C offset9 Jump is an unconditional branch -- always taken. Target address is the contents of a register. Allows any target address. [5:2] BR [:9]&NZC False JMP Base True +([8:]) [5:2] JMP Base What LC-3 happens Architecture if bits [:9] are all zero? All one? 54 LC-3 Architecture 56

15 JMP (Register) Architecture R in Sel in R6 BR in SelS Sel in SelS out Sel in Sel LC-3 Architecture 57 out bus JSR (Register) Architecture R in Sel in R6 BR in SelS Sel in SelS out Sel in Sel LC-3 Architecture 59 out bus JSR Base JSR offset JSR (Register/ -Relative) Base [5:2] JSR [] +([:]) LC-3 Architecture 58 JSR (-Relative) Architecture R in Sel in R6 offset in SelS Sel in SelS out Sel in Sel LC-3 Architecture 6 out bus

16 RET (Register) TRAP RET TRAP TrapVector8 [5:2] RET Calls a service routine, identified by 8-bit trap vector. vector routine x23 input a character from the keyboard x2 output a character to the monitor x25 halt the program When routine is done, is set to the instruction following TRAP. TRAP [5:2] ZExt[[7:]] M[] LC-3 Architecture 6 LC-3 Architecture 63 RET (Register) Architecture TRAP Architecture R in Sel in R6 in SelS Sel in SelS out Sel in Sel LC-3 Architecture 62 out bus R in Sel in R6 in SelS Sel in SelS out Sel in Sel LC-3 Architecture 64 out bus

17 Complete RTL -mapped Input [5:2] M[] ; NOT AND LD LDI LDR DR ~SR; Set [5] [5] DR S&S; Set DR S&([4:]); Set DR S+S; Set DR S+([4:]); Set +([8:]) M[] DR ; Set +([8:]) M[] M[] DR ; Set Base+([5:]) M[] DR ; Set in Address Logic KBSR KBDR Input ST +([8:]) SR M[] STI STR LEA +([8:]) M[] SR M[] Base+([5:]) SR M[] DR +([8:]); Set BR [:9]&NZC +([8:]) JMP Base JSR [] Base RET +([:]) Sel in out TRAP ZExt[[7:]] M[]; LC-3 Architecture 65 LC-3 Architecture 67 Complete Architecture -mapped Output R in Sel in R6 in SelS Sel NOT AND Tr in SelS out Sel in Sel out bus Sel in out in Address Logic DSR DDR Output LC-3 Architecture 66 LC-3 Architecture 68

18 -mapped I/O revisited Keyboard Echo: combine the above in Sel in Address Logic Address Logic Input KBSR KBDR DSR DDR Output START LDI,KBSR ;Loop if KB not ready BRzp START LDI R,KBDR ;Get character ECHO LDI,CRTSR ;Loop if monitor not ready BRzp ECHO STI R,CRTDR ;Send character BR NEXT_TASK KBSR.FILL xfe ;Address of KBSR KBDR.FILL xfe2 ;Address of KBDR DSR.FILL xfe4 ;Address of DSR DDR.FILL xfe6 ;Address of DDR out LC-3 Architecture 69 LC-3 Architecture 7 Simple Polling Routines START LDI, A ;Loop if Ready not set BRzp START LDI R, B ;If set, load char to R BR NEXT_TASK A.FILL xfe ;Address of KBSR B.FILL xfe2 ;Address of KBDR Input a character from keyboard START LDI, A ;Loop if Ready not set BRzp START STI R, B ;If set, send char to DDR BR NEXT_TASK A.FILL xfe4 ;Address of DSR B.FILL xfe6 ;Address of DDR Example: Print a string LEA, STR ;Load address of string LOOP LDR R,, # ;get next char to R BRZ DONE ;string ends with LP2 LDI R3, DSR ;Loop until MON is ready BRzp LP2 STI R, DDR ;Write next character,, # ; Set address to next char BR LOOP STR.STRINGZ "Char String" DONE HALT Output a character to the monitor LC-3 Architecture 7 LC-3 Architecture 72

19 Complete Architecture Complete Architecture (MUX version) R in Sel in R6 in SelS Sel NOT AND Tr in SelS out Sel in Sel LC-3 Architecture 73 out bus R in Sel in R6 in SelS Sel NOT AND Tr in SelS Sel Sel Sel in LC-3 Architecture 75 2 bus Finite State Machine [5:2] out, in Read, SelMDT=, in Pcout, in, Sel=, in NOT AND LD LDI LDR LEA ST STI SelS=S, SelSrc=, NOT,, SelDR=DR, Drin, in [5] SelS=S, SelSrc=, SelS=S, Sel=, AND,, SelDR=DR, Drin, in SelS=S, SelSrc=, =5, Sel=, AND,, SelDR=DR, Drin, in [5] SelS=S, SelSrc=, SelS=S, Sel=, AND,, SelDR=DR, Drin, in SelS=S, SelSrc=, =5, Sel=, AND,, SelDR=DR, Drin, in, in Read, Sel=, in out, SelDR, Drin, Sel=, =9, Sel=,, in Sel=, =9, Sel=,,, in Read, Sel=, in out, in Read, Sel=, in out, SelDR=DR, Drin, in SelS=BR, Sel=, =6, Sel=,,, in Read, Sel=, in out, SelDR=DR, Drin, in Sel=, =9, Sel=,,, SelDR=DR, Drin, in Sel=, =9, Sel=,,, in SelS=SR, Sel=, Tr,, Sel=, in Write SelS=, =9, SelS=,,, in Read, Sel=, in out, in SelS=SR, Sel=, Tr,, Sel=, in Write STR BR JMP SelS=BR, Sel=, =6, Sel=,,, in SelS=SR, Sel=, Tr,, Sel=, in Write [:9]&NZC SelS=BR, Sel=, Tr,, Sel=, in Sel=, =9, Sel=,, Sel=, in JSR Pcout, SelDR=, DRin [] SelS=BR, Sel=, Tr,, Sel=, in RET SelS=, Sel=; Tr,, Sel=, in Sel=, =, Sel=, Add,, Sel=, in TRAP SelEExt=8, Sel=, Tr,, in Read, Sel=, in, out, SelDR=,DRin out, Sel=, in LC-3 Architecture 74