Chapter 5 - ISA. 1.The Von Neumann Model. The Stored Program Computer. Von Neumann Model. Memory

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1 Chapter 5 - ISA 1.The Von Neumann Model The Stored Program Computer 1943: ENIAC Presper Eckert and John Mauchly -- first general electronic computer. (or was it John V. Atanasoff in 1939?) Hard-wired program -- settings of dials and switches. 1944: Beginnings of EDVAC among other improvements, includes program stored in memory 1945: John von Neumann wrote a report on the stored program concept, known as the First Draft of a Report on EDVAC The basic structure proposed in the draft became known as the von Neumann machine (or model). a memory, containing instructions and data a processing unit, for performing arithmetic and logical operations a control unit, for interpreting instructions For more history, see Von Neumann Model INPUT Keyboard Mouse Scanner Disk MAR MEMORY MDR PROCESSING UNIT ALU TEMP CONTROL UNIT PC IR OUTPUT Monitor Printer LED Disk Memory 2 k x m array of stored bits Address unique (k-bit) identifier of location Contents m-bit value stored in location Basic Operations: LOAD read a value from a memory location STORE write a value to a memory location

2 Interface to Memory How does processing unit get data to/from memory? MAR: Memory Address Register MEMORY MDR: Memory Data Register MAR MDR To LOAD a location (A): 1. Write the address (A) into the MAR. 2. Send a read signal to the memory. 3. Read the data from MDR. To STORE a value (X) to a location (A): 1. Write the data (X) to the MDR. 2. Write the address (A) into the MAR. 3. Send a write signal to the memory. 4-5 Processing Unit Functional Units ALU = Arithmetic and Logic Unit could have many functional units. some of them special-purpose PROCESSING UNIT (multiply, square root, ) LC-3 performs ADD, AND, NOT Registers Small, temporary storage Operands and results of functional units ALU TEMP LC-3 has eight registers (R0,, R7), each 16 bits wide Word Size number of bits normally processed by ALU in one instruction also width of registers LC-3 is 16 bits 4-6 Input and Output Devices for getting data into and out of computer memory Each device has its own interface, usually a set of registers like the memory s MAR and MDR INPUT Keyboard Mouse Scanner Disk LC-3 supports keyboard (input) and monitor (output) keyboard: data register (KBDR) and status register (KBSR) monitor: data register (DDR) and status register (DSR) Some devices provide both input and output disk, network Program that controls access to a device is usually called a driver. OUTPUT Monitor Printer LED Disk 4-7 Control Unit Orchestrates execution of the program CONTROL UNIT Instruction Register (IR) contains the current instruction. Program Counter (PC) contains the address of the next instruction to be executed. Control unit: reads an instruction from memory the instruction s address is in the PC interprets the instruction, generating signals that tell the other components what to do an instruction may take many machine cycles to complete 4-8 PC IR 2

3 Instruction Processing Fetch instruction from memory Decode instruction Evaluate address Fetch operands from memory Execute operation Instruction The instruction is the fundamental unit of work. Specifies two things: opcode: operation to be performed operands: data/locations to be used for operation An instruction is encoded as a sequence of bits. (Just like data!) Often, but not always, instructions have a fixed length, such as 16 or 32 bits. Control unit interprets instruction: generates sequence of control signals to carry out operation. Operation is either executed completely, or not at all. Store result 4-9 A computer s instructions and their formats is known as its Instruction Set Architecture (ISA). 4- Example: LC-3 ADD Instruction LC-3 has 16-bit instructions. Each instruction has a four-bit opcode, bits [15:12]. LC-3 has eight registers (R0-R7) for temporary storage. Sources and destination of ADD are registers. Example: LC-3 LDR Instruction Load instruction -- reads data from memory Base + offset mode: add offset to base register -- result is memory address load from memory address into destination register Add the contents of R2 to the contents of R6, and store the result in R6. Add the value 6 to the contents of R3 to form a memory address. Load the contents of that memory location to R

4 Instruction Processing: FETCH Load next instruction (at address stored in PC) from memory into Instruction Register (IR). Copy contents of PC into MAR. Send read signal to memory. Copy contents of MDR into IR. Then increment PC, so that it points to the next instruction in sequence. PC becomes PC+1. F D EA OP EX Instruction Processing: DECODE First identify the opcode. In LC-3, this is always the first four bits of instruction. A 4-to-16 decoder asserts a control line corresponding to the desired opcode. Depending on opcode, identify other operands from the remaining bits. Example: for LDR, last six bits is offset for ADD, last three bits is source operand #2 F D EA OP EX S S Instruction Processing: EVALUATE ADDRESS For instructions that require memory access, compute address used for access. F Instruction Processing: FETCH OPERANDS Obtain source operands needed to perform operation. F Examples: add offset to base register (as in LDR) add offset to PC add offset to zero D EA Examples: load data from memory (LDR) read data from register file (ADD) D EA OP OP EX EX S S

5 Instruction Processing: EXECUTE Perform the operation, using the source operands. F Instruction Processing: STORE RESULT Write results to destination. (register or memory) F Examples: send operands to ALU and assert ADD signal do nothing (e.g., for loads and stores) D EA OP Examples: result of ADD is placed in destination register result of memory load is placed in destination register for store instruction, data is stored to memory write address to MAR, data to MDR assert WRITE signal to memory D EA OP EX EX S S Changing the Sequence of Instructions In the FETCH phase, we increment the Program Counter by 1. Example: LC-3 JMP Instruction Set the PC to the value contained in a register. This becomes the address of the next instruction to fetch. What if we don t want to always execute the instruction that follows this one? examples: loop, if-then, function call Need special instructions that change the contents of the PC. These are called control instructions. jumps are unconditional -- they always change the PC branches are conditional -- they change the PC only if some condition is true (e.g., the result of an ADD is zero) Load the contents of R3 into the PC

6 Instruction Processing Summary Instructions look just like data -- it s all interpretation. Three basic kinds of instructions: computational instructions (ADD, AND, ) data movement instructions (LD, ST, ) control instructions (JMP, BRnz, ) Control Unit State Diagram The control unit is a state machine. Here is part of a simplified state diagram for the LC-3: Six basic phases of instruction processing: F D EA OP EX S not all phases are needed by every instruction phases may take variable number of machine cycles 4-21 A more complete state diagram is in Appendix C. It will be more understandable after Chapter The LC-3 Instruction Set Architecture ISA = All of the programmer-visible components and operations of the computer memory organization address space -- how may locations can be addressed? addressibility -- how many bits per location? register set how many? what size? how are they used? instruction set opcodes data types addressing modes ISA provides all information needed for someone that wants to write a program in machine language (or translate from a high-level language to machine language)

7 LC-3 Overview: Memory and Registers Memory address space: 2 16 locations (16-bit addresses) addressability: 16 bits Registers temporary storage, accessed in a single machine cycle accessing memory generally takes longer than a single cycle eight general-purpose registers: R0 - R7 each 16 bits wide how many bits to uniquely identify a register? other registers not directly addressable, but used by (and affected by) instructions PC (program counter), condition codes 4-25 LC-3 Overview: Instruction Set Opcodes 15 opcodes Operate instructions: ADD, AND, NOT Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP some opcodes set/clear condition codes, based on result: N = negative, Z = zero, P = positive (> 0) Data Types 16-bit 2 s complement integer Addressing Modes How is the location of an operand specified? non-memory addresses: immediate, register memory addresses: PC-relative, indirect, base+offset 4-26 Operate Instructions Only three operations: ADD, AND, NOT NOT (Register) Source and destination operands are registers These instructions do not reference memory. ADD and AND can use immediate mode, where one operand is hard-wired into the instruction. Will show dataflow diagram with each instruction. illustrates when and where data moves to accomplish the desired operation 4-27 Note: Src and Dst could be the same register

8 ADD/AND (Register) this zero means register mode ADD/AND (Immediate) this one means immediate mode Note: Immediate field is sign-extended Using Operate Instructions With only ADD, AND, NOT How do we subtract? How do we OR? How do we copy from one register to another? How do we initialize a register to zero? Data Movement Instructions Load -- read data from memory to register LD: PC-relative mode LDR: base+offset mode LDI: indirect mode Store -- write data from register to memory ST: PC-relative mode STR: base+offset mode STI: indirect mode Load effective address -- compute address, save in register LEA: immediate mode does not access memory

9 PC-Relative Addressing Mode Want to specify address directly in the instruction But an address is 16 bits, and so is an instruction! After subtracting 4 bits for opcode and 3 bits for register, we have 9 bits available for address. LD (PC-Relative) Solution: Use the 9 bits as a signed offset from the current PC. 9 bits: 256 offset Can form any address X, such that: PC 256 X PC Remember that PC is incremented as part of the FETCH phase This is done before the EVALUATE ADDRESS stage ST (PC-Relative) Indirect Addressing Mode With PC-relative mode, can only address data within 256 words of the instruction. What about the rest of memory? Solution #1: Read address from memory location, then load/store to that address. First address is generated from PC and IR (just like PC-relative addressing), then content of that address is used as target for load/store

10 LDI (Indirect) STI (Indirect) Base + Offset Addressing Mode With PC-relative mode, can only address data within 256 words of the instruction. What about the rest of memory? LDR (Base+Offset) Solution #2: Use a register to generate a full 16-bit address. 4 bits for opcode, 3 for src/dest register, 3 bits for base register -- remaining 6 bits are used as a signed offset. Offset is sign-extended before adding to base register

11 STR (Base+Offset) Load Effective Address Computes address like PC-relative (PC plus signed offset) and stores the result into a register. Note: The address is stored in the register, not the contents of the memory location LEA (Immediate) Example Address x30f6 x30f7 x30f8 x30f9 x30fa x30fb x30fc Instruction Comments R1 PC 3 = x30f4 R2 R = x32 M[PC - 5] R2 M[x30F4] x32 R2 0 R2 R2 + 5 = 5 M[R1+14] R2 M[x32] 5 R3 M[M[x30F4]] R3 M[x32] R opcode

12 Control Instructions Used to alter the sequence of instructions (by changing the Program Counter) Conditional Branch branch is taken if a specified condition is true signed offset is added to PC to yield new PC else, the branch is not taken PC is not changed, points to the next sequential instruction Unconditional Branch (or Jump) always changes the PC TRAP changes PC to the address of an OS service routine routine will return control to the next instruction (after TRAP) 4-45 Condition Codes LC-3 has three condition code registers: N -- negative Z -- zero P -- positive (greater than zero) Set by any instruction that writes a value to a register (ADD, AND, NOT, LD, LDR, LDI, LEA) Exactly one will be set at all times Based on the last instruction that altered a register 4-46 Branch Instruction Branch specifies one or more condition codes. If the set bit is specified, the branch is taken. PC-relative addressing: target address is made by adding signed offset (IR[8:0]) to current PC. Note: PC has already been incremented by FETCH stage. Note: Target must be within 256 words of BR instruction. BR (PC-Relative) If the branch is not taken, the next sequential instruction is executed What happens if bits [11:9] are all zero? All one?

13 Using Branch Instructions Compute sum of 12 integers. Numbers start at location x30. Program starts at location x3000. R1 x30 R3 0 R2 12 YES R2=0? NO R4 M[R1] R3 R3+R4 R1 R1+1 R2 R2-1 Sample Program Address x3000 x3001 Instruction x x x x x x X x Comments R1 x30 (PC+0xFF) R3 0 R2 0 R2 12 If Z, goto x300a (PC+5) Load next value to R4 Add to R3 Increment R1 (pointer) Decrement R2 (counter) Goto x3004 (PC-6) JMP (Register) Jump is an unconditional branch -- always taken. Target address is the contents of a register. Allows any target address. TRAP Calls a service routine, identified by 8-bit trap vector. vector x23 x21 x25 routine input a character from the keyboard output a character to the monitor halt the program When routine is done, PC is set to the instruction following TRAP. (We ll talk about how this works later.)

14 Another Example Count the occurrences of a character in a file Program begins at location x3000 Read character from keyboard Load each character from a file File is a sequence of memory locations Starting address of file is stored in the memory location immediately after the program If file character equals input character, increment counter End of file is indicated by a special ASCII value: EOT (x04) At the end, print the number of characters and halt (assume there will be less than occurrences of the character) A special character used to indicate the end of a sequence is often called a sentinel. Useful when you don t know ahead of time how many times to execute a loop. Flow Chart Count = 0 (R2 = 0) Ptr = 1st file character (R3 = M[x3012]) Input char from keybd (TRAP x23) Load char from file (R1 = M[R3]) Done? YES (R1?= EOT) NO YES Match? NO (R1?= R0) Incr Count (R2 = R2 + 1) Load next char from file (R3 = R3 + 1, R1 = M[R3]) Convert count to ASCII character (R0 = x30, R0 = R2 + R0) Print count (TRAP x21) HALT (TRAP x25) Program (1 of 2) Program (2 of 2) Address Instruction Comments Address Instruction Comments x R2 0 (counter) x300a R2 R2 + 1 x R3 M[x32] (ptr) x300b R3 R3 + 1 x Input to R0 (TRAP x23) x300c R1 M[R3] x R1 M[R3] x300d Goto x3004 x R4 R1 4 (EOT) x300e R0 M[x3013] x If Z, goto x300e x300f R0 R0 + R2 x R1 NOT R1 x Print R0 (TRAP x21) x R1 R1 + 1 x HALT (TRAP x25) X R1 R1 + R0 X3012 Starting Address of File x If N or P, goto x300b x ASCII x30 ( 0 )

15 LC-3 Data Path Revisited Filled arrow = info to be processed. Unfilled arrow = control signal. Data Path Components Global bus special set of wires that carry a 16-bit signal to many components inputs to the bus are tri-state devices, that only place a signal on the bus when they are enabled only one (16-bit) signal should be enabled at any time control unit decides which signal drives the bus any number of components can read the bus register only captures bus data if it is write-enabled by the control unit 4-57 Memory Control and data registers for memory and I/O devices memory: MAR, MDR (also control signal for read/write) 4-58 Data Path Components ALU Accepts inputs from register file and from sign-extended bits from IR (immediate field). Output goes to bus. used by condition code logic, register file, memory Register File Two read addresses (SR1, SR2), one write address (DR) Input from bus result of ALU operation or memory read Two 16-bit outputs used by ALU, PC, memory address data for store instructions passes through ALU Data Path Components PC and PCMUX Three inputs to PC, controlled by PCMUX 1. PC+1 FETCH stage 2. Address adder BR, JMP 3. bus TRAP (discussed later) MAR and MARMUX Two inputs to MAR, controlled by MARMUX 1. Address adder LD/ST, LDR/STR 2. Zero-extended IR[7:0] -- TRAP (discussed later)

16 Data Path Components Condition Code Logic Looks at value on bus and generates N, Z, P signals Registers set only when control unit enables them (LD.CC) only certain instructions set the codes (ADD, AND, NOT, LD, LDI, LDR, LEA) Control Unit Finite State Machine On each machine cycle, changes control signals for next phase of instruction processing who drives the bus? (GatePC, GateALU, ) which registers are write enabled? (LD.IR, LD.REG, ) which operation should ALU perform? (ALUK) Logic includes decoder for opcode, etc Programming Solving Problems using a Computer Methodologies for creating computer programs that perform a desired function. Problem Solving How do we figure out what to tell the computer to do? Convert problem statement into algorithm, using stepwise refinement. Convert algorithm into LC-3 machine instructions. Debugging How do we figure out why it didn t work? Examining registers and memory, setting breakpoints, etc. Time spent on the first can reduce time spent on the second! Stepwise Refinement Also known as systematic decomposition. Start with problem statement: We wish to count the number of occurrences of a character in a file. The character in question is to be input from the keyboard the result is to be displayed on the monitor. Decompose task into a few simpler subtasks. Decompose each subtask into smaller subtasks, and these into even smaller subtasks, etc... until you get to the machine instruction level

17 Problem Statement Because problem statements are written in English, they are sometimes ambiguous and/or incomplete. Where is file located? How big is it, or how do I know when I ve reached the end? How should final count be printed? A decimal number? If the character is a letter, should I count both upper-case and lower-case occurrences? Three Basic Constructs There are three basic ways to decompose a task: Task How do you resolve these issues? Ask the person who wants the problem solved, or Make a decision and document it. Subtask 1 Subtask 2 True Test False condition Subtask 1 Subtask 2 Test condition True Subtask False 4-65 Sequential Conditional Iterative 4-66 Sequential Do Subtask 1 to completion, then do Subtask 2 to completion, etc. Conditional If condition is true, do Subtask 1 else, do Subtask 2. Get character input from keyboard True file char = input? False Count and print the occurrences of a character in a file Examine file and count the number of characters that match Test character. If match, increment counter. Count = Count + 1 Print number to the screen

18 Iterative Do Subtask over and over, as long as the test condition is true. Problem Solving Skills Learn to convert problem statement into step-by-step description of subtasks. Check each element of the file and count the characters that match. more chars to check? True Check next char and count if matches. False Like a puzzle, or a word problem from grammar school math. What is the starting state of the system? What is the desired ending state? How do we move from one state to another? Recognize English words that correlate to three basic constructs: do A then do B sequential if G, then do H conditional for each X, do Y iterative do Z until W iterative LC-3 Control Instructions How do we use LC-3 instructions to encode the three basic constructs? Sequential Instructions naturally flow from one to the next, so no special instruction needed to go from one sequential subtask to the next. Conditional and Iterative Create code that converts condition into N, Z, or P. Example: Condition: Is R0 = R1? Code: Subtract R1 from R0 if equal, Z bit will be set. Then use BR instruction to transfer control to the proper subtask Code for Conditional True Subtask 1 Test Condition Next Subtask False Subtask 2 Exact bits depend on condition being tested Unconditional branch to Next Subtask A B 0000 C D Instruction Generate Condition? C Subtask D Subtask 2 Next Subtask Assuming all addresses are close enough that PC-relative branch can be used. PC offset to address C PC offset to address D

19 Code for Iteration Example: Counting Characters START Test Condition True Subtask Next Subtask False Exact bits depend on condition being tested Unconditional branch to retest condition Assuming all addresses are on the same page. A B C 0000 Instruction Generate Condition? C Subtask A Next Subtask PC offset to address C PC offset to address A 4-73 START Input a character. Then scan a file, counting occurrences of that character. Finally, display on the monitor the number of occurrences of the character (up to 9). STOP Initial refinement: Big task into three sequential subtasks. A B C Initialize: Put initial values into all locations that will be needed to carry out this task. - Input a character. - Set up a pointer to the first location of the file that will be scanned. - Get the first character from the file. - Zero the register that holds the count. Scan the file, location by location, incrementing the counter if the character matches. Display the count on the monitor. STOP 4-74 Refining B Refining B1 B Yes Done? B Yes Done? B Scan the file, location by location, incrementing the counter if the character matches. No B1 Test character. If a match, increment counter. Get next character. Yes Done? No B1 Test character. If a match, increment counter. Get next character. B1 No B2 Test character. If matches, increment counter. B3 Get next character. Refining B into iterative construct. Refining B1 into sequential subtasks

20 Refining B2 and B3 B2 Yes Done? No The Last Step: LC-3 Instructions Use comments to separate into modules and to document your code. B1 Yes Done? No B2 Test character. If matches, increment counter. B3 Get next character. R1 = R0? Yes R2 = R2 + 1 B3 R3 = R3 + 1 R1 = M[R3] No Yes Done? No B2 R1 = R0? Yes R2 = R2 + 1 B3 R3 = R3 + 1 No Look at each char in file is R1 = EOT? 00000xxxxxxxxx if so, exit loop Check for match with R R1 = -char R1 = R0 char 00001xxxxxxxxx no match, skip incr R2 = R2 + 1 Incr file ptr and get next char R3 = R R1 = M[R3] R1 = M[R3] Conditional (B2) and sequential (B3). Use of LC-2 registers and instructions Don t know PCoffset bits until all the code is done 4-78 Debugging You ve written your program and it doesn t work. Now what? What do you do when you re lost in a city? Drive around randomly and hope you find it? Return to a known point and look at a map? In debugging, the equivalent to looking at a map is tracing your program. Examine the sequence of instructions being executed. Keep track of results being produced. Compare result from each instruction to the expected result Debugging Operations Any debugging environment should provide means to: 1. Display values in memory and registers. 2. Deposit values in memory and registers. 3. Execute instruction sequence in a program. 4. Stop execution when desired. Different programming levels offer different tools. High-level languages (C, Java,...) usually have source-code debugging tools. For debugging at the machine instruction level: simulators operating system monitor tools in-circuit emulators (ICE) plug-in hardware replacements that give instruction-level control

21 LC-3 Simulator execute instruction sequences set/display registers and memory stop execution, set breakpoints 4-81 Types of Errors Syntax Errors You made a typing error that resulted in an illegal operation. Not usually an issue with machine language, because almost any bit pattern corresponds to some legal instruction. In high-level languages, these are often caught during the translation from language to machine code. Logic Errors Your program is legal, but wrong, so the results don t match the problem statement. Trace the program to see what s really happening and determine how to get the proper behavior. Data Errors Input data is different than what you expected. Test the program with a wide variety of inputs Tracing the Program Execute the program one piece at a time, examining register and memory to see results at each step. Single-Stepping Execute one instruction at a time. Tedious, but useful to help you verify each step of your program. Breakpoints Tell the simulator to stop executing when it reaches a specific instruction. Check overall results at specific points in the program. Lets you quickly execute sequences to get a high-level overview of the execution behavior. Quickly execute sequences that your believe are correct. Watchpoints Tell the simulator to stop when a register or memory location changes or when it equals a specific value. Useful when you don t know where or when a value is changed Example 1: Multiply This program is supposed to multiply the two unsigned integers in R4 and R5. No clear R2 add R4 to R2 decrement R5 R5 = 0? Yes HALT x x x x x Set R4 =, R5 =3. Run program. Result: R2 = 40, not

22 Debugging the Multiply Program PC and registers at the beginning of each instruction PC x3200 x3201 x3202 x3203 x3201 x3202 x3203 x3201 x3202 x3203 x3201 x3202 x3203 x3204 R R4 R Single-stepping Breakpoint at branch (x3203) PC x3203 x3203 x3203 x3203 R R4 R Should stop looping here! Executing loop one time too many. Branch at x3203 should be based on Z bit only, not Z and P Example 2: Summing an Array of Numbers This program is supposed to sum the numbers stored in locations beginning with x30, leaving the result in R1. No R1 = 0 R4 = R2 = x30 R1 = R1 + M[R2] R2 = R2 + 1 R4 = R4-1 R4 = 0? Yes HALT x x x x x x x x x x Debugging the Summing Program Running the the data below yields R1 = x0024, but the sum should be x8135. What happened? Address x30 x31 x32 x33 x34 x35 x36 x37 x38 x39 Contents x37 x2819 x01 x03 x01 x11 x11b1 x0019 x0007 x0004 Start single-stepping program... PC x3000 x3001 x3002 x3003 x3004 R R x37 R Should be x30! Loading contents of M[x30], not address. Change opcode of x3003 from 00 (LD) to 11 (LEA) Assembly Language 22

23 Human-Readable Machine Language Computers like ones and zeros Humans like symbols ADD R6,R2,R6 increment index reg. Assembler is a program that turns symbols into machine instructions. ISA-specific: close correspondence between symbols and instruction set mnemonics for opcodes labels for memory locations additional operations for allocating storage and initializing data An Assembly Language Program Program to multiply a number by the constant 6.ORIG x3050 LD R1, SIX LD R2, NUMBER AND R3, R3, #0 Clear R3. It will contain the product. The inner loop AGAIN ADD R3, R3, R2 ADD R1, R1, #-1 R1 keeps track of BRp AGAIN the iteration. HALT NUMBER.BLKW 1 SIX.FILL x0006.end LC-3 Assembly Language Syntax Each line of a program is one of the following: an instruction an assember directive (or pseudo-op) a comment Whitespace (between symbols) and case are ignored. Comments (beginning with ) are also ignored. An instruction has the following format: LABEL OPCODE OPERANDS COMMENTS optional mandatory Opcodes and Operands Opcodes reserved symbols that correspond to LC-3 instructions listed in Appendix A ex: ADD, AND, LD, LDR, Operands registers -- specified by Rn, where n is the register number numbers -- indicated by # (decimal) or x (hex) label -- symbolic name of memory location separated by comma number, order, and type correspond to instruction format ex: ADD R1,R1,R3 ADD R1,R1,#3 LD R6,NUMBER BRz LOOP

24 Labels and Comments Label placed at the beginning of the line assigns a symbolic name to the address corresponding to line ex: LOOP ADD R1,R1,#-1 BRp LOOP Comment anything after a semicolon is a comment ignored by assembler used by humans to document/understand programs tips for useful comments: avoid restating the obvious, as decrement R1 provide additional insight, as in accumulate product in R6 use comments to separate pieces of program 4-93 Assembler Directives Pseudo-operations do not refer to operations executed by program used by assembler look like instruction, but opcode starts with dot Opcode.ORIG.END.BLKW.FILL.STRINGZ Operand address n n n-character string Meaning starting address of program end of program allocate n words of storage allocate one word, initialize with value n allocate n+1 locations, initialize w/characters and null terminator 4-94 Trap Codes LC-3 assembler provides pseudo-instructions for each trap code, so you don t have to remember them. Code HALT IN OUT GETC PUTS Equivalent TRAP x25 TRAP x23 TRAP x21 TRAP x20 TRAP x22 Description Halt execution and print message to console. Print prompt on console, read (and echo) one character from keybd. Character stored in R0[7:0]. Write one character (in R0[7:0]) to console. Read one character from keyboard. Character stored in R0[7:0]. Write null-terminated string to console. Address of string is in R Style Guidelines Use the following style guidelines to improve the readability and understandability of your programs: 1. Provide a program header, with author s name, date, etc., and purpose of program. 2. Start labels, opcode, operands, and comments in same column for each line. (Unless entire line is a comment.) 3. Use comments to explain what each register does. 4. Give explanatory comment for most instructions. 5. Use meaningful symbolic names. Mixed upper and lower case for readability. ASCIItoBinary, InputRoutine, SaveR1 6. Provide comments between program sections. 7. Each line must fit on the page -- no wraparound or truncations. Long statements split in aesthetically pleasing manner

25 Sample Program Count the occurrences of a character in a file. Remember this? Count = 0 (R2 = 0) Ptr = 1st file character (R3 = M[x3012]) Input char from keybd (TRAP x23) Load char from file (R1 = M[R3]) YES Incr Count (R2 = R2 + 1) Done? (R1?= EOT) NO Match? (R1?= R0) YES NO Convert count to ASCII character (R0 = x30, R0 = R2 + R0) Print count (TRAP x21) HALT (TRAP x25) Char Count in Assembly Language (1 of 3) Program to count occurrences of a character in a file. Character to be input from the keyboard. Result to be displayed on the monitor. Program only works if no more than 9 occurrences are found. Initialization.ORIG x3000 AND R2, R2, #0 R2 is counter, initially 0 LD R3, PTR R3 is pointer to characters GETC R0 gets character input LDR R1, R3, #0 R1 gets first character Test character for end of file TEST ADD R4, R1, #-4 Test for EOT (ASCII x04) BRz OUTPUT If done, prepare the output Load next char from file (R3 = R3 + 1, R1 = M[R3]) Char Count in Assembly Language (2 of 3) Test character for match. If a match, increment count. NOT R1, R1 ADD R1, R1, R0 If match, R1 = xffff NOT R1, R1 If match, R1 = x0000 BRnp GETCHAR If no match, do not increment ADD R2, R2, #1 Get next character from file. GETCHAR ADD R3, R3, #1 Point to next character. LDR R1, R3, #0 R1 gets next char to test BRnzp TEST Output the count. OUTPUT LD R0, ASCII Load the ASCII template ADD R0, R0, R2 Covert binary count to ASCII OUT HALT ASCII code in R0 is displayed. Halt machine Char Count in Assembly Language (3 of 3) Storage for pointer and ASCII template ASCII.FILL x0030 PTR.FILL x4000.end

26 Assembly Process Convert assembly language file (.asm) into an executable file (.obj) for the LC-3 simulator. First Pass: scan program file find all labels and calculate the corresponding addresses this is called the symbol table Second Pass: convert instructions to machine language, using information from symbol table 4-1 First Pass: Constructing the Symbol Table 1. Find the.orig statement, which tells us the address of the first instruction. Initialize location counter (LC), which keeps track of the current instruction. 2. For each non-empty line in the program: a) If line contains a label, add label and LC to symbol table. b) Increment LC. NOTE: If statement is.blkw or.stringz, increment LC by the number of words allocated. 3. Stop when.end statement is reached. NOTE: A line that contains only a comment is considered an empty line. 4-2 Second Pass: Generating Machine Language For each executable assembly language statement, generate the corresponding machine language instruction. If operand is a label, look up the address from the symbol table. Potential problems: Improper number or type of arguments ex: NOT R1,#7 ADD R1,R2 ADD R3,R3,NUMBER Immediate argument too large ex: ADD R1,R2,#23 Address (associated with label) more than 256 from instruction can t use PC-relative addressing mode Practice Using the symbol table constructed earlier, translate these statements into LC-3 machine language. Statement LD R3,PTR ADD R4,R1,#-4 LDR R1,R3,#0 BRnp GETCHAR Machine Language

27 LC-3 Assembler Using assemble (Unix) or LC3Edit (Windows), generates several different output files. This one gets loaded into the simulator. 4-5 Object File Format LC-3 object file contains Starting address (location where program must be loaded), followed by Machine instructions Example Beginning of count character object file looks like this: ORIG x3000 AND R2, R2, #0 LD R3, PTR TRAP x Multiple Object Files An object file is not necessarily a complete program. system-provided library routines code blocks written by multiple developers For LC-3 simulator, can load multiple object files into memory, then start executing at a desired address. system routines, such as keyboard input, are loaded automatically loaded into system memory, below x3000 user code should be loaded between x3000 and xfdff each object file includes a starting address be careful not to load overlapping object files 4-7 Linking and Loading Loading is the process of copying an executable image into memory. more sophisticated loaders are able to relocate images to fit into available memory must readjust branch targets, load/store addresses Linking is the process of resolving symbols between independent object files. suppose we define a symbol in one module, and want to use it in another some notation, such as.external, is used to tell assembler that a symbol is defined in another module linker will search symbol tables of other modules to resolve symbols and complete code generation before loading