A RECONFIGURABLE BASEBAND FOR 2.5G/3G AND BEYOND

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1 A RECONFIGURABLE BASEBAND FOR 2.5G/3G AND BEYOND John Glossner, Daniel Iancu, Erdem Hokenek, and Mayan Moudgill Sandbridge Technologies, Inc. White Plains, NY ABSTRACT We describe a reconfigurable baseband platform capable of processing WCDMA FDD 2Mbps, b, GPS, and GSM/GPRS communications systems in real-time without requiring special purpose hardware accelerators. In addition, the processor may also perform multimedia functions and Java acceleration without special purpose hardware. Processing is performed completely in software and executes in real-time on the SB9600 baseband platform. INTRODUCTION From the end-user point of view, a modern communications device has a color screen, a keyboard, an antenna, audio, and video. All these features require high computing capability at low power consumption. Adding new features requires adding computing capability. Traditional communications systems have typically been implemented using custom hardware solutions. Chip rate, symbol rate, and bit rate co-processors are often coordinated by programmable DSPs but the DSP processor does not typically participate in computationally intensive tasks. Even with a single communication system the hardware development cycle is onerous often requiring multiple chip redesigns late into the certification process. When multiple communications systems requirements are considered, both silicon area and design validation are major inhibitors to commercial success. A software-based platform capable of dynamically reconfiguring communications systems enables elegant reuse of silicon area and dramatically reduces time to market through software modifications instead of time consuming hardware redesigns. Digital Signal Processors (DSPs) are now capable of executing many billions of operations per second at power efficiency levels appropriate for handset deployment. This has brought Software Defined Radio (SDR) to prominence and addresses a difficult portion of SDR implementation. The advantages of a reconfigurable SDR solution versus hardware solutions are significant. First, reconfigurable solutions are more flexible allowing multiple communication protocols to dynamically execute on the same transistors thereby reducing hardware costs. Specific functions such as filters, modulation schemes, encoders/decoders etc., can be reconfigured adaptively at run time. Second, several communication protocols can be efficiently stored in memory and coexist or execute concurrently. This significantly reduces the cost of the system for both the end user and the service provider. Third, remotely reconfigurable protocols provide simple and inexpensive software version control and feature upgrades. This allows service providers to differentiate products after the product is deployed. Fourth, the development time of new and existing communications protocols is significantly reduced providing an accelerated time to market. Development cycles are not limited by long and laborious hardware design cycles. With SDR, new protocols are quickly added as soon as the software is available for deployment. Fifth, SDR provides an attractive method of dealing with new standards releases while assuring backward compatibility with existing standards. COMMUNICATIONS SYSTEM DESIGN Implementing a third generation wireless technology (3G) design is up to ten times more complex than previous 2/2.5G designs [1][2]. Furthermore, modern communications devices will be required to connect to networks with multiple protocols. A factorial combination of choices presents intractable chip implementations. To facilitate successful system-on-a-chip (SoC) designs requires new approaches to communications systems implementation.

2 PN BT#1 PN BT#2 PN BT#3 CRC attachment TrBk concatenation / Code block segmentation RAKE Searcher De-Scrambler Measurements: SIR MRC Channel coding Path Table Building RSCP ISCP Radio framequalization Timing Management Ec/Io 1 st interleaving Radio frame segmentation Rate matching Rate matching FILTER De- Scramble Channel Est/Derot TrCHMultiplexing 4 Path 3Path DSCH Path 2 S-CCPCH DPCH 4 Path 3Path Path 2 Path 1 Path 1 Physical channel Segmentation 2 nd interleaving Multi Channel Code 2 nd Deinterleaver De-Mux Physical channel mapping Spreading/Scrambling Further Processing 1 nd Deinterleaver Channel Decoding Filter Figure 1. WCDMA Transmission System Available communications design typically contain an ARM processor, a DSP, and many hardware blocks for communications processing (e.g. WCDMA, CMDA-2k, IS-95, GSM, Bluetooth, etc.) and this is just for the modem. Multimedia terminals typically include an additional ARM, an additional DSP, and additional hardware accelerators for multimedia functions. Choosing the proper combination of accelerators poses both implementation challenges and time-to-market constraints. Sandbridge Technologies has chosen to develop a reconfigurable software platform that does not require any additional accelerators for either modem nor multimedia processing. An ARM applications processor is available to run an operating system but the Sandbridge platform replaces all other block with a software approach. The Sandbridge communications design approach begins with Matlab models of both the basestation and the terminal. Within Matlab we implement all conformance testing necessary to ensure that our algorithms perform properly. We then code in high-level ANSI C and use our sophisticated tool chain to immediately produce production executable code. Figure 1 shows the major blocks for both a transmitter and receiver for the UMTS WCDMA FDDmode communication system [1][4]. We choose to focus on WCDMA because it is computationally intensive with tight constraints on latency. The transmit chain (Tx) processing is shown on the left side. Sandbridge has implemented each block completely in software including the output filter. Similarly, the receive chain processing (Rx) is shown on the right. All blocks including the rake receiver, despreading, deinterleaving, and turbo decoding are implemented completely in software. Another important consideration in real-time WCDMA radio design is the generation of RF control signals. Automatic frequency control (AFC) and automatic gain control (AGC) is implemented in software in our design and meets the tight timing requirements specified by UMTS. In a similar manner, we have implemented the physical layer processing for GSM/GPRS, GPS, and b on our platform. All execute in real-time on the SB9600. MULTI-THREADED PROCESSOR Sandbridge Technologies has designed a multithreaded processor capable of executing DSP, Control, and Java code in a single compound instruction set optimized for handset radio applications [5]. The Sandbridge design overcomes the deficiencies of previous approaches by providing substantial parallelism and throughput for high-performance DSP applications while maintaining fast interrupt response, high-level language programmability, and very low power dissipation. As shown in Figure 2, the core includes a unique combination of modern techniques such as a SIMD Vector/DSP unit, a parallel reduction unit, and a RISCbased integer unit. Each processor core provides support for concurrent execution for up to eight threads of execution. All state may be saved from each individual thread and no special software support is required for interrupt processing. The machine is partitioned into a RISC-based control unit that fetches instructions from a set-associative instruction cache. Instruction space is conserved through the use of compounded instructions that are grouped into packets for execution. The cache relieves the programmer of moving large programs into SRAM and avoids overlays that burden software systems. A cache also has the advantage that a programmer need only concern themselves with working

3 Bus/Memory Interface Dir LRU Replace I Cache 64B Lines 4W (2-active) Data Memory Data Data Memory Data Memory Memory Data Data Memory Data Memory Memory 8-Banks I- I- Decode Decode Data Buffer Interrupt CR JTR LCR JumpQ PC AGEN WB LS IQ INT IQ (16) 32-bit GPR SIMDIQ VPR0 VPR1 VPR2 VPR3 LRA LRB IRA IRB Address ALU ADD ADD ADD ADD ACC ACC ACC ACC Figure 2. Sandblaster Processor Core SAT set size (e.g. the dynamic code that predominantly executes) rather than the static instruction size that resides in flash or is downloaded dynamically over the air. The data memory does not use a cache because in most broadband communications systems the data is streamed from A/D converters and passed on for further processing. Analogous to the instruction memory, the data memory also has eight independent banks for concurrent access by each thread. The complete memory system is unified to allow easy software access to any thread data. Special care has been taken in the design of the memory subsystem to reduce power dissipation. The pipeline design in combination with the memory design ensures that all memories are single ported and yet the processor can sustain nearly 4 taps per cycle (the theoretical maximum) in every thread unit simultaneously. A RISC-based execution unit, depicted in the center of Figure 2, assists with control processing. Physical layer processing often consists of control structures with compute-intensive inner loops. A baseband processor must deal with both integer and fractional datatypes. For the control code, a 16 entry, 32-bit register file per thread unit provides for very efficient control processing. Common Integer datatypes are typically stored in the register file. This allows for branch bounds to be computed and addresses to be efficiently generated. Intensive DSP physical layer processing is performed in the SIMD/Vector unit depicted on the right side of Figure 2. Each cycle, a 4x16-bit vector may be loaded into the register file while two vectors are being multiplied, saturated, reduced (e.g. summed), and saturated again. The branch bound may also be computed and the instruction looped on itself until the entire vector is processed. This may be specified in as little as 64-bits. This compares very favorably to VLIW implementations. An important power consideration is that the Vector File contains a single write port for threads. This is in distinct contrast to VLIW implementations that must specify an independent write port for each VLIW instruction (often up to 256-bits with 4 or more write ports). Since write ports contribute significantly to power dissipation, minimizing them is an important consideration in handset design. The Sandblaster core allows any instruction from any thread to be interrupted on any processor cycle. This is critically important to real-time constraints imposed by physical layer processing. The processor also provides special hardware support for a specific thread unit to interrupt another thread unit with very low latency. This low-latency cross-thread interrupt capability enables fast response to time critical events. Parallelism To enable physical layer processing in software, the processor supports many levels of parallelism. Threadlevel parallelism is supported by providing hardware support for up to 8 independent programs to be simultaneously active on a single Sandblaster core. This minimizes the latency in physical layer processing. Since many algorithms have stringent requirements on response time, multithreading is an integral technique in reducing latencies. In addition to thread-level parallelism, the processor also supports data-level parallelism through the use of a Vector unit. In the inner kernel of signal processing or baseband routines, the computations appear as vector operations of moderate length. Filters, FFTs, convolutions, etc., all can be specified in this manner. Efficient, low power support for data level parallelism effectively accelerates inner loop signal processing.

4 To accelerate control code, the processor supports issuing multiple operations per cycle. Since control code often limits overall program speed-up (e.g. Amdahl s Law), it is helpful to allow control code and vector code to be overlapped. This is provided through a compound instruction set and multithreaded organization. The Sandblaster core provides instruction level parallelism by allowing multiple operations to issue in parallel. Thus, a branch, an integer, and a vector operation may all issue simultaneously per thread unit. In addition, many compound operations are specified within an instruction class such as load with update, and branch with compare. Finally, the SB9600 product includes four processor cores per chip to provide enough computational capability to execute the entire 2Mbps WCDMA baseband processing in software in real-time. y-axis shows the number of MHz required to compute frames of speech in real-time. The AMR code is completely unmodified and no special include files are used [8]. Without using any compiler techniques such as intrinsics or special typedefs, the Sandbridge compiler is able to achieve real-time operation on the Sandblaster TM core at hand-coded assembly language performance levels. Note that it is completely compiled from high-level language. Since other solutions are not able to automatically generate DSP operations, intrinsic libraries must be used. With intrinsic libraries the results for most DSPs are near the Sandbridge results but they only apply to the ETSI algorithms whereas the Sandbridge compiler may be applied to arbitrary C code. SANDBRIDGE TECHNOLOGIES COMPILER Sandbridge has built a new compilable DSP and a supercomputer-class vectorizing compiler to go with it [6]. A unique aspect of the Sandbridge compiler is that DSP operations are automatically generated using a technique called semantic analysis. In semantic analysis, a sophisticated compiler must search for the meaning of a sequence of C language constructs. A programmer writes C code in an architecture independent manner - such as for a micro controller - focusing primarily on the function to be implemented. If DSP operations are required, the programmer implements them using standard modulo C arithmetic. The Sandbridge compiler analyzes the C code, automatically extracts the DSP operations and generates optimized DSP code without the excess operations required to specify DSP arithmetic in C code. This technique has a significant software productivity gain over intrinsic functions and does not force the compiler writers to become DSP assembly language programmers [7]. The Sandbridge architecture uses SIMD instructions to implement Vector operations. The compiler vectorizes C code to exploit the data level parallelism inherent in signal processing applications and then generates the appropriate vector instructions. The compiler also handles the difficult problem of outer loop vectorization A final difficult consideration is vectorizing saturating arithmetic. Because saturating arithmetic is non-associative, the order in which the computations are computed is significant. Because the compiler was designed in conjunction with the processor, special hardware support allows the compiler to safely vectorize non-associative loops. Figure 3 shows the results of various compilers on out-of-the-box ETSI C code for state-of-the-art DSPs. The Mhz AMR Encoder SB TI C64x TI C62x SC140 ADI BlackFin DSP's Figure 3. Out-of-the-box AMR ETSI Encoder C code results Ultra-fast Software Simulation Efficient compilation is just one aspect of software productivity. Prior to having processor systems, designers should have access to fast simulation technology. Figure 4 shows the post-compilation simulation performance of the same AMR encoder for a number of DSP processors. All programs were executed on the same 1GHz laptop Pentium computer. The Sandbridge tools are capable of simulating 25+ Million instructions per second. This is more than two orders of magnitude faster than the nearest competitor and allows real-time execution of GSM speech coding on a Pentium simulation model. To further elaborate, while some DSPs can not even execute the outof-box code in real-time on their native processor, Sandbridge achieves multiple real-time channels on a simulation model of processor. We achieved this by using our own compilation technology to accelerate the simulation.

5 RTOS and IDE The programming interface for the Sandbridge processor is generic ANSI C code. In keeping with an easy-to-use programming philosophy, access to multithreading is provided through the open standards of either Java threads or POSIX pthreads [9]. Since nearly all general purpose platforms support these standards it is simple to port programs to the Sandbridge platform. An API is also supported to allow access to the underlying thread scheduler and for fast porting of 3 rd party RTOS s. for b and even concurrent capacity for multiple communications systems. % SB9600 Utilization Millions of Instructions Per Second Simulation Speed (log scale) SB TI C64x (Code Composer) TI C62x(Code Composer) SC140(Metrow erks) ADI Blackfin (Visual DSP) Figure Simulation speed of ETSI AMR Encoder An IDE is also provided based on the opensource Netbeans IDE [10]. Our netbeans implementation has been extended to work with C programs and allows for both Java and C to be debugged using a common environment. RESULTS Sandbridge Technologies has developed complete SDR product, including baseband processor as well as C code for the UMTS 2Mbps WCDMA FDD mode physical layer standard. Using an internally developed compiler, real-time performance on a 768kbps transmit chain and a 2Mbps receive chain has been achieved, which includes all the blocks shown in Figure 1. The entire transmit chain including bit, symbol, and chip rate processing requires less than 400MHz of processor capacity to sustain a 768 kbps transmit capability. Figure 5 shows the performance requirements for , GPRS, and WCDMA as a function of SB9600 utilization for a number of different transmission rates. Providing processing capability for 2Mbps WCDMA FDD-mode also provides sufficient processing capability 0 Figure GPRS WCDMA 1/2/5.5/11Mbps Class 10/12 64/384/2k Kbps Baseband System Performance SUMMARY Sandbridge Technologies has introduced a completely new and scalable design methodology for implementing multiple transmission systems on a single chip. Using a unique multithreaded architecture specifically designed to reduce power consumption, efficient broadband communications operations are executed on a programmable platform. The processor uses completely interlocked instruction execution providing software compatibility among all processors. Because of the interlocked execution, interrupt latency is very short. An interrupt may occur on any instruction boundary including loads and stores. This is critical for real-time systems. The processor is combined with a highly optimizing compiler with the ability to analyze programs and generate DSP instructions. This obviates the need for assembly language programming and significantly accelerates time-to-market for new transmission systems. To validate our approach, we designed our own 2Mbps WCDMA, b, GSM/GPRS, and GPS physical layers. First, we designed a MATLAB implementation to ensure conformance to the 3GPP specifications. We then implemented the algorithms in fixed point C code and compiled them to our platform using our internally developed tools. The executables were then simulated on our cycle accurate simulator that runs at up to 100 million SandBlaster instructions per second on a high end Pentium thereby ensuring complete logical operation. In addition to the software design, we also build RF cards for each communications system. With a complete system, we execute RF to IF to baseband and reverse uplink processing in our lab. Our measurements confirm that our communications designs, including 2Mbps WCDMA, will execute within field conformance

6 requirements in real time completely in software on the SB9600 TM platform. REFERENCES [1] J. Glossner, E. Hokenek, and M. Moudgill, Wireless SDR Solutions: The Challenge and Promise of Next Generation Handsets, Published at the November 2002 Communications Design Conference, San Jose, California. Available at htm. [2] J. Glossner, M. Schulte, and S. Vassiliadis, Towards a Java-enabled 2Mbps Wireless Handheld Device, in Proceedings of the Systems, Architectures, Modeling, and Simulation (SAMOS) Conference, Samos, Greece, July 14-16, [3] 3GPP, 3rd Generation Partnership Project, Technical SpecificationsV3.8.0 ( ) [4] H. Holma and A. Toskala, WCDMA For UMTS Radio Access For Third Generation Mobile Communications, John Wiley & Sons, LTD, 2001 [5] J. Glossner, E. Hokenek, and M. Moudgill, Multithreaded Processor for Software Defined Radio, Proceedings of the 2002 Software Defined Radio Technical Conference, Volume I, pp , November 11-12, 2002, San Diego, California. [6] J. Glossner, D. Iancu, J. Lu, E. Hokenek, and M. Moudgill, A Software Defined Communications Baseband Design, IEEE Communications Magazine, Vol. 41, No. 1, pages , January, [7] S. Jinturkar, J. Glossner, E. Hokenek, and M. Moudgill, Programming the Sandbridge Multithreaded Processor, Accepted for publication at the 2003 Global Signal Processing Expo (GSPx) and International Signal Processing Conference (ISPC), March 31-April 3, 2003, Dallas, Texas. [8] European Telecommunications Standards Institute, Digital cellular telecommunications system, ANSI-C code for the Adaptive Multi Rate (AMR) speech codec (GSM 6.73) ftp://ftp.3gpp.org/specs/archive /06_series/06.73 [9] B. Nichols, D. Buttlar, and J. Proulx-Farrell, Pthreads Programming: A POSIX Standard for Better Multiprocessing, O'Reilly & Associates, Sebastopol, CA, 1 st edition (September 1996). [10] T. Boudreau, J. Glick, S. Greene, J. Woehr, and V. Spurlin, NetBeans: The Definitive Guide, O'Reilly & Associates, Sebastopol, CA, 1 st edition (October 15, 2002).