High performance, power-efficient DSPs based on the TI C64x

Size: px

Start display at page:

Download "High performance, power-efficient DSPs based on the TI C64x"

Chloe Cummings
5 years ago
Views:

1 High performance, power-efficient DSPs based on the TI C64x Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner Rice University RICE UNIVERSITY

2 Recent (2003) Research Results Stream-based programmable processors meet real-time requirements for a set of base-station phy layer algorithms, Map algorithms on stream processors and studied tradeoffs between packing, ALU utilization and memory operations Improve power efficiency in stream processors by adapting compute resources to workload variations and varying voltage and clock frequency to real-time requirements Design exploration between #ALUs and clock frequency to minimize power consumption of the processor S. Rajagopal, S. Rixner, J. R. Cavallaro 'A programmable baseband processor design for software RICE UNIVERSITY2 defined radios, 2002, Paper draft sent previously, rest of the contributions in thesis

3 Recent (2003) Research Results Peak computation rate available : ~200 billion arithmetic operations at 1.2 GHz Estimated Peak Power (0.13 micron) : W at 1.2 GHz Power: W for 32 users, constraint 9 decoding, at 128Kbps/user At 1.2 GHz, 1.4 V 300 mw for 4 users, constraint 7 decoding, at 128Kbps/user At 433 MHz, V RICE UNIVERSITY3

4 Motivation This research could be applied to DSP design! Designing High performance DSPs Power-efficient Adapt computing resources with workload changes Such that Gradual changes in C64x architecture Gradual changes in compilers and tools RICE UNIVERSITY4

5 Levels of changes To allow changes in TI DSPs and tools gradually Changes classified into 3 levels Level 1 : simple, minimum changes (next silicon) Level 2 : intermediate, handover changes (1-2 years) Level 3 : actual proposed changes (2-3 years) We want to go to Level 3 but in steps! RICE UNIVERSITY5

6 Level 1 changes: Power-efficiency RICE UNIVERSITY6

7 Level 1 changes: Power saving features (1) Use Dynamic Voltage and Frequency scaling When workload changes such as Users, data rates, modulation, coding rates, Already in industry : Crusoe, XScale (2) Use Voltage gating to turn off unused resources When units idle for a sufficiently long time Saves static and dynamic power dissipation See example on next page RICE UNIVERSITY7

exploration 2 multipliers turned off to save power Turned off using

8 Turning off ALUs Adders Multipliers Adders Multipliers Instruction Schedule Sleep Instruction Default schedule Schedule after exploration 2 multipliers turned off to save power Turned off using voltage gating to eliminate static and dynamic power dissipation RICE UNIVERSITY8

9 Level 1: Architecture tradeoffs DVS: Advanced voltage regulation scheme Cannot use NMOS pass gates Cannot use tri-state buffers Use at a coarser time scale (once in a million cycles) cycles settling time Voltage gating: Gating device design important Should be able to supply current to gated circuit Use at coarser time scale (once in cycles) 1-10 cycles settling time RICE UNIVERSITY9

10 Level 1: Tools/Programming impact Need a DSP BIOS TASK running continuously which looks at the workload change and changes voltage/frequency using a look-up table in memory Compiler should be made re-targetable Target subset of ALUs and explore static performance with different adder-multiplier schedules Voltage gating using a sleep instruction that the compiler generates for unused ALUs ALUs should be idle for > 100 cycles for this to occur Other resources can be gated off similarly to save static power dissipation Programmer is not aware of these changes RICE UNIVERSITY10

11 Level 2 changes: Performance RICE UNIVERSITY11

12 Solutions to increase DSP performance (1) Increasing clock frequency C64x: ? Easiest solution but limited benefits Not good for power, given cubic dependence with frequency (2) Increasing ALUs Limited instruction level parallelism (ILP) Register file area, ports explosion Compiler issues in extracting more ILP (3) Multiprocessors (MIMD) Usually 3 rd party vendors (except C40-types) RICE UNIVERSITY12

13 DSP multiprocessors DSP DSP ASSP Network Interface Interconnection DSP DSP ASSP Co-Proc s Source: Texas Instruments Wireless Infrastructure Solutions Guide, Pentek, Sundance, C80 RICE UNIVERSITY13

14 Multiprocessing tradeoffs Advantages: Performance, and tools don t have to change!! Load-balancing algorithms on multiple DSPs not straight-forward Burden pushed on to the programmer Not scalable with number of processors difficult to adapt with workload changes Traditional DSPs not built for multiprocessing (except C40-types) I/O impacts throughput, power and area (E)DMA use minimizes the throughput problem Power and area problems still remain R. Baines, The DSP bottleneck, IEEE Communications Magazine, May 1995, pp (outdated?) S. Rajagopal, B. Jones and J.R. Cavallaro, Task partitioning wireless base-station algorithms RICE on UNIVERSITY14 multiple DSPs and FPGAs, ICSPAT 2001

15 Options Chip multiprocessors with SIMD parallelism (Level 3) SIMD parallelism can alleviate load balancing (shown in Level 3) Scalable with processors Automatic SIMD parallelism can be done by the compiler Single chip will alleviate I/O bottlenecks Tool will need changes To get to level 3, intermediate (Level 2) level investigation Level 2 Do SPMD on DSP multiprocessor RICE UNIVERSITY15

16 Texas Instruments C64x DSP C64x Datapath Source: Texas Instruments C64x DSP Generation (sprt236a.pdf) RICE UNIVERSITY16

17 A possible, plausible solution Exploit data parallelism (DP) Available in many wireless algorithms This is what ASICs do! int i,a[n],b[n],sum[n]; // 32 bits short int c[n],d[n],diff[n]; // 16 bits packed for (i = 0; i< 1024; i) { sum[i] = a[i] b[i]; diff[i] = c[i] - d[i]; } Subword ILP DP RICE UNIVERSITY Data Parallelism is defined as the parallelism available after subword packing and loop unrolling 17

18 SPMD multiprocessor DSP C64x Datapath C64x Datapath Same Program running on all DSPs C64x Datapath C64x Datapath RICE UNIVERSITY18

19 Level 2: Architecture tradeoffs C64x s Interconnection could be similar to the ones used by 3 rd party vendors FPGA- based C40 comm ports (Sundance) ~400 MBps VIM modules (Pentek) ~300 MBps Others developed by TI, BlueWave systems RICE UNIVERSITY19

20 Level 2: Tools/Programming impact All DSPs run the same program Programmer thinks of only 1 DSP program Burden now on tools Can use C8x compiler and tool support expertise Integration of C8x and C6x compilers Data parallelism used for SPMD DMA data movement can be left to programmer at this stage to keep data fed to the all the processors MPI (Message Passing) can also be alternatively applied RICE UNIVERSITY20

21 Level 3 changes: Performance and Power RICE UNIVERSITY21

22 A chip multiprocessor (CMP) DSP Internal Memory (L2) ILP Subword Internal Memory L2 Instruction decoder C64x DSP Core (1 cluster) ILP Subword DP Instruction decoder C64x based CMP DSP Core adapt #clusters to DP Identical clusters, same operations. Power-down unused ALUs, clusters RICE UNIVERSITY22

Datapath C64x Datapath C64x Datapath Increasing

23 A 4 cluster CMP using TI C64x C64x Datapath Significant savings possible in area and power C64x Datapath C64x Datapath C64x Datapath Increasing benefits with larger #clusters (8,16,32 clusters) RICE UNIVERSITY23

24 Alternate view of the CMP DSP DMA Controller L2 internal memory Bank 1 Bank 2 Bank C Prefetch Buffers Clusters Of C64x C64x core 0 C64x core 1 C64x core C Instruction decoder Inter-cluster communication network RICE UNIVERSITY24

25 Adapting #clusters to Data Parallelism Adaptive Multiplexer Network Turned off using voltage gating to eliminate static and dynamic power dissipation C C C C No reconfiguration 4: 2 reconfiguration 4:1 reconfiguration All clusters off C C C C C C C RICE UNIVERSITY25

26 Level 3: Architecture tradeoffs Single processor -> SPMD -> SIMD Single chip : Max die size limited to 128 clusters with 8 functional units/cluster at 90 nm technology [estimate] Number of memory banks = #clusters Instruction addition to turn off clusters when data parallelism is insufficient RICE UNIVERSITY26

27 Level 3: Tools/Programming impact Level 2 compiler provides support for data parallelism adapt #clusters to data parallelism for power savings check for loop count index after loop unrolling If less than #clusters, provide instruction to turn off clusters Design of parallel algorithms and mapping important Programmer still writes regular C code Transparent to the programmer Burden on the compiler Automatic DMA data movement to keep data feeding into the arithmetic units RICE UNIVERSITY27

28 Verification of potential benefits Level 3 potential verification using the Imagine stream processor simulator Replacing the C64x DSP with a cluster containing 3, 3 X and a distributed register file RICE UNIVERSITY28

29 Need for adapting to flexibility Base-stations are designed for worst case workload Base-stations rarely operate at worst case workload Adapting the resources to the workload can save power! RICE UNIVERSITY29

30 Example of flexibility needed in workloads Operation count (in GOPs) G base-station (16 Kbps/user) 3G base-station (128 Kbps/user) Note: GOPs refer only to arithmetic computations 0 (4,7) (4,9) (8,7) (8,9) (16,7) (16,9) (32,7) (32,9) (Users, Constraint lengths) Billions of computations per second needed Workload variation from ~1 GOPs for 4 users, constraint 7 viterbi RICE UNIVERSITY30 to ~23 GOPs for 32 users, constraint 9 viterbi

31 Flexibility affects Data Parallelism U - Users, K - constraint length, N - spreading gain, R - decoding rate Workload Estimation Detection Decoding (U,K) f(u,n) f(u,n) f(u,k,r) (4,7) (4,9) (8,7) (8,9) (16,7) (16,9) (32,7) (32,9) Data Parallelism is defined as the parallelism available after subword packing and loop unrolling RICE UNIVERSITY31

32 Cluster utilization variation with workload (4,9) (4,7) Cluster Utilization (8,9) (8,7) (16,9) (16,7) (32,9) (32,7) Cluster Index Cluster utilization variation on a 32-cluster processor (32, 9) = 32 users, constraint length 9 Viterbi RICE UNIVERSITY32

33 Frequency variation with workload Real-time Frequency (in MHz) Mem Stall L2 Stall Busy (4,7) (4,9) (8,7) (8,9) (16,7) (16,9) (32,7) (32,9) RICE UNIVERSITY33

34 Operation DVS when system changes significantly Users, data rates Coarse time scale (every few seconds) Turn off clusters when parallelism changes significantly Parallelism can change within the same algorithm Eg: spreading gain changes during matched filtering Finer time scales (100 s of microseconds) Turn off ALUs when algorithms change significantly estimation, detection, decoding Finer time scales (100 s of microseconds) RICE UNIVERSITY34

35 Power savings: Voltage Gating & Scaling Workload Freq (MHz) Voltage Power Savings (W) Power (W) Savings needed used (V) clocking Memory Clusters New Base (4,7) % (4,9) % (8,7) % (8,9) % (16,7) % (16,9) % (32,7) % (32,9) % Estimated Cluster Power Consumption 78 % Estimated L2 memory Power Consumption 11.5 % Estimated instruction decooder Power Consumption 10.5 % Estimated Chip Area (0.13 micron process) 45.7 mm 2 Power can change from W to 300 mw depending on workload changes RICE UNIVERSITY35

36 How to decide ALUs vs. clock frequency No independent variables Clusters, ALUs, frequency, voltage Trade-offs exist P 2 3 CV f V f P How to find the right combination for lowest power! f a m a m a m 1 cluster 100 clusters c clusters 100 GHz 10 MHz f MHz (A) (B) (C) RICE UNIVERSITY36

37 Setting clusters, adders, multipliers If sufficient DP, linear decrease in frequency with clusters Set clusters depending on DP and execution time estimate To find adders and multipliers, Let compiler schedule algorithm workloads across different numbers of adders and multipliers and let it find execution time Put all numbers in previous equation Compare increase in capacitance due to added ALUs and clusters with benefits in execution time Choose the solution that minimizes the power Details available in Sridhar s thesis RICE UNIVERSITY37

38 Conclusions We propose a step-by-step methodology to design high performance power-efficient DSPs based on the TI 64x architecture Initial results show benefits in power/performance greater than an order-of-magnitude over a conventional C64x We tailor the design to ensure maximum compatibility with TI s C6x architecture and tools We are interested in exploring opportunities in TI for designing and actual fabrication of a chip and associated tool development We are interested in feedback limitations that we have not accounted for Unreasonable assumptions that we have made Recommended reading: S. Rixner et al, A register organization for media processing, HPCA 2000 B. Khailany et al, Exploring the VLSI scalability of stream processors, HPCA 2003 U. J. Kapasi et al, Programmable Stream Processors, IEEE Computer, August 2003 RICE UNIVERSITY38

Flexible wireless communication architectures

Flexible wireless communication architectures Sridhar Rajagopal Department of Electrical and Computer Engineering Rice University, Houston TX Faculty Candidate Seminar Southern Methodist University April